4ecbebd2d7585cc3deb632b138efa366e63451e6
[qemu.git] / hw / misc / exynos4210_rng.c
1 /*
2 * Exynos4210 Pseudo Random Nubmer Generator Emulation
3 *
4 * Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "crypto/random.h"
22 #include "hw/sysbus.h"
23 #include "qapi/error.h"
24 #include "qemu/log.h"
25
26 #define DEBUG_EXYNOS_RNG 0
27
28 #define DPRINTF(fmt, ...) \
29 do { \
30 if (DEBUG_EXYNOS_RNG) { \
31 printf("exynos4210_rng: " fmt, ## __VA_ARGS__); \
32 } \
33 } while (0)
34
35 #define TYPE_EXYNOS4210_RNG "exynos4210.rng"
36 #define EXYNOS4210_RNG(obj) \
37 OBJECT_CHECK(Exynos4210RngState, (obj), TYPE_EXYNOS4210_RNG)
38
39 /*
40 * Exynos4220, PRNG, only polling mode is supported.
41 */
42
43 /* RNG_CONTROL_1 register bitfields, reset value: 0x0 */
44 #define EXYNOS4210_RNG_CONTROL_1_PRNG 0x8
45 #define EXYNOS4210_RNG_CONTROL_1_START_INIT BIT(4)
46 /* RNG_STATUS register bitfields, reset value: 0x1 */
47 #define EXYNOS4210_RNG_STATUS_PRNG_ERROR BIT(7)
48 #define EXYNOS4210_RNG_STATUS_PRNG_DONE BIT(5)
49 #define EXYNOS4210_RNG_STATUS_MSG_DONE BIT(4)
50 #define EXYNOS4210_RNG_STATUS_PARTIAL_DONE BIT(3)
51 #define EXYNOS4210_RNG_STATUS_PRNG_BUSY BIT(2)
52 #define EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE BIT(1)
53 #define EXYNOS4210_RNG_STATUS_BUFFER_READY BIT(0)
54 #define EXYNOS4210_RNG_STATUS_WRITE_MASK (EXYNOS4210_RNG_STATUS_PRNG_DONE \
55 | EXYNOS4210_RNG_STATUS_MSG_DONE \
56 | EXYNOS4210_RNG_STATUS_PARTIAL_DONE)
57
58 #define EXYNOS4210_RNG_CONTROL_1 0x0
59 #define EXYNOS4210_RNG_STATUS 0x10
60 #define EXYNOS4210_RNG_SEED_IN 0x140
61 #define EXYNOS4210_RNG_SEED_IN_OFFSET(n) (EXYNOS4210_RNG_SEED_IN + (n * 0x4))
62 #define EXYNOS4210_RNG_PRNG 0x160
63 #define EXYNOS4210_RNG_PRNG_OFFSET(n) (EXYNOS4210_RNG_PRNG + (n * 0x4))
64
65 #define EXYNOS4210_RNG_PRNG_NUM 5
66
67 #define EXYNOS4210_RNG_REGS_MEM_SIZE 0x200
68
69 typedef struct Exynos4210RngState {
70 SysBusDevice parent_obj;
71 MemoryRegion iomem;
72
73 int32_t randr_value[EXYNOS4210_RNG_PRNG_NUM];
74 /* bits from 0 to EXYNOS4210_RNG_PRNG_NUM if given seed register was set */
75 uint32_t seed_set;
76
77 /* Register values */
78 uint32_t reg_control;
79 uint32_t reg_status;
80 } Exynos4210RngState;
81
82 static bool exynos4210_rng_seed_ready(const Exynos4210RngState *s)
83 {
84 uint32_t mask = MAKE_64BIT_MASK(0, EXYNOS4210_RNG_PRNG_NUM);
85
86 /* Return true if all the seed-set bits are set. */
87 return (s->seed_set & mask) == mask;
88 }
89
90 static void exynos4210_rng_set_seed(Exynos4210RngState *s, unsigned int i,
91 uint64_t val)
92 {
93 /*
94 * We actually ignore the seed and always generate true random numbers.
95 * Theoretically this should not match the device as Exynos has
96 * a Pseudo Random Number Generator but testing shown that it always
97 * generates random numbers regardless of the seed value.
98 */
99 s->seed_set |= BIT(i);
100
101 /* If all seeds were written, update the status to reflect it */
102 if (exynos4210_rng_seed_ready(s)) {
103 s->reg_status |= EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE;
104 } else {
105 s->reg_status &= ~EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE;
106 }
107 }
108
109 static void exynos4210_rng_run_engine(Exynos4210RngState *s)
110 {
111 Error *err = NULL;
112 int ret;
113
114 /* Seed set? */
115 if ((s->reg_status & EXYNOS4210_RNG_STATUS_SEED_SETTING_DONE) == 0) {
116 goto out;
117 }
118
119 /* PRNG engine chosen? */
120 if ((s->reg_control & EXYNOS4210_RNG_CONTROL_1_PRNG) == 0) {
121 goto out;
122 }
123
124 /* PRNG engine started? */
125 if ((s->reg_control & EXYNOS4210_RNG_CONTROL_1_START_INIT) == 0) {
126 goto out;
127 }
128
129 /* Get randoms */
130 ret = qcrypto_random_bytes((uint8_t *)s->randr_value,
131 sizeof(s->randr_value), &err);
132 if (!ret) {
133 /* Notify that PRNG is ready */
134 s->reg_status |= EXYNOS4210_RNG_STATUS_PRNG_DONE;
135 } else {
136 error_report_err(err);
137 }
138
139 out:
140 /* Always clear start engine bit */
141 s->reg_control &= ~EXYNOS4210_RNG_CONTROL_1_START_INIT;
142 }
143
144 static uint64_t exynos4210_rng_read(void *opaque, hwaddr offset,
145 unsigned size)
146 {
147 Exynos4210RngState *s = (Exynos4210RngState *)opaque;
148 uint32_t val = 0;
149
150 assert(size == 4);
151
152 switch (offset) {
153 case EXYNOS4210_RNG_CONTROL_1:
154 val = s->reg_control;
155 break;
156
157 case EXYNOS4210_RNG_STATUS:
158 val = s->reg_status;
159 break;
160
161 case EXYNOS4210_RNG_PRNG_OFFSET(0):
162 case EXYNOS4210_RNG_PRNG_OFFSET(1):
163 case EXYNOS4210_RNG_PRNG_OFFSET(2):
164 case EXYNOS4210_RNG_PRNG_OFFSET(3):
165 case EXYNOS4210_RNG_PRNG_OFFSET(4):
166 val = s->randr_value[(offset - EXYNOS4210_RNG_PRNG_OFFSET(0)) / 4];
167 DPRINTF("returning random @0x%" HWADDR_PRIx ": 0x%" PRIx32 "\n",
168 offset, val);
169 break;
170
171 default:
172 qemu_log_mask(LOG_GUEST_ERROR,
173 "%s: bad read offset 0x%" HWADDR_PRIx "\n",
174 __func__, offset);
175 }
176
177 return val;
178 }
179
180 static void exynos4210_rng_write(void *opaque, hwaddr offset,
181 uint64_t val, unsigned size)
182 {
183 Exynos4210RngState *s = (Exynos4210RngState *)opaque;
184
185 assert(size == 4);
186
187 switch (offset) {
188 case EXYNOS4210_RNG_CONTROL_1:
189 DPRINTF("RNG_CONTROL_1 = 0x%" PRIx64 "\n", val);
190 s->reg_control = val;
191 exynos4210_rng_run_engine(s);
192 break;
193
194 case EXYNOS4210_RNG_STATUS:
195 /* For clearing status fields */
196 s->reg_status &= ~EXYNOS4210_RNG_STATUS_WRITE_MASK;
197 s->reg_status |= val & EXYNOS4210_RNG_STATUS_WRITE_MASK;
198 break;
199
200 case EXYNOS4210_RNG_SEED_IN_OFFSET(0):
201 case EXYNOS4210_RNG_SEED_IN_OFFSET(1):
202 case EXYNOS4210_RNG_SEED_IN_OFFSET(2):
203 case EXYNOS4210_RNG_SEED_IN_OFFSET(3):
204 case EXYNOS4210_RNG_SEED_IN_OFFSET(4):
205 exynos4210_rng_set_seed(s,
206 (offset - EXYNOS4210_RNG_SEED_IN_OFFSET(0)) / 4,
207 val);
208 break;
209
210 default:
211 qemu_log_mask(LOG_GUEST_ERROR,
212 "%s: bad write offset 0x%" HWADDR_PRIx "\n",
213 __func__, offset);
214 }
215 }
216
217 static const MemoryRegionOps exynos4210_rng_ops = {
218 .read = exynos4210_rng_read,
219 .write = exynos4210_rng_write,
220 .endianness = DEVICE_NATIVE_ENDIAN,
221 };
222
223 static void exynos4210_rng_reset(DeviceState *dev)
224 {
225 Exynos4210RngState *s = EXYNOS4210_RNG(dev);
226
227 s->reg_control = 0;
228 s->reg_status = EXYNOS4210_RNG_STATUS_BUFFER_READY;
229 memset(s->randr_value, 0, sizeof(s->randr_value));
230 s->seed_set = 0;
231 }
232
233 static void exynos4210_rng_init(Object *obj)
234 {
235 Exynos4210RngState *s = EXYNOS4210_RNG(obj);
236 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
237
238 memory_region_init_io(&s->iomem, obj, &exynos4210_rng_ops, s,
239 TYPE_EXYNOS4210_RNG, EXYNOS4210_RNG_REGS_MEM_SIZE);
240 sysbus_init_mmio(dev, &s->iomem);
241 }
242
243 static const VMStateDescription exynos4210_rng_vmstate = {
244 .name = TYPE_EXYNOS4210_RNG,
245 .version_id = 1,
246 .minimum_version_id = 1,
247 .fields = (VMStateField[]) {
248 VMSTATE_INT32_ARRAY(randr_value, Exynos4210RngState,
249 EXYNOS4210_RNG_PRNG_NUM),
250 VMSTATE_UINT32(seed_set, Exynos4210RngState),
251 VMSTATE_UINT32(reg_status, Exynos4210RngState),
252 VMSTATE_UINT32(reg_control, Exynos4210RngState),
253 VMSTATE_END_OF_LIST()
254 }
255 };
256
257 static void exynos4210_rng_class_init(ObjectClass *klass, void *data)
258 {
259 DeviceClass *dc = DEVICE_CLASS(klass);
260
261 dc->reset = exynos4210_rng_reset;
262 dc->vmsd = &exynos4210_rng_vmstate;
263 }
264
265 static const TypeInfo exynos4210_rng_info = {
266 .name = TYPE_EXYNOS4210_RNG,
267 .parent = TYPE_SYS_BUS_DEVICE,
268 .instance_size = sizeof(Exynos4210RngState),
269 .instance_init = exynos4210_rng_init,
270 .class_init = exynos4210_rng_class_init,
271 };
272
273 static void exynos4210_rng_register(void)
274 {
275 type_register_static(&exynos4210_rng_info);
276 }
277
278 type_init(exynos4210_rng_register)