macio: Fix to realize "mos6522-cuda" and "mos6522-pmu" devices
[qemu.git] / hw / misc / macio / pmu.c
1 /*
2 * QEMU PowerMac PMU device support
3 *
4 * Copyright (c) 2016 Benjamin Herrenschmidt, IBM Corp.
5 * Copyright (c) 2018 Mark Cave-Ayland
6 *
7 * Based on the CUDA device by:
8 *
9 * Copyright (c) 2004-2007 Fabrice Bellard
10 * Copyright (c) 2007 Jocelyn Mayer
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a copy
13 * of this software and associated documentation files (the "Software"), to deal
14 * in the Software without restriction, including without limitation the rights
15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
16 * copies of the Software, and to permit persons to whom the Software is
17 * furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice shall be included in
20 * all copies or substantial portions of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28 * THE SOFTWARE.
29 */
30
31 #include "qemu/osdep.h"
32 #include "qemu-common.h"
33 #include "hw/ppc/mac.h"
34 #include "hw/qdev-properties.h"
35 #include "migration/vmstate.h"
36 #include "hw/input/adb.h"
37 #include "hw/irq.h"
38 #include "hw/misc/mos6522.h"
39 #include "hw/misc/macio/gpio.h"
40 #include "hw/misc/macio/pmu.h"
41 #include "qemu/timer.h"
42 #include "sysemu/runstate.h"
43 #include "qapi/error.h"
44 #include "qemu/cutils.h"
45 #include "qemu/log.h"
46 #include "qemu/module.h"
47 #include "trace.h"
48
49
50 /* Bits in B data register: all active low */
51 #define TACK 0x08 /* Transfer request (input) */
52 #define TREQ 0x10 /* Transfer acknowledge (output) */
53
54 /* PMU returns time_t's offset from Jan 1, 1904, not 1970 */
55 #define RTC_OFFSET 2082844800
56
57 #define VIA_TIMER_FREQ (4700000 / 6)
58
59 static void via_update_irq(PMUState *s)
60 {
61 MOS6522PMUState *mps = MOS6522_PMU(&s->mos6522_pmu);
62 MOS6522State *ms = MOS6522(mps);
63
64 bool new_state = !!(ms->ifr & ms->ier & (SR_INT | T1_INT | T2_INT));
65
66 if (new_state != s->via_irq_state) {
67 s->via_irq_state = new_state;
68 qemu_set_irq(s->via_irq, new_state);
69 }
70 }
71
72 static void via_set_sr_int(void *opaque)
73 {
74 PMUState *s = opaque;
75 MOS6522PMUState *mps = MOS6522_PMU(&s->mos6522_pmu);
76 MOS6522State *ms = MOS6522(mps);
77 MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(ms);
78
79 mdc->set_sr_int(ms);
80 }
81
82 static void pmu_update_extirq(PMUState *s)
83 {
84 if ((s->intbits & s->intmask) != 0) {
85 macio_set_gpio(s->gpio, 1, false);
86 } else {
87 macio_set_gpio(s->gpio, 1, true);
88 }
89 }
90
91 static void pmu_adb_poll(void *opaque)
92 {
93 PMUState *s = opaque;
94 int olen;
95
96 if (!(s->intbits & PMU_INT_ADB)) {
97 olen = adb_poll(&s->adb_bus, s->adb_reply, s->adb_poll_mask);
98 trace_pmu_adb_poll(olen);
99
100 if (olen > 0) {
101 s->adb_reply_size = olen;
102 s->intbits |= PMU_INT_ADB | PMU_INT_ADB_AUTO;
103 pmu_update_extirq(s);
104 }
105 }
106
107 timer_mod(s->adb_poll_timer,
108 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 30);
109 }
110
111 static void pmu_one_sec_timer(void *opaque)
112 {
113 PMUState *s = opaque;
114
115 trace_pmu_one_sec_timer();
116
117 s->intbits |= PMU_INT_TICK;
118 pmu_update_extirq(s);
119 s->one_sec_target += 1000;
120
121 timer_mod(s->one_sec_timer, s->one_sec_target);
122 }
123
124 static void pmu_cmd_int_ack(PMUState *s,
125 const uint8_t *in_data, uint8_t in_len,
126 uint8_t *out_data, uint8_t *out_len)
127 {
128 if (in_len != 0) {
129 qemu_log_mask(LOG_GUEST_ERROR,
130 "PMU: INT_ACK command, invalid len: %d want: 0\n",
131 in_len);
132 return;
133 }
134
135 /* Make appropriate reply packet */
136 if (s->intbits & PMU_INT_ADB) {
137 if (!s->adb_reply_size) {
138 qemu_log_mask(LOG_GUEST_ERROR,
139 "Odd, PMU_INT_ADB set with no reply in buffer\n");
140 }
141
142 memcpy(out_data + 1, s->adb_reply, s->adb_reply_size);
143 out_data[0] = s->intbits & (PMU_INT_ADB | PMU_INT_ADB_AUTO);
144 *out_len = s->adb_reply_size + 1;
145 s->intbits &= ~(PMU_INT_ADB | PMU_INT_ADB_AUTO);
146 s->adb_reply_size = 0;
147 } else {
148 out_data[0] = s->intbits;
149 s->intbits = 0;
150 *out_len = 1;
151 }
152
153 pmu_update_extirq(s);
154 }
155
156 static void pmu_cmd_set_int_mask(PMUState *s,
157 const uint8_t *in_data, uint8_t in_len,
158 uint8_t *out_data, uint8_t *out_len)
159 {
160 if (in_len != 1) {
161 qemu_log_mask(LOG_GUEST_ERROR,
162 "PMU: SET_INT_MASK command, invalid len: %d want: 1\n",
163 in_len);
164 return;
165 }
166
167 trace_pmu_cmd_set_int_mask(s->intmask);
168 s->intmask = in_data[0];
169
170 pmu_update_extirq(s);
171 }
172
173 static void pmu_cmd_set_adb_autopoll(PMUState *s, uint16_t mask)
174 {
175 trace_pmu_cmd_set_adb_autopoll(mask);
176
177 if (s->autopoll_mask == mask) {
178 return;
179 }
180
181 s->autopoll_mask = mask;
182 if (mask) {
183 timer_mod(s->adb_poll_timer,
184 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 30);
185 } else {
186 timer_del(s->adb_poll_timer);
187 }
188 }
189
190 static void pmu_cmd_adb(PMUState *s,
191 const uint8_t *in_data, uint8_t in_len,
192 uint8_t *out_data, uint8_t *out_len)
193 {
194 int len, adblen;
195 uint8_t adb_cmd[255];
196
197 if (in_len < 2) {
198 qemu_log_mask(LOG_GUEST_ERROR,
199 "PMU: ADB PACKET, invalid len: %d want at least 2\n",
200 in_len);
201 return;
202 }
203
204 *out_len = 0;
205
206 if (!s->has_adb) {
207 trace_pmu_cmd_adb_nobus();
208 return;
209 }
210
211 /* Set autopoll is a special form of the command */
212 if (in_data[0] == 0 && in_data[1] == 0x86) {
213 uint16_t mask = in_data[2];
214 mask = (mask << 8) | in_data[3];
215 if (in_len != 4) {
216 qemu_log_mask(LOG_GUEST_ERROR,
217 "PMU: ADB Autopoll requires 4 bytes, got %d\n",
218 in_len);
219 return;
220 }
221
222 pmu_cmd_set_adb_autopoll(s, mask);
223 return;
224 }
225
226 trace_pmu_cmd_adb_request(in_len, in_data[0], in_data[1], in_data[2],
227 in_data[3], in_data[4]);
228
229 *out_len = 0;
230
231 /* Check ADB len */
232 adblen = in_data[2];
233 if (adblen > (in_len - 3)) {
234 qemu_log_mask(LOG_GUEST_ERROR,
235 "PMU: ADB len is %d > %d (in_len -3)...erroring\n",
236 adblen, in_len - 3);
237 len = -1;
238 } else if (adblen > 252) {
239 qemu_log_mask(LOG_GUEST_ERROR, "PMU: ADB command too big!\n");
240 len = -1;
241 } else {
242 /* Format command */
243 adb_cmd[0] = in_data[0];
244 memcpy(&adb_cmd[1], &in_data[3], in_len - 3);
245 len = adb_request(&s->adb_bus, s->adb_reply + 2, adb_cmd, in_len - 2);
246
247 trace_pmu_cmd_adb_reply(len);
248 }
249
250 if (len > 0) {
251 /* XXX Check this */
252 s->adb_reply_size = len + 2;
253 s->adb_reply[0] = 0x01;
254 s->adb_reply[1] = len;
255 } else {
256 /* XXX Check this */
257 s->adb_reply_size = 1;
258 s->adb_reply[0] = 0x00;
259 }
260
261 s->intbits |= PMU_INT_ADB;
262 pmu_update_extirq(s);
263 }
264
265 static void pmu_cmd_adb_poll_off(PMUState *s,
266 const uint8_t *in_data, uint8_t in_len,
267 uint8_t *out_data, uint8_t *out_len)
268 {
269 if (in_len != 0) {
270 qemu_log_mask(LOG_GUEST_ERROR,
271 "PMU: ADB POLL OFF command, invalid len: %d want: 0\n",
272 in_len);
273 return;
274 }
275
276 if (s->has_adb && s->autopoll_mask) {
277 timer_del(s->adb_poll_timer);
278 s->autopoll_mask = false;
279 }
280 }
281
282 static void pmu_cmd_shutdown(PMUState *s,
283 const uint8_t *in_data, uint8_t in_len,
284 uint8_t *out_data, uint8_t *out_len)
285 {
286 if (in_len != 4) {
287 qemu_log_mask(LOG_GUEST_ERROR,
288 "PMU: SHUTDOWN command, invalid len: %d want: 4\n",
289 in_len);
290 return;
291 }
292
293 *out_len = 1;
294 out_data[0] = 0;
295
296 if (in_data[0] != 'M' || in_data[1] != 'A' || in_data[2] != 'T' ||
297 in_data[3] != 'T') {
298
299 qemu_log_mask(LOG_GUEST_ERROR,
300 "PMU: SHUTDOWN command, Bad MATT signature\n");
301 return;
302 }
303
304 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
305 }
306
307 static void pmu_cmd_reset(PMUState *s,
308 const uint8_t *in_data, uint8_t in_len,
309 uint8_t *out_data, uint8_t *out_len)
310 {
311 if (in_len != 0) {
312 qemu_log_mask(LOG_GUEST_ERROR,
313 "PMU: RESET command, invalid len: %d want: 0\n",
314 in_len);
315 return;
316 }
317
318 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
319 }
320
321 static void pmu_cmd_get_rtc(PMUState *s,
322 const uint8_t *in_data, uint8_t in_len,
323 uint8_t *out_data, uint8_t *out_len)
324 {
325 uint32_t ti;
326
327 if (in_len != 0) {
328 qemu_log_mask(LOG_GUEST_ERROR,
329 "PMU: GET_RTC command, invalid len: %d want: 0\n",
330 in_len);
331 return;
332 }
333
334 ti = s->tick_offset + (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)
335 / NANOSECONDS_PER_SECOND);
336 out_data[0] = ti >> 24;
337 out_data[1] = ti >> 16;
338 out_data[2] = ti >> 8;
339 out_data[3] = ti;
340 *out_len = 4;
341 }
342
343 static void pmu_cmd_set_rtc(PMUState *s,
344 const uint8_t *in_data, uint8_t in_len,
345 uint8_t *out_data, uint8_t *out_len)
346 {
347 uint32_t ti;
348
349 if (in_len != 4) {
350 qemu_log_mask(LOG_GUEST_ERROR,
351 "PMU: SET_RTC command, invalid len: %d want: 4\n",
352 in_len);
353 return;
354 }
355
356 ti = (((uint32_t)in_data[0]) << 24) + (((uint32_t)in_data[1]) << 16)
357 + (((uint32_t)in_data[2]) << 8) + in_data[3];
358
359 s->tick_offset = ti - (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)
360 / NANOSECONDS_PER_SECOND);
361 }
362
363 static void pmu_cmd_system_ready(PMUState *s,
364 const uint8_t *in_data, uint8_t in_len,
365 uint8_t *out_data, uint8_t *out_len)
366 {
367 /* Do nothing */
368 }
369
370 static void pmu_cmd_get_version(PMUState *s,
371 const uint8_t *in_data, uint8_t in_len,
372 uint8_t *out_data, uint8_t *out_len)
373 {
374 *out_len = 1;
375 *out_data = 1; /* ??? Check what Apple does */
376 }
377
378 static void pmu_cmd_power_events(PMUState *s,
379 const uint8_t *in_data, uint8_t in_len,
380 uint8_t *out_data, uint8_t *out_len)
381 {
382 if (in_len < 1) {
383 qemu_log_mask(LOG_GUEST_ERROR,
384 "PMU: POWER EVENTS command, invalid len %d, want at least 1\n",
385 in_len);
386 return;
387 }
388
389 switch (in_data[0]) {
390 /* Dummies for now */
391 case PMU_PWR_GET_POWERUP_EVENTS:
392 *out_len = 2;
393 out_data[0] = 0;
394 out_data[1] = 0;
395 break;
396 case PMU_PWR_SET_POWERUP_EVENTS:
397 case PMU_PWR_CLR_POWERUP_EVENTS:
398 break;
399 case PMU_PWR_GET_WAKEUP_EVENTS:
400 *out_len = 2;
401 out_data[0] = 0;
402 out_data[1] = 0;
403 break;
404 case PMU_PWR_SET_WAKEUP_EVENTS:
405 case PMU_PWR_CLR_WAKEUP_EVENTS:
406 break;
407 default:
408 qemu_log_mask(LOG_GUEST_ERROR,
409 "PMU: POWER EVENTS unknown subcommand 0x%02x\n",
410 in_data[0]);
411 }
412 }
413
414 static void pmu_cmd_get_cover(PMUState *s,
415 const uint8_t *in_data, uint8_t in_len,
416 uint8_t *out_data, uint8_t *out_len)
417 {
418 /* Not 100% sure here, will have to check what a real Mac
419 * returns other than byte 0 bit 0 is LID closed on laptops
420 */
421 *out_len = 1;
422 *out_data = 0x00;
423 }
424
425 static void pmu_cmd_download_status(PMUState *s,
426 const uint8_t *in_data, uint8_t in_len,
427 uint8_t *out_data, uint8_t *out_len)
428 {
429 /* This has to do with PMU firmware updates as far as I can tell.
430 *
431 * We return 0x62 which is what OpenPMU expects
432 */
433 *out_len = 1;
434 *out_data = 0x62;
435 }
436
437 static void pmu_cmd_read_pmu_ram(PMUState *s,
438 const uint8_t *in_data, uint8_t in_len,
439 uint8_t *out_data, uint8_t *out_len)
440 {
441 if (in_len < 3) {
442 qemu_log_mask(LOG_GUEST_ERROR,
443 "PMU: READ_PMU_RAM command, invalid len %d, expected 3\n",
444 in_len);
445 return;
446 }
447
448 qemu_log_mask(LOG_GUEST_ERROR,
449 "PMU: Unsupported READ_PMU_RAM, args: %02x %02x %02x\n",
450 in_data[0], in_data[1], in_data[2]);
451
452 *out_len = 0;
453 }
454
455 /* description of commands */
456 typedef struct PMUCmdHandler {
457 uint8_t command;
458 const char *name;
459 void (*handler)(PMUState *s,
460 const uint8_t *in_args, uint8_t in_len,
461 uint8_t *out_args, uint8_t *out_len);
462 } PMUCmdHandler;
463
464 static const PMUCmdHandler PMUCmdHandlers[] = {
465 { PMU_INT_ACK, "INT ACK", pmu_cmd_int_ack },
466 { PMU_SET_INTR_MASK, "SET INT MASK", pmu_cmd_set_int_mask },
467 { PMU_ADB_CMD, "ADB COMMAND", pmu_cmd_adb },
468 { PMU_ADB_POLL_OFF, "ADB POLL OFF", pmu_cmd_adb_poll_off },
469 { PMU_RESET, "REBOOT", pmu_cmd_reset },
470 { PMU_SHUTDOWN, "SHUTDOWN", pmu_cmd_shutdown },
471 { PMU_READ_RTC, "GET RTC", pmu_cmd_get_rtc },
472 { PMU_SET_RTC, "SET RTC", pmu_cmd_set_rtc },
473 { PMU_SYSTEM_READY, "SYSTEM READY", pmu_cmd_system_ready },
474 { PMU_GET_VERSION, "GET VERSION", pmu_cmd_get_version },
475 { PMU_POWER_EVENTS, "POWER EVENTS", pmu_cmd_power_events },
476 { PMU_GET_COVER, "GET_COVER", pmu_cmd_get_cover },
477 { PMU_DOWNLOAD_STATUS, "DOWNLOAD STATUS", pmu_cmd_download_status },
478 { PMU_READ_PMU_RAM, "READ PMGR RAM", pmu_cmd_read_pmu_ram },
479 };
480
481 static void pmu_dispatch_cmd(PMUState *s)
482 {
483 unsigned int i;
484
485 /* No response by default */
486 s->cmd_rsp_sz = 0;
487
488 for (i = 0; i < ARRAY_SIZE(PMUCmdHandlers); i++) {
489 const PMUCmdHandler *desc = &PMUCmdHandlers[i];
490
491 if (desc->command != s->cmd) {
492 continue;
493 }
494
495 trace_pmu_dispatch_cmd(desc->name);
496 desc->handler(s, s->cmd_buf, s->cmd_buf_pos,
497 s->cmd_rsp, &s->cmd_rsp_sz);
498
499 if (s->rsplen != -1 && s->rsplen != s->cmd_rsp_sz) {
500 trace_pmu_debug_protocol_string("QEMU internal cmd resp mismatch!");
501 } else {
502 trace_pmu_debug_protocol_resp_size(s->cmd_rsp_sz);
503 }
504
505 return;
506 }
507
508 trace_pmu_dispatch_unknown_cmd(s->cmd);
509
510 /* Manufacture fake response with 0's */
511 if (s->rsplen == -1) {
512 s->cmd_rsp_sz = 0;
513 } else {
514 s->cmd_rsp_sz = s->rsplen;
515 memset(s->cmd_rsp, 0, s->rsplen);
516 }
517 }
518
519 static void pmu_update(PMUState *s)
520 {
521 MOS6522PMUState *mps = &s->mos6522_pmu;
522 MOS6522State *ms = MOS6522(mps);
523
524 /* Only react to changes in reg B */
525 if (ms->b == s->last_b) {
526 return;
527 }
528 s->last_b = ms->b;
529
530 /* Check the TREQ / TACK state */
531 switch (ms->b & (TREQ | TACK)) {
532 case TREQ:
533 /* This is an ack release, handle it and bail out */
534 ms->b |= TACK;
535 s->last_b = ms->b;
536
537 trace_pmu_debug_protocol_string("handshake: TREQ high, setting TACK");
538 return;
539 case TACK:
540 /* This is a valid request, handle below */
541 break;
542 case TREQ | TACK:
543 /* This is an idle state */
544 return;
545 default:
546 /* Invalid state, log and ignore */
547 trace_pmu_debug_protocol_error(ms->b);
548 return;
549 }
550
551 /* If we wanted to handle commands asynchronously, this is where
552 * we would delay the clearing of TACK until we are ready to send
553 * the response
554 */
555
556 /* We have a request, handshake TACK so we don't stay in
557 * an invalid state. If we were concurrent with the OS we
558 * should only do this after we grabbed the SR but that isn't
559 * a problem here.
560 */
561
562 trace_pmu_debug_protocol_clear_treq(s->cmd_state);
563
564 ms->b &= ~TACK;
565 s->last_b = ms->b;
566
567 /* Act according to state */
568 switch (s->cmd_state) {
569 case pmu_state_idle:
570 if (!(ms->acr & SR_OUT)) {
571 trace_pmu_debug_protocol_string("protocol error! "
572 "state idle, ACR reading");
573 break;
574 }
575
576 s->cmd = ms->sr;
577 via_set_sr_int(s);
578 s->cmdlen = pmu_data_len[s->cmd][0];
579 s->rsplen = pmu_data_len[s->cmd][1];
580 s->cmd_buf_pos = 0;
581 s->cmd_rsp_pos = 0;
582 s->cmd_state = pmu_state_cmd;
583
584 trace_pmu_debug_protocol_cmd(s->cmd, s->cmdlen, s->rsplen);
585 break;
586
587 case pmu_state_cmd:
588 if (!(ms->acr & SR_OUT)) {
589 trace_pmu_debug_protocol_string("protocol error! "
590 "state cmd, ACR reading");
591 break;
592 }
593
594 if (s->cmdlen == -1) {
595 trace_pmu_debug_protocol_cmdlen(ms->sr);
596
597 s->cmdlen = ms->sr;
598 if (s->cmdlen > sizeof(s->cmd_buf)) {
599 trace_pmu_debug_protocol_cmd_toobig(s->cmdlen);
600 }
601 } else if (s->cmd_buf_pos < sizeof(s->cmd_buf)) {
602 s->cmd_buf[s->cmd_buf_pos++] = ms->sr;
603 }
604
605 via_set_sr_int(s);
606 break;
607
608 case pmu_state_rsp:
609 if (ms->acr & SR_OUT) {
610 trace_pmu_debug_protocol_string("protocol error! "
611 "state resp, ACR writing");
612 break;
613 }
614
615 if (s->rsplen == -1) {
616 trace_pmu_debug_protocol_cmd_send_resp_size(s->cmd_rsp_sz);
617
618 ms->sr = s->cmd_rsp_sz;
619 s->rsplen = s->cmd_rsp_sz;
620 } else if (s->cmd_rsp_pos < s->cmd_rsp_sz) {
621 trace_pmu_debug_protocol_cmd_send_resp(s->cmd_rsp_pos, s->rsplen);
622
623 ms->sr = s->cmd_rsp[s->cmd_rsp_pos++];
624 }
625
626 via_set_sr_int(s);
627 break;
628 }
629
630 /* Check for state completion */
631 if (s->cmd_state == pmu_state_cmd && s->cmdlen == s->cmd_buf_pos) {
632 trace_pmu_debug_protocol_string("Command reception complete, "
633 "dispatching...");
634
635 pmu_dispatch_cmd(s);
636 s->cmd_state = pmu_state_rsp;
637 }
638
639 if (s->cmd_state == pmu_state_rsp && s->rsplen == s->cmd_rsp_pos) {
640 trace_pmu_debug_protocol_cmd_resp_complete(ms->ier);
641
642 s->cmd_state = pmu_state_idle;
643 }
644 }
645
646 static uint64_t mos6522_pmu_read(void *opaque, hwaddr addr, unsigned size)
647 {
648 PMUState *s = opaque;
649 MOS6522PMUState *mps = &s->mos6522_pmu;
650 MOS6522State *ms = MOS6522(mps);
651
652 addr = (addr >> 9) & 0xf;
653 return mos6522_read(ms, addr, size);
654 }
655
656 static void mos6522_pmu_write(void *opaque, hwaddr addr, uint64_t val,
657 unsigned size)
658 {
659 PMUState *s = opaque;
660 MOS6522PMUState *mps = &s->mos6522_pmu;
661 MOS6522State *ms = MOS6522(mps);
662
663 addr = (addr >> 9) & 0xf;
664 mos6522_write(ms, addr, val, size);
665 }
666
667 static const MemoryRegionOps mos6522_pmu_ops = {
668 .read = mos6522_pmu_read,
669 .write = mos6522_pmu_write,
670 .endianness = DEVICE_BIG_ENDIAN,
671 .impl = {
672 .min_access_size = 1,
673 .max_access_size = 1,
674 },
675 };
676
677 static bool pmu_adb_state_needed(void *opaque)
678 {
679 PMUState *s = opaque;
680
681 return s->has_adb;
682 }
683
684 static const VMStateDescription vmstate_pmu_adb = {
685 .name = "pmu/adb",
686 .version_id = 0,
687 .minimum_version_id = 0,
688 .needed = pmu_adb_state_needed,
689 .fields = (VMStateField[]) {
690 VMSTATE_UINT16(adb_poll_mask, PMUState),
691 VMSTATE_TIMER_PTR(adb_poll_timer, PMUState),
692 VMSTATE_UINT8(adb_reply_size, PMUState),
693 VMSTATE_BUFFER(adb_reply, PMUState),
694 VMSTATE_END_OF_LIST()
695 }
696 };
697
698 static const VMStateDescription vmstate_pmu = {
699 .name = "pmu",
700 .version_id = 0,
701 .minimum_version_id = 0,
702 .fields = (VMStateField[]) {
703 VMSTATE_STRUCT(mos6522_pmu.parent_obj, PMUState, 0, vmstate_mos6522,
704 MOS6522State),
705 VMSTATE_UINT8(last_b, PMUState),
706 VMSTATE_UINT8(cmd, PMUState),
707 VMSTATE_UINT32(cmdlen, PMUState),
708 VMSTATE_UINT32(rsplen, PMUState),
709 VMSTATE_UINT8(cmd_buf_pos, PMUState),
710 VMSTATE_BUFFER(cmd_buf, PMUState),
711 VMSTATE_UINT8(cmd_rsp_pos, PMUState),
712 VMSTATE_UINT8(cmd_rsp_sz, PMUState),
713 VMSTATE_BUFFER(cmd_rsp, PMUState),
714 VMSTATE_UINT8(intbits, PMUState),
715 VMSTATE_UINT8(intmask, PMUState),
716 VMSTATE_UINT8(autopoll_rate_ms, PMUState),
717 VMSTATE_UINT8(autopoll_mask, PMUState),
718 VMSTATE_UINT32(tick_offset, PMUState),
719 VMSTATE_TIMER_PTR(one_sec_timer, PMUState),
720 VMSTATE_INT64(one_sec_target, PMUState),
721 VMSTATE_END_OF_LIST()
722 },
723 .subsections = (const VMStateDescription * []) {
724 &vmstate_pmu_adb,
725 }
726 };
727
728 static void pmu_reset(DeviceState *dev)
729 {
730 PMUState *s = VIA_PMU(dev);
731
732 /* OpenBIOS needs to do this? MacOS 9 needs it */
733 s->intmask = PMU_INT_ADB | PMU_INT_TICK;
734 s->intbits = 0;
735
736 s->cmd_state = pmu_state_idle;
737 s->autopoll_mask = 0;
738 }
739
740 static void pmu_realize(DeviceState *dev, Error **errp)
741 {
742 PMUState *s = VIA_PMU(dev);
743 Error *err = NULL;
744 SysBusDevice *sbd;
745 struct tm tm;
746
747 object_property_set_bool(OBJECT(&s->mos6522_pmu), true, "realized",
748 &err);
749 if (err) {
750 error_propagate(errp, err);
751 return;
752 }
753
754 /* Pass IRQ from 6522 */
755 sbd = SYS_BUS_DEVICE(s);
756 sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->mos6522_pmu));
757
758 qemu_get_timedate(&tm, 0);
759 s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET;
760 s->one_sec_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, pmu_one_sec_timer, s);
761 s->one_sec_target = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 1000;
762 timer_mod(s->one_sec_timer, s->one_sec_target);
763
764 if (s->has_adb) {
765 qbus_create_inplace(&s->adb_bus, sizeof(s->adb_bus), TYPE_ADB_BUS,
766 dev, "adb.0");
767 s->adb_poll_timer = timer_new_ms(QEMU_CLOCK_VIRTUAL, pmu_adb_poll, s);
768 s->adb_poll_mask = 0xffff;
769 s->autopoll_rate_ms = 20;
770 }
771 }
772
773 static void pmu_init(Object *obj)
774 {
775 SysBusDevice *d = SYS_BUS_DEVICE(obj);
776 PMUState *s = VIA_PMU(obj);
777
778 object_property_add_link(obj, "gpio", TYPE_MACIO_GPIO,
779 (Object **) &s->gpio,
780 qdev_prop_allow_set_link_before_realize,
781 0);
782
783 sysbus_init_child_obj(obj, "mos6522-pmu", &s->mos6522_pmu,
784 sizeof(s->mos6522_pmu), TYPE_MOS6522_PMU);
785
786 memory_region_init_io(&s->mem, obj, &mos6522_pmu_ops, s, "via-pmu",
787 0x2000);
788 sysbus_init_mmio(d, &s->mem);
789 }
790
791 static Property pmu_properties[] = {
792 DEFINE_PROP_BOOL("has-adb", PMUState, has_adb, true),
793 DEFINE_PROP_END_OF_LIST()
794 };
795
796 static void pmu_class_init(ObjectClass *oc, void *data)
797 {
798 DeviceClass *dc = DEVICE_CLASS(oc);
799
800 dc->realize = pmu_realize;
801 dc->reset = pmu_reset;
802 dc->vmsd = &vmstate_pmu;
803 device_class_set_props(dc, pmu_properties);
804 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
805 }
806
807 static const TypeInfo pmu_type_info = {
808 .name = TYPE_VIA_PMU,
809 .parent = TYPE_SYS_BUS_DEVICE,
810 .instance_size = sizeof(PMUState),
811 .instance_init = pmu_init,
812 .class_init = pmu_class_init,
813 };
814
815 static void mos6522_pmu_portB_write(MOS6522State *s)
816 {
817 MOS6522PMUState *mps = container_of(s, MOS6522PMUState, parent_obj);
818 PMUState *ps = container_of(mps, PMUState, mos6522_pmu);
819
820 if ((s->pcr & 0xe0) == 0x20 || (s->pcr & 0xe0) == 0x60) {
821 s->ifr &= ~CB2_INT;
822 }
823 s->ifr &= ~CB1_INT;
824
825 via_update_irq(ps);
826 pmu_update(ps);
827 }
828
829 static void mos6522_pmu_portA_write(MOS6522State *s)
830 {
831 MOS6522PMUState *mps = container_of(s, MOS6522PMUState, parent_obj);
832 PMUState *ps = container_of(mps, PMUState, mos6522_pmu);
833
834 if ((s->pcr & 0x0e) == 0x02 || (s->pcr & 0x0e) == 0x06) {
835 s->ifr &= ~CA2_INT;
836 }
837 s->ifr &= ~CA1_INT;
838
839 via_update_irq(ps);
840 }
841
842 static void mos6522_pmu_reset(DeviceState *dev)
843 {
844 MOS6522State *ms = MOS6522(dev);
845 MOS6522PMUState *mps = container_of(ms, MOS6522PMUState, parent_obj);
846 PMUState *s = container_of(mps, PMUState, mos6522_pmu);
847 MOS6522DeviceClass *mdc = MOS6522_DEVICE_GET_CLASS(ms);
848
849 mdc->parent_reset(dev);
850
851 ms->timers[0].frequency = VIA_TIMER_FREQ;
852 ms->timers[1].frequency = (SCALE_US * 6000) / 4700;
853
854 s->last_b = ms->b = TACK | TREQ;
855 }
856
857 static void mos6522_pmu_class_init(ObjectClass *oc, void *data)
858 {
859 DeviceClass *dc = DEVICE_CLASS(oc);
860 MOS6522DeviceClass *mdc = MOS6522_DEVICE_CLASS(oc);
861
862 dc->reset = mos6522_pmu_reset;
863 mdc->portB_write = mos6522_pmu_portB_write;
864 mdc->portA_write = mos6522_pmu_portA_write;
865 }
866
867 static const TypeInfo mos6522_pmu_type_info = {
868 .name = TYPE_MOS6522_PMU,
869 .parent = TYPE_MOS6522,
870 .instance_size = sizeof(MOS6522PMUState),
871 .class_init = mos6522_pmu_class_init,
872 };
873
874 static void pmu_register_types(void)
875 {
876 type_register_static(&pmu_type_info);
877 type_register_static(&mos6522_pmu_type_info);
878 }
879
880 type_init(pmu_register_types)