hw/misc/mps2-scc: Use the LED device
[qemu.git] / hw / misc / mps2-scc.c
1 /*
2 * ARM MPS2 SCC emulation
3 *
4 * Copyright (c) 2017 Linaro Limited
5 * Written by Peter Maydell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 or
9 * (at your option) any later version.
10 */
11
12 /* This is a model of the SCC (Serial Communication Controller)
13 * found in the FPGA images of MPS2 development boards.
14 *
15 * Documentation of it can be found in the MPS2 TRM:
16 * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.100112_0100_03_en/index.html
17 * and also in the Application Notes documenting individual FPGA images.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/log.h"
22 #include "qemu/module.h"
23 #include "qemu/bitops.h"
24 #include "trace.h"
25 #include "hw/sysbus.h"
26 #include "migration/vmstate.h"
27 #include "hw/registerfields.h"
28 #include "hw/misc/mps2-scc.h"
29 #include "hw/misc/led.h"
30 #include "hw/qdev-properties.h"
31
32 REG32(CFG0, 0)
33 REG32(CFG1, 4)
34 REG32(CFG3, 0xc)
35 REG32(CFG4, 0x10)
36 REG32(CFGDATA_RTN, 0xa0)
37 REG32(CFGDATA_OUT, 0xa4)
38 REG32(CFGCTRL, 0xa8)
39 FIELD(CFGCTRL, DEVICE, 0, 12)
40 FIELD(CFGCTRL, RES1, 12, 8)
41 FIELD(CFGCTRL, FUNCTION, 20, 6)
42 FIELD(CFGCTRL, RES2, 26, 4)
43 FIELD(CFGCTRL, WRITE, 30, 1)
44 FIELD(CFGCTRL, START, 31, 1)
45 REG32(CFGSTAT, 0xac)
46 FIELD(CFGSTAT, DONE, 0, 1)
47 FIELD(CFGSTAT, ERROR, 1, 1)
48 REG32(DLL, 0x100)
49 REG32(AID, 0xFF8)
50 REG32(ID, 0xFFC)
51
52 /* Handle a write via the SYS_CFG channel to the specified function/device.
53 * Return false on error (reported to guest via SYS_CFGCTRL ERROR bit).
54 */
55 static bool scc_cfg_write(MPS2SCC *s, unsigned function,
56 unsigned device, uint32_t value)
57 {
58 trace_mps2_scc_cfg_write(function, device, value);
59
60 if (function != 1 || device >= NUM_OSCCLK) {
61 qemu_log_mask(LOG_GUEST_ERROR,
62 "MPS2 SCC config write: bad function %d device %d\n",
63 function, device);
64 return false;
65 }
66
67 s->oscclk[device] = value;
68 return true;
69 }
70
71 /* Handle a read via the SYS_CFG channel to the specified function/device.
72 * Return false on error (reported to guest via SYS_CFGCTRL ERROR bit),
73 * or set *value on success.
74 */
75 static bool scc_cfg_read(MPS2SCC *s, unsigned function,
76 unsigned device, uint32_t *value)
77 {
78 if (function != 1 || device >= NUM_OSCCLK) {
79 qemu_log_mask(LOG_GUEST_ERROR,
80 "MPS2 SCC config read: bad function %d device %d\n",
81 function, device);
82 return false;
83 }
84
85 *value = s->oscclk[device];
86
87 trace_mps2_scc_cfg_read(function, device, *value);
88 return true;
89 }
90
91 static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size)
92 {
93 MPS2SCC *s = MPS2_SCC(opaque);
94 uint64_t r;
95
96 switch (offset) {
97 case A_CFG0:
98 r = s->cfg0;
99 break;
100 case A_CFG1:
101 r = s->cfg1;
102 break;
103 case A_CFG3:
104 /* These are user-settable DIP switches on the board. We don't
105 * model that, so just return zeroes.
106 */
107 r = 0;
108 break;
109 case A_CFG4:
110 r = s->cfg4;
111 break;
112 case A_CFGDATA_RTN:
113 r = s->cfgdata_rtn;
114 break;
115 case A_CFGDATA_OUT:
116 r = s->cfgdata_out;
117 break;
118 case A_CFGCTRL:
119 r = s->cfgctrl;
120 break;
121 case A_CFGSTAT:
122 r = s->cfgstat;
123 break;
124 case A_DLL:
125 r = s->dll;
126 break;
127 case A_AID:
128 r = s->aid;
129 break;
130 case A_ID:
131 r = s->id;
132 break;
133 default:
134 qemu_log_mask(LOG_GUEST_ERROR,
135 "MPS2 SCC read: bad offset %x\n", (int) offset);
136 r = 0;
137 break;
138 }
139
140 trace_mps2_scc_read(offset, r, size);
141 return r;
142 }
143
144 static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value,
145 unsigned size)
146 {
147 MPS2SCC *s = MPS2_SCC(opaque);
148
149 trace_mps2_scc_write(offset, value, size);
150
151 switch (offset) {
152 case A_CFG0:
153 /* TODO on some boards bit 0 controls RAM remapping */
154 s->cfg0 = value;
155 break;
156 case A_CFG1:
157 s->cfg1 = value;
158 for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) {
159 led_set_state(s->led[i], extract32(value, i, 1));
160 }
161 break;
162 case A_CFGDATA_OUT:
163 s->cfgdata_out = value;
164 break;
165 case A_CFGCTRL:
166 /* Writing to CFGCTRL clears SYS_CFGSTAT */
167 s->cfgstat = 0;
168 s->cfgctrl = value & ~(R_CFGCTRL_RES1_MASK |
169 R_CFGCTRL_RES2_MASK |
170 R_CFGCTRL_START_MASK);
171
172 if (value & R_CFGCTRL_START_MASK) {
173 /* Start bit set -- do a read or write (instantaneously) */
174 int device = extract32(s->cfgctrl, R_CFGCTRL_DEVICE_SHIFT,
175 R_CFGCTRL_DEVICE_LENGTH);
176 int function = extract32(s->cfgctrl, R_CFGCTRL_FUNCTION_SHIFT,
177 R_CFGCTRL_FUNCTION_LENGTH);
178
179 s->cfgstat = R_CFGSTAT_DONE_MASK;
180 if (s->cfgctrl & R_CFGCTRL_WRITE_MASK) {
181 if (!scc_cfg_write(s, function, device, s->cfgdata_out)) {
182 s->cfgstat |= R_CFGSTAT_ERROR_MASK;
183 }
184 } else {
185 uint32_t result;
186 if (!scc_cfg_read(s, function, device, &result)) {
187 s->cfgstat |= R_CFGSTAT_ERROR_MASK;
188 } else {
189 s->cfgdata_rtn = result;
190 }
191 }
192 }
193 break;
194 case A_DLL:
195 /* DLL stands for Digital Locked Loop.
196 * Bits [31:24] (DLL_LOCK_MASK) are writable, and indicate a
197 * mask of which of the DLL_LOCKED bits [16:23] should be ORed
198 * together to determine the ALL_UNMASKED_DLLS_LOCKED bit [0].
199 * For QEMU, our DLLs are always locked, so we can leave bit 0
200 * as 1 always and don't need to recalculate it.
201 */
202 s->dll = deposit32(s->dll, 24, 8, extract32(value, 24, 8));
203 break;
204 default:
205 qemu_log_mask(LOG_GUEST_ERROR,
206 "MPS2 SCC write: bad offset 0x%x\n", (int) offset);
207 break;
208 }
209 }
210
211 static const MemoryRegionOps mps2_scc_ops = {
212 .read = mps2_scc_read,
213 .write = mps2_scc_write,
214 .endianness = DEVICE_LITTLE_ENDIAN,
215 };
216
217 static void mps2_scc_reset(DeviceState *dev)
218 {
219 MPS2SCC *s = MPS2_SCC(dev);
220 int i;
221
222 trace_mps2_scc_reset();
223 s->cfg0 = 0;
224 s->cfg1 = 0;
225 s->cfgdata_rtn = 0;
226 s->cfgdata_out = 0;
227 s->cfgctrl = 0x100000;
228 s->cfgstat = 0;
229 s->dll = 0xffff0001;
230 for (i = 0; i < NUM_OSCCLK; i++) {
231 s->oscclk[i] = s->oscclk_reset[i];
232 }
233 for (i = 0; i < ARRAY_SIZE(s->led); i++) {
234 device_cold_reset(DEVICE(s->led[i]));
235 }
236 }
237
238 static void mps2_scc_init(Object *obj)
239 {
240 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
241 MPS2SCC *s = MPS2_SCC(obj);
242
243 memory_region_init_io(&s->iomem, obj, &mps2_scc_ops, s, "mps2-scc", 0x1000);
244 sysbus_init_mmio(sbd, &s->iomem);
245 }
246
247 static void mps2_scc_realize(DeviceState *dev, Error **errp)
248 {
249 MPS2SCC *s = MPS2_SCC(dev);
250
251 for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) {
252 char *name = g_strdup_printf("SCC LED%zu", i);
253 s->led[i] = led_create_simple(OBJECT(dev), GPIO_POLARITY_ACTIVE_HIGH,
254 LED_COLOR_GREEN, name);
255 g_free(name);
256 }
257 }
258
259 static const VMStateDescription mps2_scc_vmstate = {
260 .name = "mps2-scc",
261 .version_id = 1,
262 .minimum_version_id = 1,
263 .fields = (VMStateField[]) {
264 VMSTATE_UINT32(cfg0, MPS2SCC),
265 VMSTATE_UINT32(cfg1, MPS2SCC),
266 VMSTATE_UINT32(cfgdata_rtn, MPS2SCC),
267 VMSTATE_UINT32(cfgdata_out, MPS2SCC),
268 VMSTATE_UINT32(cfgctrl, MPS2SCC),
269 VMSTATE_UINT32(cfgstat, MPS2SCC),
270 VMSTATE_UINT32(dll, MPS2SCC),
271 VMSTATE_UINT32_ARRAY(oscclk, MPS2SCC, NUM_OSCCLK),
272 VMSTATE_END_OF_LIST()
273 }
274 };
275
276 static Property mps2_scc_properties[] = {
277 /* Values for various read-only ID registers (which are specific
278 * to the board model or FPGA image)
279 */
280 DEFINE_PROP_UINT32("scc-cfg4", MPS2SCC, cfg4, 0),
281 DEFINE_PROP_UINT32("scc-aid", MPS2SCC, aid, 0),
282 DEFINE_PROP_UINT32("scc-id", MPS2SCC, id, 0),
283 /* These are the initial settings for the source clocks on the board.
284 * In hardware they can be configured via a config file read by the
285 * motherboard configuration controller to suit the FPGA image.
286 * These default values are used by most of the standard FPGA images.
287 */
288 DEFINE_PROP_UINT32("oscclk0", MPS2SCC, oscclk_reset[0], 50000000),
289 DEFINE_PROP_UINT32("oscclk1", MPS2SCC, oscclk_reset[1], 24576000),
290 DEFINE_PROP_UINT32("oscclk2", MPS2SCC, oscclk_reset[2], 25000000),
291 DEFINE_PROP_END_OF_LIST(),
292 };
293
294 static void mps2_scc_class_init(ObjectClass *klass, void *data)
295 {
296 DeviceClass *dc = DEVICE_CLASS(klass);
297
298 dc->realize = mps2_scc_realize;
299 dc->vmsd = &mps2_scc_vmstate;
300 dc->reset = mps2_scc_reset;
301 device_class_set_props(dc, mps2_scc_properties);
302 }
303
304 static const TypeInfo mps2_scc_info = {
305 .name = TYPE_MPS2_SCC,
306 .parent = TYPE_SYS_BUS_DEVICE,
307 .instance_size = sizeof(MPS2SCC),
308 .instance_init = mps2_scc_init,
309 .class_init = mps2_scc_class_init,
310 };
311
312 static void mps2_scc_register_types(void)
313 {
314 type_register_static(&mps2_scc_info);
315 }
316
317 type_init(mps2_scc_register_types);