trace: switch position of headers to what Meson requires
[qemu.git] / hw / misc / puv3_pm.c
1 /*
2 * Power Management device simulation in PKUnity SoC
3 *
4 * Copyright (C) 2010-2012 Guan Xuetao
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation, or any later version.
9 * See the COPYING file in the top-level directory.
10 */
11
12 #include "qemu/osdep.h"
13 #include "hw/sysbus.h"
14
15 #undef DEBUG_PUV3
16 #include "hw/unicore32/puv3.h"
17 #include "qemu/module.h"
18 #include "qemu/log.h"
19
20 #define TYPE_PUV3_PM "puv3_pm"
21 #define PUV3_PM(obj) OBJECT_CHECK(PUV3PMState, (obj), TYPE_PUV3_PM)
22
23 typedef struct PUV3PMState {
24 SysBusDevice parent_obj;
25
26 MemoryRegion iomem;
27
28 uint32_t reg_PMCR;
29 uint32_t reg_PCGR;
30 uint32_t reg_PLL_SYS_CFG;
31 uint32_t reg_PLL_DDR_CFG;
32 uint32_t reg_PLL_VGA_CFG;
33 uint32_t reg_DIVCFG;
34 } PUV3PMState;
35
36 static uint64_t puv3_pm_read(void *opaque, hwaddr offset,
37 unsigned size)
38 {
39 PUV3PMState *s = opaque;
40 uint32_t ret = 0;
41
42 switch (offset) {
43 case 0x14:
44 ret = s->reg_PCGR;
45 break;
46 case 0x18:
47 ret = s->reg_PLL_SYS_CFG;
48 break;
49 case 0x1c:
50 ret = s->reg_PLL_DDR_CFG;
51 break;
52 case 0x20:
53 ret = s->reg_PLL_VGA_CFG;
54 break;
55 case 0x24:
56 ret = s->reg_DIVCFG;
57 break;
58 case 0x28: /* PLL SYS STATUS */
59 ret = 0x00002401;
60 break;
61 case 0x2c: /* PLL DDR STATUS */
62 ret = 0x00100c00;
63 break;
64 case 0x30: /* PLL VGA STATUS */
65 ret = 0x00003801;
66 break;
67 case 0x34: /* DIV STATUS */
68 ret = 0x22f52015;
69 break;
70 case 0x38: /* SW RESET */
71 ret = 0x0;
72 break;
73 case 0x44: /* PLL DFC DONE */
74 ret = 0x7;
75 break;
76 default:
77 qemu_log_mask(LOG_GUEST_ERROR,
78 "%s: Bad read offset 0x%"HWADDR_PRIx"\n",
79 __func__, offset);
80 }
81 DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
82
83 return ret;
84 }
85
86 static void puv3_pm_write(void *opaque, hwaddr offset,
87 uint64_t value, unsigned size)
88 {
89 PUV3PMState *s = opaque;
90
91 switch (offset) {
92 case 0x0:
93 s->reg_PMCR = value;
94 break;
95 case 0x14:
96 s->reg_PCGR = value;
97 break;
98 case 0x18:
99 s->reg_PLL_SYS_CFG = value;
100 break;
101 case 0x1c:
102 s->reg_PLL_DDR_CFG = value;
103 break;
104 case 0x20:
105 s->reg_PLL_VGA_CFG = value;
106 break;
107 case 0x24:
108 case 0x38:
109 break;
110 default:
111 qemu_log_mask(LOG_GUEST_ERROR,
112 "%s: Bad write offset 0x%"HWADDR_PRIx"\n",
113 __func__, offset);
114 }
115 DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
116 }
117
118 static const MemoryRegionOps puv3_pm_ops = {
119 .read = puv3_pm_read,
120 .write = puv3_pm_write,
121 .impl = {
122 .min_access_size = 4,
123 .max_access_size = 4,
124 },
125 .endianness = DEVICE_NATIVE_ENDIAN,
126 };
127
128 static void puv3_pm_realize(DeviceState *dev, Error **errp)
129 {
130 PUV3PMState *s = PUV3_PM(dev);
131
132 s->reg_PCGR = 0x0;
133
134 memory_region_init_io(&s->iomem, OBJECT(s), &puv3_pm_ops, s, "puv3_pm",
135 PUV3_REGS_OFFSET);
136 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
137 }
138
139 static void puv3_pm_class_init(ObjectClass *klass, void *data)
140 {
141 DeviceClass *dc = DEVICE_CLASS(klass);
142
143 dc->realize = puv3_pm_realize;
144 }
145
146 static const TypeInfo puv3_pm_info = {
147 .name = TYPE_PUV3_PM,
148 .parent = TYPE_SYS_BUS_DEVICE,
149 .instance_size = sizeof(PUV3PMState),
150 .class_init = puv3_pm_class_init,
151 };
152
153 static void puv3_pm_register_type(void)
154 {
155 type_register_static(&puv3_pm_info);
156 }
157
158 type_init(puv3_pm_register_type)