sm501: Add missing arbitration control register
[qemu.git] / hw / net / cadence_gem.c
1 /*
2 * QEMU Cadence GEM emulation
3 *
4 * Copyright (c) 2011 Xilinx, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include <zlib.h> /* For crc32 */
27
28 #include "hw/net/cadence_gem.h"
29 #include "qapi/error.h"
30 #include "qemu/log.h"
31 #include "net/checksum.h"
32
33 #ifdef CADENCE_GEM_ERR_DEBUG
34 #define DB_PRINT(...) do { \
35 fprintf(stderr, ": %s: ", __func__); \
36 fprintf(stderr, ## __VA_ARGS__); \
37 } while (0);
38 #else
39 #define DB_PRINT(...)
40 #endif
41
42 #define GEM_NWCTRL (0x00000000/4) /* Network Control reg */
43 #define GEM_NWCFG (0x00000004/4) /* Network Config reg */
44 #define GEM_NWSTATUS (0x00000008/4) /* Network Status reg */
45 #define GEM_USERIO (0x0000000C/4) /* User IO reg */
46 #define GEM_DMACFG (0x00000010/4) /* DMA Control reg */
47 #define GEM_TXSTATUS (0x00000014/4) /* TX Status reg */
48 #define GEM_RXQBASE (0x00000018/4) /* RX Q Base address reg */
49 #define GEM_TXQBASE (0x0000001C/4) /* TX Q Base address reg */
50 #define GEM_RXSTATUS (0x00000020/4) /* RX Status reg */
51 #define GEM_ISR (0x00000024/4) /* Interrupt Status reg */
52 #define GEM_IER (0x00000028/4) /* Interrupt Enable reg */
53 #define GEM_IDR (0x0000002C/4) /* Interrupt Disable reg */
54 #define GEM_IMR (0x00000030/4) /* Interrupt Mask reg */
55 #define GEM_PHYMNTNC (0x00000034/4) /* Phy Maintenance reg */
56 #define GEM_RXPAUSE (0x00000038/4) /* RX Pause Time reg */
57 #define GEM_TXPAUSE (0x0000003C/4) /* TX Pause Time reg */
58 #define GEM_TXPARTIALSF (0x00000040/4) /* TX Partial Store and Forward */
59 #define GEM_RXPARTIALSF (0x00000044/4) /* RX Partial Store and Forward */
60 #define GEM_HASHLO (0x00000080/4) /* Hash Low address reg */
61 #define GEM_HASHHI (0x00000084/4) /* Hash High address reg */
62 #define GEM_SPADDR1LO (0x00000088/4) /* Specific addr 1 low reg */
63 #define GEM_SPADDR1HI (0x0000008C/4) /* Specific addr 1 high reg */
64 #define GEM_SPADDR2LO (0x00000090/4) /* Specific addr 2 low reg */
65 #define GEM_SPADDR2HI (0x00000094/4) /* Specific addr 2 high reg */
66 #define GEM_SPADDR3LO (0x00000098/4) /* Specific addr 3 low reg */
67 #define GEM_SPADDR3HI (0x0000009C/4) /* Specific addr 3 high reg */
68 #define GEM_SPADDR4LO (0x000000A0/4) /* Specific addr 4 low reg */
69 #define GEM_SPADDR4HI (0x000000A4/4) /* Specific addr 4 high reg */
70 #define GEM_TIDMATCH1 (0x000000A8/4) /* Type ID1 Match reg */
71 #define GEM_TIDMATCH2 (0x000000AC/4) /* Type ID2 Match reg */
72 #define GEM_TIDMATCH3 (0x000000B0/4) /* Type ID3 Match reg */
73 #define GEM_TIDMATCH4 (0x000000B4/4) /* Type ID4 Match reg */
74 #define GEM_WOLAN (0x000000B8/4) /* Wake on LAN reg */
75 #define GEM_IPGSTRETCH (0x000000BC/4) /* IPG Stretch reg */
76 #define GEM_SVLAN (0x000000C0/4) /* Stacked VLAN reg */
77 #define GEM_MODID (0x000000FC/4) /* Module ID reg */
78 #define GEM_OCTTXLO (0x00000100/4) /* Octects transmitted Low reg */
79 #define GEM_OCTTXHI (0x00000104/4) /* Octects transmitted High reg */
80 #define GEM_TXCNT (0x00000108/4) /* Error-free Frames transmitted */
81 #define GEM_TXBCNT (0x0000010C/4) /* Error-free Broadcast Frames */
82 #define GEM_TXMCNT (0x00000110/4) /* Error-free Multicast Frame */
83 #define GEM_TXPAUSECNT (0x00000114/4) /* Pause Frames Transmitted */
84 #define GEM_TX64CNT (0x00000118/4) /* Error-free 64 TX */
85 #define GEM_TX65CNT (0x0000011C/4) /* Error-free 65-127 TX */
86 #define GEM_TX128CNT (0x00000120/4) /* Error-free 128-255 TX */
87 #define GEM_TX256CNT (0x00000124/4) /* Error-free 256-511 */
88 #define GEM_TX512CNT (0x00000128/4) /* Error-free 512-1023 TX */
89 #define GEM_TX1024CNT (0x0000012C/4) /* Error-free 1024-1518 TX */
90 #define GEM_TX1519CNT (0x00000130/4) /* Error-free larger than 1519 TX */
91 #define GEM_TXURUNCNT (0x00000134/4) /* TX under run error counter */
92 #define GEM_SINGLECOLLCNT (0x00000138/4) /* Single Collision Frames */
93 #define GEM_MULTCOLLCNT (0x0000013C/4) /* Multiple Collision Frames */
94 #define GEM_EXCESSCOLLCNT (0x00000140/4) /* Excessive Collision Frames */
95 #define GEM_LATECOLLCNT (0x00000144/4) /* Late Collision Frames */
96 #define GEM_DEFERTXCNT (0x00000148/4) /* Deferred Transmission Frames */
97 #define GEM_CSENSECNT (0x0000014C/4) /* Carrier Sense Error Counter */
98 #define GEM_OCTRXLO (0x00000150/4) /* Octects Received register Low */
99 #define GEM_OCTRXHI (0x00000154/4) /* Octects Received register High */
100 #define GEM_RXCNT (0x00000158/4) /* Error-free Frames Received */
101 #define GEM_RXBROADCNT (0x0000015C/4) /* Error-free Broadcast Frames RX */
102 #define GEM_RXMULTICNT (0x00000160/4) /* Error-free Multicast Frames RX */
103 #define GEM_RXPAUSECNT (0x00000164/4) /* Pause Frames Received Counter */
104 #define GEM_RX64CNT (0x00000168/4) /* Error-free 64 byte Frames RX */
105 #define GEM_RX65CNT (0x0000016C/4) /* Error-free 65-127B Frames RX */
106 #define GEM_RX128CNT (0x00000170/4) /* Error-free 128-255B Frames RX */
107 #define GEM_RX256CNT (0x00000174/4) /* Error-free 256-512B Frames RX */
108 #define GEM_RX512CNT (0x00000178/4) /* Error-free 512-1023B Frames RX */
109 #define GEM_RX1024CNT (0x0000017C/4) /* Error-free 1024-1518B Frames RX */
110 #define GEM_RX1519CNT (0x00000180/4) /* Error-free 1519-max Frames RX */
111 #define GEM_RXUNDERCNT (0x00000184/4) /* Undersize Frames Received */
112 #define GEM_RXOVERCNT (0x00000188/4) /* Oversize Frames Received */
113 #define GEM_RXJABCNT (0x0000018C/4) /* Jabbers Received Counter */
114 #define GEM_RXFCSCNT (0x00000190/4) /* Frame Check seq. Error Counter */
115 #define GEM_RXLENERRCNT (0x00000194/4) /* Length Field Error Counter */
116 #define GEM_RXSYMERRCNT (0x00000198/4) /* Symbol Error Counter */
117 #define GEM_RXALIGNERRCNT (0x0000019C/4) /* Alignment Error Counter */
118 #define GEM_RXRSCERRCNT (0x000001A0/4) /* Receive Resource Error Counter */
119 #define GEM_RXORUNCNT (0x000001A4/4) /* Receive Overrun Counter */
120 #define GEM_RXIPCSERRCNT (0x000001A8/4) /* IP header Checksum Error Counter */
121 #define GEM_RXTCPCCNT (0x000001AC/4) /* TCP Checksum Error Counter */
122 #define GEM_RXUDPCCNT (0x000001B0/4) /* UDP Checksum Error Counter */
123
124 #define GEM_1588S (0x000001D0/4) /* 1588 Timer Seconds */
125 #define GEM_1588NS (0x000001D4/4) /* 1588 Timer Nanoseconds */
126 #define GEM_1588ADJ (0x000001D8/4) /* 1588 Timer Adjust */
127 #define GEM_1588INC (0x000001DC/4) /* 1588 Timer Increment */
128 #define GEM_PTPETXS (0x000001E0/4) /* PTP Event Frame Transmitted (s) */
129 #define GEM_PTPETXNS (0x000001E4/4) /* PTP Event Frame Transmitted (ns) */
130 #define GEM_PTPERXS (0x000001E8/4) /* PTP Event Frame Received (s) */
131 #define GEM_PTPERXNS (0x000001EC/4) /* PTP Event Frame Received (ns) */
132 #define GEM_PTPPTXS (0x000001E0/4) /* PTP Peer Frame Transmitted (s) */
133 #define GEM_PTPPTXNS (0x000001E4/4) /* PTP Peer Frame Transmitted (ns) */
134 #define GEM_PTPPRXS (0x000001E8/4) /* PTP Peer Frame Received (s) */
135 #define GEM_PTPPRXNS (0x000001EC/4) /* PTP Peer Frame Received (ns) */
136
137 /* Design Configuration Registers */
138 #define GEM_DESCONF (0x00000280/4)
139 #define GEM_DESCONF2 (0x00000284/4)
140 #define GEM_DESCONF3 (0x00000288/4)
141 #define GEM_DESCONF4 (0x0000028C/4)
142 #define GEM_DESCONF5 (0x00000290/4)
143 #define GEM_DESCONF6 (0x00000294/4)
144 #define GEM_DESCONF7 (0x00000298/4)
145
146 #define GEM_INT_Q1_STATUS (0x00000400 / 4)
147 #define GEM_INT_Q1_MASK (0x00000640 / 4)
148
149 #define GEM_TRANSMIT_Q1_PTR (0x00000440 / 4)
150 #define GEM_TRANSMIT_Q7_PTR (GEM_TRANSMIT_Q1_PTR + 6)
151
152 #define GEM_RECEIVE_Q1_PTR (0x00000480 / 4)
153 #define GEM_RECEIVE_Q7_PTR (GEM_RECEIVE_Q1_PTR + 6)
154
155 #define GEM_INT_Q1_ENABLE (0x00000600 / 4)
156 #define GEM_INT_Q7_ENABLE (GEM_INT_Q1_ENABLE + 6)
157
158 #define GEM_INT_Q1_DISABLE (0x00000620 / 4)
159 #define GEM_INT_Q7_DISABLE (GEM_INT_Q1_DISABLE + 6)
160
161 #define GEM_INT_Q1_MASK (0x00000640 / 4)
162 #define GEM_INT_Q7_MASK (GEM_INT_Q1_MASK + 6)
163
164 #define GEM_SCREENING_TYPE1_REGISTER_0 (0x00000500 / 4)
165
166 #define GEM_ST1R_UDP_PORT_MATCH_ENABLE (1 << 29)
167 #define GEM_ST1R_DSTC_ENABLE (1 << 28)
168 #define GEM_ST1R_UDP_PORT_MATCH_SHIFT (12)
169 #define GEM_ST1R_UDP_PORT_MATCH_WIDTH (27 - GEM_ST1R_UDP_PORT_MATCH_SHIFT + 1)
170 #define GEM_ST1R_DSTC_MATCH_SHIFT (4)
171 #define GEM_ST1R_DSTC_MATCH_WIDTH (11 - GEM_ST1R_DSTC_MATCH_SHIFT + 1)
172 #define GEM_ST1R_QUEUE_SHIFT (0)
173 #define GEM_ST1R_QUEUE_WIDTH (3 - GEM_ST1R_QUEUE_SHIFT + 1)
174
175 #define GEM_SCREENING_TYPE2_REGISTER_0 (0x00000540 / 4)
176
177 #define GEM_ST2R_COMPARE_A_ENABLE (1 << 18)
178 #define GEM_ST2R_COMPARE_A_SHIFT (13)
179 #define GEM_ST2R_COMPARE_WIDTH (17 - GEM_ST2R_COMPARE_A_SHIFT + 1)
180 #define GEM_ST2R_ETHERTYPE_ENABLE (1 << 12)
181 #define GEM_ST2R_ETHERTYPE_INDEX_SHIFT (9)
182 #define GEM_ST2R_ETHERTYPE_INDEX_WIDTH (11 - GEM_ST2R_ETHERTYPE_INDEX_SHIFT \
183 + 1)
184 #define GEM_ST2R_QUEUE_SHIFT (0)
185 #define GEM_ST2R_QUEUE_WIDTH (3 - GEM_ST2R_QUEUE_SHIFT + 1)
186
187 #define GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 (0x000006e0 / 4)
188 #define GEM_TYPE2_COMPARE_0_WORD_0 (0x00000700 / 4)
189
190 #define GEM_T2CW1_COMPARE_OFFSET_SHIFT (7)
191 #define GEM_T2CW1_COMPARE_OFFSET_WIDTH (8 - GEM_T2CW1_COMPARE_OFFSET_SHIFT + 1)
192 #define GEM_T2CW1_OFFSET_VALUE_SHIFT (0)
193 #define GEM_T2CW1_OFFSET_VALUE_WIDTH (6 - GEM_T2CW1_OFFSET_VALUE_SHIFT + 1)
194
195 /*****************************************/
196 #define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */
197 #define GEM_NWCTRL_TXENA 0x00000008 /* Transmit Enable */
198 #define GEM_NWCTRL_RXENA 0x00000004 /* Receive Enable */
199 #define GEM_NWCTRL_LOCALLOOP 0x00000002 /* Local Loopback */
200
201 #define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */
202 #define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with len err */
203 #define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */
204 #define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */
205 #define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash match */
206 #define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if hash match */
207 #define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */
208 #define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */
209
210 #define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */
211 #define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */
212 #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */
213 #define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */
214
215 #define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */
216 #define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */
217
218 #define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */
219 #define GEM_RXSTATUS_NOBUF 0x00000001 /* Buffer unavailable */
220
221 /* GEM_ISR GEM_IER GEM_IDR GEM_IMR */
222 #define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */
223 #define GEM_INT_TXUSED 0x00000008
224 #define GEM_INT_RXUSED 0x00000004
225 #define GEM_INT_RXCMPL 0x00000002
226
227 #define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */
228 #define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */
229 #define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */
230 #define GEM_PHYMNTNC_ADDR_SHFT 23
231 #define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */
232 #define GEM_PHYMNTNC_REG_SHIFT 18
233
234 /* Marvell PHY definitions */
235 #define BOARD_PHY_ADDRESS 23 /* PHY address we will emulate a device at */
236
237 #define PHY_REG_CONTROL 0
238 #define PHY_REG_STATUS 1
239 #define PHY_REG_PHYID1 2
240 #define PHY_REG_PHYID2 3
241 #define PHY_REG_ANEGADV 4
242 #define PHY_REG_LINKPABIL 5
243 #define PHY_REG_ANEGEXP 6
244 #define PHY_REG_NEXTP 7
245 #define PHY_REG_LINKPNEXTP 8
246 #define PHY_REG_100BTCTRL 9
247 #define PHY_REG_1000BTSTAT 10
248 #define PHY_REG_EXTSTAT 15
249 #define PHY_REG_PHYSPCFC_CTL 16
250 #define PHY_REG_PHYSPCFC_ST 17
251 #define PHY_REG_INT_EN 18
252 #define PHY_REG_INT_ST 19
253 #define PHY_REG_EXT_PHYSPCFC_CTL 20
254 #define PHY_REG_RXERR 21
255 #define PHY_REG_EACD 22
256 #define PHY_REG_LED 24
257 #define PHY_REG_LED_OVRD 25
258 #define PHY_REG_EXT_PHYSPCFC_CTL2 26
259 #define PHY_REG_EXT_PHYSPCFC_ST 27
260 #define PHY_REG_CABLE_DIAG 28
261
262 #define PHY_REG_CONTROL_RST 0x8000
263 #define PHY_REG_CONTROL_LOOP 0x4000
264 #define PHY_REG_CONTROL_ANEG 0x1000
265
266 #define PHY_REG_STATUS_LINK 0x0004
267 #define PHY_REG_STATUS_ANEGCMPL 0x0020
268
269 #define PHY_REG_INT_ST_ANEGCMPL 0x0800
270 #define PHY_REG_INT_ST_LINKC 0x0400
271 #define PHY_REG_INT_ST_ENERGY 0x0010
272
273 /***********************************************************************/
274 #define GEM_RX_REJECT (-1)
275 #define GEM_RX_PROMISCUOUS_ACCEPT (-2)
276 #define GEM_RX_BROADCAST_ACCEPT (-3)
277 #define GEM_RX_MULTICAST_HASH_ACCEPT (-4)
278 #define GEM_RX_UNICAST_HASH_ACCEPT (-5)
279
280 #define GEM_RX_SAR_ACCEPT 0
281
282 /***********************************************************************/
283
284 #define DESC_1_USED 0x80000000
285 #define DESC_1_LENGTH 0x00001FFF
286
287 #define DESC_1_TX_WRAP 0x40000000
288 #define DESC_1_TX_LAST 0x00008000
289
290 #define DESC_0_RX_WRAP 0x00000002
291 #define DESC_0_RX_OWNERSHIP 0x00000001
292
293 #define R_DESC_1_RX_SAR_SHIFT 25
294 #define R_DESC_1_RX_SAR_LENGTH 2
295 #define R_DESC_1_RX_SAR_MATCH (1 << 27)
296 #define R_DESC_1_RX_UNICAST_HASH (1 << 29)
297 #define R_DESC_1_RX_MULTICAST_HASH (1 << 30)
298 #define R_DESC_1_RX_BROADCAST (1 << 31)
299
300 #define DESC_1_RX_SOF 0x00004000
301 #define DESC_1_RX_EOF 0x00008000
302
303 #define GEM_MODID_VALUE 0x00020118
304
305 static inline unsigned tx_desc_get_buffer(unsigned *desc)
306 {
307 return desc[0];
308 }
309
310 static inline unsigned tx_desc_get_used(unsigned *desc)
311 {
312 return (desc[1] & DESC_1_USED) ? 1 : 0;
313 }
314
315 static inline void tx_desc_set_used(unsigned *desc)
316 {
317 desc[1] |= DESC_1_USED;
318 }
319
320 static inline unsigned tx_desc_get_wrap(unsigned *desc)
321 {
322 return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0;
323 }
324
325 static inline unsigned tx_desc_get_last(unsigned *desc)
326 {
327 return (desc[1] & DESC_1_TX_LAST) ? 1 : 0;
328 }
329
330 static inline void tx_desc_set_last(unsigned *desc)
331 {
332 desc[1] |= DESC_1_TX_LAST;
333 }
334
335 static inline unsigned tx_desc_get_length(unsigned *desc)
336 {
337 return desc[1] & DESC_1_LENGTH;
338 }
339
340 static inline void print_gem_tx_desc(unsigned *desc, uint8_t queue)
341 {
342 DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue);
343 DB_PRINT("bufaddr: 0x%08x\n", *desc);
344 DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc));
345 DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc));
346 DB_PRINT("last: %d\n", tx_desc_get_last(desc));
347 DB_PRINT("length: %d\n", tx_desc_get_length(desc));
348 }
349
350 static inline unsigned rx_desc_get_buffer(unsigned *desc)
351 {
352 return desc[0] & ~0x3UL;
353 }
354
355 static inline unsigned rx_desc_get_wrap(unsigned *desc)
356 {
357 return desc[0] & DESC_0_RX_WRAP ? 1 : 0;
358 }
359
360 static inline unsigned rx_desc_get_ownership(unsigned *desc)
361 {
362 return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0;
363 }
364
365 static inline void rx_desc_set_ownership(unsigned *desc)
366 {
367 desc[0] |= DESC_0_RX_OWNERSHIP;
368 }
369
370 static inline void rx_desc_set_sof(unsigned *desc)
371 {
372 desc[1] |= DESC_1_RX_SOF;
373 }
374
375 static inline void rx_desc_set_eof(unsigned *desc)
376 {
377 desc[1] |= DESC_1_RX_EOF;
378 }
379
380 static inline void rx_desc_set_length(unsigned *desc, unsigned len)
381 {
382 desc[1] &= ~DESC_1_LENGTH;
383 desc[1] |= len;
384 }
385
386 static inline void rx_desc_set_broadcast(unsigned *desc)
387 {
388 desc[1] |= R_DESC_1_RX_BROADCAST;
389 }
390
391 static inline void rx_desc_set_unicast_hash(unsigned *desc)
392 {
393 desc[1] |= R_DESC_1_RX_UNICAST_HASH;
394 }
395
396 static inline void rx_desc_set_multicast_hash(unsigned *desc)
397 {
398 desc[1] |= R_DESC_1_RX_MULTICAST_HASH;
399 }
400
401 static inline void rx_desc_set_sar(unsigned *desc, int sar_idx)
402 {
403 desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH,
404 sar_idx);
405 desc[1] |= R_DESC_1_RX_SAR_MATCH;
406 }
407
408 /* The broadcast MAC address: 0xFFFFFFFFFFFF */
409 static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
410
411 /*
412 * gem_init_register_masks:
413 * One time initialization.
414 * Set masks to identify which register bits have magical clear properties
415 */
416 static void gem_init_register_masks(CadenceGEMState *s)
417 {
418 /* Mask of register bits which are read only */
419 memset(&s->regs_ro[0], 0, sizeof(s->regs_ro));
420 s->regs_ro[GEM_NWCTRL] = 0xFFF80000;
421 s->regs_ro[GEM_NWSTATUS] = 0xFFFFFFFF;
422 s->regs_ro[GEM_DMACFG] = 0xFE00F000;
423 s->regs_ro[GEM_TXSTATUS] = 0xFFFFFE08;
424 s->regs_ro[GEM_RXQBASE] = 0x00000003;
425 s->regs_ro[GEM_TXQBASE] = 0x00000003;
426 s->regs_ro[GEM_RXSTATUS] = 0xFFFFFFF0;
427 s->regs_ro[GEM_ISR] = 0xFFFFFFFF;
428 s->regs_ro[GEM_IMR] = 0xFFFFFFFF;
429 s->regs_ro[GEM_MODID] = 0xFFFFFFFF;
430
431 /* Mask of register bits which are clear on read */
432 memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc));
433 s->regs_rtc[GEM_ISR] = 0xFFFFFFFF;
434
435 /* Mask of register bits which are write 1 to clear */
436 memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c));
437 s->regs_w1c[GEM_TXSTATUS] = 0x000001F7;
438 s->regs_w1c[GEM_RXSTATUS] = 0x0000000F;
439
440 /* Mask of register bits which are write only */
441 memset(&s->regs_wo[0], 0, sizeof(s->regs_wo));
442 s->regs_wo[GEM_NWCTRL] = 0x00073E60;
443 s->regs_wo[GEM_IER] = 0x07FFFFFF;
444 s->regs_wo[GEM_IDR] = 0x07FFFFFF;
445 }
446
447 /*
448 * phy_update_link:
449 * Make the emulated PHY link state match the QEMU "interface" state.
450 */
451 static void phy_update_link(CadenceGEMState *s)
452 {
453 DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down);
454
455 /* Autonegotiation status mirrors link status. */
456 if (qemu_get_queue(s->nic)->link_down) {
457 s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL |
458 PHY_REG_STATUS_LINK);
459 s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC;
460 } else {
461 s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL |
462 PHY_REG_STATUS_LINK);
463 s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC |
464 PHY_REG_INT_ST_ANEGCMPL |
465 PHY_REG_INT_ST_ENERGY);
466 }
467 }
468
469 static int gem_can_receive(NetClientState *nc)
470 {
471 CadenceGEMState *s;
472 int i;
473
474 s = qemu_get_nic_opaque(nc);
475
476 /* Do nothing if receive is not enabled. */
477 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_RXENA)) {
478 if (s->can_rx_state != 1) {
479 s->can_rx_state = 1;
480 DB_PRINT("can't receive - no enable\n");
481 }
482 return 0;
483 }
484
485 for (i = 0; i < s->num_priority_queues; i++) {
486 if (rx_desc_get_ownership(s->rx_desc[i]) != 1) {
487 break;
488 }
489 };
490
491 if (i == s->num_priority_queues) {
492 if (s->can_rx_state != 2) {
493 s->can_rx_state = 2;
494 DB_PRINT("can't receive - all the buffer descriptors are busy\n");
495 }
496 return 0;
497 }
498
499 if (s->can_rx_state != 0) {
500 s->can_rx_state = 0;
501 DB_PRINT("can receive\n");
502 }
503 return 1;
504 }
505
506 /*
507 * gem_update_int_status:
508 * Raise or lower interrupt based on current status.
509 */
510 static void gem_update_int_status(CadenceGEMState *s)
511 {
512 int i;
513
514 if (!s->regs[GEM_ISR]) {
515 /* ISR isn't set, clear all the interrupts */
516 for (i = 0; i < s->num_priority_queues; ++i) {
517 qemu_set_irq(s->irq[i], 0);
518 }
519 return;
520 }
521
522 /* If we get here we know s->regs[GEM_ISR] is set, so we don't need to
523 * check it again.
524 */
525 if (s->num_priority_queues == 1) {
526 /* No priority queues, just trigger the interrupt */
527 DB_PRINT("asserting int.\n");
528 qemu_set_irq(s->irq[0], 1);
529 return;
530 }
531
532 for (i = 0; i < s->num_priority_queues; ++i) {
533 if (s->regs[GEM_INT_Q1_STATUS + i]) {
534 DB_PRINT("asserting int. (q=%d)\n", i);
535 qemu_set_irq(s->irq[i], 1);
536 }
537 }
538 }
539
540 /*
541 * gem_receive_updatestats:
542 * Increment receive statistics.
543 */
544 static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet,
545 unsigned bytes)
546 {
547 uint64_t octets;
548
549 /* Total octets (bytes) received */
550 octets = ((uint64_t)(s->regs[GEM_OCTRXLO]) << 32) |
551 s->regs[GEM_OCTRXHI];
552 octets += bytes;
553 s->regs[GEM_OCTRXLO] = octets >> 32;
554 s->regs[GEM_OCTRXHI] = octets;
555
556 /* Error-free Frames received */
557 s->regs[GEM_RXCNT]++;
558
559 /* Error-free Broadcast Frames counter */
560 if (!memcmp(packet, broadcast_addr, 6)) {
561 s->regs[GEM_RXBROADCNT]++;
562 }
563
564 /* Error-free Multicast Frames counter */
565 if (packet[0] == 0x01) {
566 s->regs[GEM_RXMULTICNT]++;
567 }
568
569 if (bytes <= 64) {
570 s->regs[GEM_RX64CNT]++;
571 } else if (bytes <= 127) {
572 s->regs[GEM_RX65CNT]++;
573 } else if (bytes <= 255) {
574 s->regs[GEM_RX128CNT]++;
575 } else if (bytes <= 511) {
576 s->regs[GEM_RX256CNT]++;
577 } else if (bytes <= 1023) {
578 s->regs[GEM_RX512CNT]++;
579 } else if (bytes <= 1518) {
580 s->regs[GEM_RX1024CNT]++;
581 } else {
582 s->regs[GEM_RX1519CNT]++;
583 }
584 }
585
586 /*
587 * Get the MAC Address bit from the specified position
588 */
589 static unsigned get_bit(const uint8_t *mac, unsigned bit)
590 {
591 unsigned byte;
592
593 byte = mac[bit / 8];
594 byte >>= (bit & 0x7);
595 byte &= 1;
596
597 return byte;
598 }
599
600 /*
601 * Calculate a GEM MAC Address hash index
602 */
603 static unsigned calc_mac_hash(const uint8_t *mac)
604 {
605 int index_bit, mac_bit;
606 unsigned hash_index;
607
608 hash_index = 0;
609 mac_bit = 5;
610 for (index_bit = 5; index_bit >= 0; index_bit--) {
611 hash_index |= (get_bit(mac, mac_bit) ^
612 get_bit(mac, mac_bit + 6) ^
613 get_bit(mac, mac_bit + 12) ^
614 get_bit(mac, mac_bit + 18) ^
615 get_bit(mac, mac_bit + 24) ^
616 get_bit(mac, mac_bit + 30) ^
617 get_bit(mac, mac_bit + 36) ^
618 get_bit(mac, mac_bit + 42)) << index_bit;
619 mac_bit--;
620 }
621
622 return hash_index;
623 }
624
625 /*
626 * gem_mac_address_filter:
627 * Accept or reject this destination address?
628 * Returns:
629 * GEM_RX_REJECT: reject
630 * >= 0: Specific address accept (which matched SAR is returned)
631 * others for various other modes of accept:
632 * GEM_RM_PROMISCUOUS_ACCEPT, GEM_RX_BROADCAST_ACCEPT,
633 * GEM_RX_MULTICAST_HASH_ACCEPT or GEM_RX_UNICAST_HASH_ACCEPT
634 */
635 static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet)
636 {
637 uint8_t *gem_spaddr;
638 int i;
639
640 /* Promiscuous mode? */
641 if (s->regs[GEM_NWCFG] & GEM_NWCFG_PROMISC) {
642 return GEM_RX_PROMISCUOUS_ACCEPT;
643 }
644
645 if (!memcmp(packet, broadcast_addr, 6)) {
646 /* Reject broadcast packets? */
647 if (s->regs[GEM_NWCFG] & GEM_NWCFG_BCAST_REJ) {
648 return GEM_RX_REJECT;
649 }
650 return GEM_RX_BROADCAST_ACCEPT;
651 }
652
653 /* Accept packets -w- hash match? */
654 if ((packet[0] == 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) ||
655 (packet[0] != 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_UCAST_HASH))) {
656 unsigned hash_index;
657
658 hash_index = calc_mac_hash(packet);
659 if (hash_index < 32) {
660 if (s->regs[GEM_HASHLO] & (1<<hash_index)) {
661 return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT :
662 GEM_RX_UNICAST_HASH_ACCEPT;
663 }
664 } else {
665 hash_index -= 32;
666 if (s->regs[GEM_HASHHI] & (1<<hash_index)) {
667 return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT :
668 GEM_RX_UNICAST_HASH_ACCEPT;
669 }
670 }
671 }
672
673 /* Check all 4 specific addresses */
674 gem_spaddr = (uint8_t *)&(s->regs[GEM_SPADDR1LO]);
675 for (i = 3; i >= 0; i--) {
676 if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) {
677 return GEM_RX_SAR_ACCEPT + i;
678 }
679 }
680
681 /* No address match; reject the packet */
682 return GEM_RX_REJECT;
683 }
684
685 /* Figure out which queue the received data should be sent to */
686 static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
687 unsigned rxbufsize)
688 {
689 uint32_t reg;
690 bool matched, mismatched;
691 int i, j;
692
693 for (i = 0; i < s->num_type1_screeners; i++) {
694 reg = s->regs[GEM_SCREENING_TYPE1_REGISTER_0 + i];
695 matched = false;
696 mismatched = false;
697
698 /* Screening is based on UDP Port */
699 if (reg & GEM_ST1R_UDP_PORT_MATCH_ENABLE) {
700 uint16_t udp_port = rxbuf_ptr[14 + 22] << 8 | rxbuf_ptr[14 + 23];
701 if (udp_port == extract32(reg, GEM_ST1R_UDP_PORT_MATCH_SHIFT,
702 GEM_ST1R_UDP_PORT_MATCH_WIDTH)) {
703 matched = true;
704 } else {
705 mismatched = true;
706 }
707 }
708
709 /* Screening is based on DS/TC */
710 if (reg & GEM_ST1R_DSTC_ENABLE) {
711 uint8_t dscp = rxbuf_ptr[14 + 1];
712 if (dscp == extract32(reg, GEM_ST1R_DSTC_MATCH_SHIFT,
713 GEM_ST1R_DSTC_MATCH_WIDTH)) {
714 matched = true;
715 } else {
716 mismatched = true;
717 }
718 }
719
720 if (matched && !mismatched) {
721 return extract32(reg, GEM_ST1R_QUEUE_SHIFT, GEM_ST1R_QUEUE_WIDTH);
722 }
723 }
724
725 for (i = 0; i < s->num_type2_screeners; i++) {
726 reg = s->regs[GEM_SCREENING_TYPE2_REGISTER_0 + i];
727 matched = false;
728 mismatched = false;
729
730 if (reg & GEM_ST2R_ETHERTYPE_ENABLE) {
731 uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13];
732 int et_idx = extract32(reg, GEM_ST2R_ETHERTYPE_INDEX_SHIFT,
733 GEM_ST2R_ETHERTYPE_INDEX_WIDTH);
734
735 if (et_idx > s->num_type2_screeners) {
736 qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype "
737 "register index: %d\n", et_idx);
738 }
739 if (type == s->regs[GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 +
740 et_idx]) {
741 matched = true;
742 } else {
743 mismatched = true;
744 }
745 }
746
747 /* Compare A, B, C */
748 for (j = 0; j < 3; j++) {
749 uint32_t cr0, cr1, mask;
750 uint16_t rx_cmp;
751 int offset;
752 int cr_idx = extract32(reg, GEM_ST2R_COMPARE_A_SHIFT + j * 6,
753 GEM_ST2R_COMPARE_WIDTH);
754
755 if (!(reg & (GEM_ST2R_COMPARE_A_ENABLE << (j * 6)))) {
756 continue;
757 }
758 if (cr_idx > s->num_type2_screeners) {
759 qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare "
760 "register index: %d\n", cr_idx);
761 }
762
763 cr0 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2];
764 cr1 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1];
765 offset = extract32(cr1, GEM_T2CW1_OFFSET_VALUE_SHIFT,
766 GEM_T2CW1_OFFSET_VALUE_WIDTH);
767
768 switch (extract32(cr1, GEM_T2CW1_COMPARE_OFFSET_SHIFT,
769 GEM_T2CW1_COMPARE_OFFSET_WIDTH)) {
770 case 3: /* Skip UDP header */
771 qemu_log_mask(LOG_UNIMP, "TCP compare offsets"
772 "unimplemented - assuming UDP\n");
773 offset += 8;
774 /* Fallthrough */
775 case 2: /* skip the IP header */
776 offset += 20;
777 /* Fallthrough */
778 case 1: /* Count from after the ethertype */
779 offset += 14;
780 break;
781 case 0:
782 /* Offset from start of frame */
783 break;
784 }
785
786 rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset];
787 mask = extract32(cr0, 0, 16);
788
789 if ((rx_cmp & mask) == (extract32(cr0, 16, 16) & mask)) {
790 matched = true;
791 } else {
792 mismatched = true;
793 }
794 }
795
796 if (matched && !mismatched) {
797 return extract32(reg, GEM_ST2R_QUEUE_SHIFT, GEM_ST2R_QUEUE_WIDTH);
798 }
799 }
800
801 /* We made it here, assume it's queue 0 */
802 return 0;
803 }
804
805 static void gem_get_rx_desc(CadenceGEMState *s, int q)
806 {
807 DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr[q]);
808 /* read current descriptor */
809 cpu_physical_memory_read(s->rx_desc_addr[q],
810 (uint8_t *)s->rx_desc[q], sizeof(s->rx_desc[q]));
811
812 /* Descriptor owned by software ? */
813 if (rx_desc_get_ownership(s->rx_desc[q]) == 1) {
814 DB_PRINT("descriptor 0x%x owned by sw.\n",
815 (unsigned)s->rx_desc_addr[q]);
816 s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF;
817 s->regs[GEM_ISR] |= GEM_INT_RXUSED & ~(s->regs[GEM_IMR]);
818 /* Handle interrupt consequences */
819 gem_update_int_status(s);
820 }
821 }
822
823 /*
824 * gem_receive:
825 * Fit a packet handed to us by QEMU into the receive descriptor ring.
826 */
827 static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
828 {
829 CadenceGEMState *s;
830 unsigned rxbufsize, bytes_to_copy;
831 unsigned rxbuf_offset;
832 uint8_t rxbuf[2048];
833 uint8_t *rxbuf_ptr;
834 bool first_desc = true;
835 int maf;
836 int q = 0;
837
838 s = qemu_get_nic_opaque(nc);
839
840 /* Is this destination MAC address "for us" ? */
841 maf = gem_mac_address_filter(s, buf);
842 if (maf == GEM_RX_REJECT) {
843 return -1;
844 }
845
846 /* Discard packets with receive length error enabled ? */
847 if (s->regs[GEM_NWCFG] & GEM_NWCFG_LERR_DISC) {
848 unsigned type_len;
849
850 /* Fish the ethertype / length field out of the RX packet */
851 type_len = buf[12] << 8 | buf[13];
852 /* It is a length field, not an ethertype */
853 if (type_len < 0x600) {
854 if (size < type_len) {
855 /* discard */
856 return -1;
857 }
858 }
859 }
860
861 /*
862 * Determine configured receive buffer offset (probably 0)
863 */
864 rxbuf_offset = (s->regs[GEM_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >>
865 GEM_NWCFG_BUFF_OFST_S;
866
867 /* The configure size of each receive buffer. Determines how many
868 * buffers needed to hold this packet.
869 */
870 rxbufsize = ((s->regs[GEM_DMACFG] & GEM_DMACFG_RBUFSZ_M) >>
871 GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL;
872 bytes_to_copy = size;
873
874 /* Hardware allows a zero value here but warns against it. To avoid QEMU
875 * indefinite loops we enforce a minimum value here
876 */
877 if (rxbufsize < GEM_DMACFG_RBUFSZ_MUL) {
878 rxbufsize = GEM_DMACFG_RBUFSZ_MUL;
879 }
880
881 /* Pad to minimum length. Assume FCS field is stripped, logic
882 * below will increment it to the real minimum of 64 when
883 * not FCS stripping
884 */
885 if (size < 60) {
886 size = 60;
887 }
888
889 /* Strip of FCS field ? (usually yes) */
890 if (s->regs[GEM_NWCFG] & GEM_NWCFG_STRIP_FCS) {
891 rxbuf_ptr = (void *)buf;
892 } else {
893 unsigned crc_val;
894
895 if (size > sizeof(rxbuf) - sizeof(crc_val)) {
896 size = sizeof(rxbuf) - sizeof(crc_val);
897 }
898 bytes_to_copy = size;
899 /* The application wants the FCS field, which QEMU does not provide.
900 * We must try and calculate one.
901 */
902
903 memcpy(rxbuf, buf, size);
904 memset(rxbuf + size, 0, sizeof(rxbuf) - size);
905 rxbuf_ptr = rxbuf;
906 crc_val = cpu_to_le32(crc32(0, rxbuf, MAX(size, 60)));
907 memcpy(rxbuf + size, &crc_val, sizeof(crc_val));
908
909 bytes_to_copy += 4;
910 size += 4;
911 }
912
913 DB_PRINT("config bufsize: %d packet size: %ld\n", rxbufsize, size);
914
915 /* Find which queue we are targeting */
916 q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize);
917
918 while (bytes_to_copy) {
919 /* Do nothing if receive is not enabled. */
920 if (!gem_can_receive(nc)) {
921 assert(!first_desc);
922 return -1;
923 }
924
925 DB_PRINT("copy %d bytes to 0x%x\n", MIN(bytes_to_copy, rxbufsize),
926 rx_desc_get_buffer(s->rx_desc[q]));
927
928 /* Copy packet data to emulated DMA buffer */
929 cpu_physical_memory_write(rx_desc_get_buffer(s->rx_desc[q]) +
930 rxbuf_offset,
931 rxbuf_ptr, MIN(bytes_to_copy, rxbufsize));
932 rxbuf_ptr += MIN(bytes_to_copy, rxbufsize);
933 bytes_to_copy -= MIN(bytes_to_copy, rxbufsize);
934
935 /* Update the descriptor. */
936 if (first_desc) {
937 rx_desc_set_sof(s->rx_desc[q]);
938 first_desc = false;
939 }
940 if (bytes_to_copy == 0) {
941 rx_desc_set_eof(s->rx_desc[q]);
942 rx_desc_set_length(s->rx_desc[q], size);
943 }
944 rx_desc_set_ownership(s->rx_desc[q]);
945
946 switch (maf) {
947 case GEM_RX_PROMISCUOUS_ACCEPT:
948 break;
949 case GEM_RX_BROADCAST_ACCEPT:
950 rx_desc_set_broadcast(s->rx_desc[q]);
951 break;
952 case GEM_RX_UNICAST_HASH_ACCEPT:
953 rx_desc_set_unicast_hash(s->rx_desc[q]);
954 break;
955 case GEM_RX_MULTICAST_HASH_ACCEPT:
956 rx_desc_set_multicast_hash(s->rx_desc[q]);
957 break;
958 case GEM_RX_REJECT:
959 abort();
960 default: /* SAR */
961 rx_desc_set_sar(s->rx_desc[q], maf);
962 }
963
964 /* Descriptor write-back. */
965 cpu_physical_memory_write(s->rx_desc_addr[q],
966 (uint8_t *)s->rx_desc[q],
967 sizeof(s->rx_desc[q]));
968
969 /* Next descriptor */
970 if (rx_desc_get_wrap(s->rx_desc[q])) {
971 DB_PRINT("wrapping RX descriptor list\n");
972 s->rx_desc_addr[q] = s->regs[GEM_RXQBASE];
973 } else {
974 DB_PRINT("incrementing RX descriptor list\n");
975 s->rx_desc_addr[q] += 8;
976 }
977
978 gem_get_rx_desc(s, q);
979 }
980
981 /* Count it */
982 gem_receive_updatestats(s, buf, size);
983
984 s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD;
985 s->regs[GEM_ISR] |= GEM_INT_RXCMPL & ~(s->regs[GEM_IMR]);
986
987 /* Handle interrupt consequences */
988 gem_update_int_status(s);
989
990 return size;
991 }
992
993 /*
994 * gem_transmit_updatestats:
995 * Increment transmit statistics.
996 */
997 static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet,
998 unsigned bytes)
999 {
1000 uint64_t octets;
1001
1002 /* Total octets (bytes) transmitted */
1003 octets = ((uint64_t)(s->regs[GEM_OCTTXLO]) << 32) |
1004 s->regs[GEM_OCTTXHI];
1005 octets += bytes;
1006 s->regs[GEM_OCTTXLO] = octets >> 32;
1007 s->regs[GEM_OCTTXHI] = octets;
1008
1009 /* Error-free Frames transmitted */
1010 s->regs[GEM_TXCNT]++;
1011
1012 /* Error-free Broadcast Frames counter */
1013 if (!memcmp(packet, broadcast_addr, 6)) {
1014 s->regs[GEM_TXBCNT]++;
1015 }
1016
1017 /* Error-free Multicast Frames counter */
1018 if (packet[0] == 0x01) {
1019 s->regs[GEM_TXMCNT]++;
1020 }
1021
1022 if (bytes <= 64) {
1023 s->regs[GEM_TX64CNT]++;
1024 } else if (bytes <= 127) {
1025 s->regs[GEM_TX65CNT]++;
1026 } else if (bytes <= 255) {
1027 s->regs[GEM_TX128CNT]++;
1028 } else if (bytes <= 511) {
1029 s->regs[GEM_TX256CNT]++;
1030 } else if (bytes <= 1023) {
1031 s->regs[GEM_TX512CNT]++;
1032 } else if (bytes <= 1518) {
1033 s->regs[GEM_TX1024CNT]++;
1034 } else {
1035 s->regs[GEM_TX1519CNT]++;
1036 }
1037 }
1038
1039 /*
1040 * gem_transmit:
1041 * Fish packets out of the descriptor ring and feed them to QEMU
1042 */
1043 static void gem_transmit(CadenceGEMState *s)
1044 {
1045 unsigned desc[2];
1046 hwaddr packet_desc_addr;
1047 uint8_t tx_packet[2048];
1048 uint8_t *p;
1049 unsigned total_bytes;
1050 int q = 0;
1051
1052 /* Do nothing if transmit is not enabled. */
1053 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) {
1054 return;
1055 }
1056
1057 DB_PRINT("\n");
1058
1059 /* The packet we will hand off to QEMU.
1060 * Packets scattered across multiple descriptors are gathered to this
1061 * one contiguous buffer first.
1062 */
1063 p = tx_packet;
1064 total_bytes = 0;
1065
1066 for (q = s->num_priority_queues - 1; q >= 0; q--) {
1067 /* read current descriptor */
1068 packet_desc_addr = s->tx_desc_addr[q];
1069
1070 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr);
1071 cpu_physical_memory_read(packet_desc_addr,
1072 (uint8_t *)desc, sizeof(desc));
1073 /* Handle all descriptors owned by hardware */
1074 while (tx_desc_get_used(desc) == 0) {
1075
1076 /* Do nothing if transmit is not enabled. */
1077 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) {
1078 return;
1079 }
1080 print_gem_tx_desc(desc, q);
1081
1082 /* The real hardware would eat this (and possibly crash).
1083 * For QEMU let's lend a helping hand.
1084 */
1085 if ((tx_desc_get_buffer(desc) == 0) ||
1086 (tx_desc_get_length(desc) == 0)) {
1087 DB_PRINT("Invalid TX descriptor @ 0x%x\n",
1088 (unsigned)packet_desc_addr);
1089 break;
1090 }
1091
1092 if (tx_desc_get_length(desc) > sizeof(tx_packet) -
1093 (p - tx_packet)) {
1094 DB_PRINT("TX descriptor @ 0x%x too large: size 0x%x space " \
1095 "0x%x\n", (unsigned)packet_desc_addr,
1096 (unsigned)tx_desc_get_length(desc),
1097 sizeof(tx_packet) - (p - tx_packet));
1098 break;
1099 }
1100
1101 /* Gather this fragment of the packet from "dma memory" to our
1102 * contig buffer.
1103 */
1104 cpu_physical_memory_read(tx_desc_get_buffer(desc), p,
1105 tx_desc_get_length(desc));
1106 p += tx_desc_get_length(desc);
1107 total_bytes += tx_desc_get_length(desc);
1108
1109 /* Last descriptor for this packet; hand the whole thing off */
1110 if (tx_desc_get_last(desc)) {
1111 unsigned desc_first[2];
1112
1113 /* Modify the 1st descriptor of this packet to be owned by
1114 * the processor.
1115 */
1116 cpu_physical_memory_read(s->tx_desc_addr[q],
1117 (uint8_t *)desc_first,
1118 sizeof(desc_first));
1119 tx_desc_set_used(desc_first);
1120 cpu_physical_memory_write(s->tx_desc_addr[q],
1121 (uint8_t *)desc_first,
1122 sizeof(desc_first));
1123 /* Advance the hardware current descriptor past this packet */
1124 if (tx_desc_get_wrap(desc)) {
1125 s->tx_desc_addr[q] = s->regs[GEM_TXQBASE];
1126 } else {
1127 s->tx_desc_addr[q] = packet_desc_addr + 8;
1128 }
1129 DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]);
1130
1131 s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_TXCMPL;
1132 s->regs[GEM_ISR] |= GEM_INT_TXCMPL & ~(s->regs[GEM_IMR]);
1133
1134 /* Update queue interrupt status */
1135 if (s->num_priority_queues > 1) {
1136 s->regs[GEM_INT_Q1_STATUS + q] |=
1137 GEM_INT_TXCMPL & ~(s->regs[GEM_INT_Q1_MASK + q]);
1138 }
1139
1140 /* Handle interrupt consequences */
1141 gem_update_int_status(s);
1142
1143 /* Is checksum offload enabled? */
1144 if (s->regs[GEM_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) {
1145 net_checksum_calculate(tx_packet, total_bytes);
1146 }
1147
1148 /* Update MAC statistics */
1149 gem_transmit_updatestats(s, tx_packet, total_bytes);
1150
1151 /* Send the packet somewhere */
1152 if (s->phy_loop || (s->regs[GEM_NWCTRL] &
1153 GEM_NWCTRL_LOCALLOOP)) {
1154 gem_receive(qemu_get_queue(s->nic), tx_packet,
1155 total_bytes);
1156 } else {
1157 qemu_send_packet(qemu_get_queue(s->nic), tx_packet,
1158 total_bytes);
1159 }
1160
1161 /* Prepare for next packet */
1162 p = tx_packet;
1163 total_bytes = 0;
1164 }
1165
1166 /* read next descriptor */
1167 if (tx_desc_get_wrap(desc)) {
1168 tx_desc_set_last(desc);
1169 packet_desc_addr = s->regs[GEM_TXQBASE];
1170 } else {
1171 packet_desc_addr += 8;
1172 }
1173 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr);
1174 cpu_physical_memory_read(packet_desc_addr,
1175 (uint8_t *)desc, sizeof(desc));
1176 }
1177
1178 if (tx_desc_get_used(desc)) {
1179 s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_USED;
1180 s->regs[GEM_ISR] |= GEM_INT_TXUSED & ~(s->regs[GEM_IMR]);
1181 gem_update_int_status(s);
1182 }
1183 }
1184 }
1185
1186 static void gem_phy_reset(CadenceGEMState *s)
1187 {
1188 memset(&s->phy_regs[0], 0, sizeof(s->phy_regs));
1189 s->phy_regs[PHY_REG_CONTROL] = 0x1140;
1190 s->phy_regs[PHY_REG_STATUS] = 0x7969;
1191 s->phy_regs[PHY_REG_PHYID1] = 0x0141;
1192 s->phy_regs[PHY_REG_PHYID2] = 0x0CC2;
1193 s->phy_regs[PHY_REG_ANEGADV] = 0x01E1;
1194 s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1;
1195 s->phy_regs[PHY_REG_ANEGEXP] = 0x000F;
1196 s->phy_regs[PHY_REG_NEXTP] = 0x2001;
1197 s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6;
1198 s->phy_regs[PHY_REG_100BTCTRL] = 0x0300;
1199 s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00;
1200 s->phy_regs[PHY_REG_EXTSTAT] = 0x3000;
1201 s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078;
1202 s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00;
1203 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60;
1204 s->phy_regs[PHY_REG_LED] = 0x4100;
1205 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A;
1206 s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B;
1207
1208 phy_update_link(s);
1209 }
1210
1211 static void gem_reset(DeviceState *d)
1212 {
1213 int i;
1214 CadenceGEMState *s = CADENCE_GEM(d);
1215 const uint8_t *a;
1216
1217 DB_PRINT("\n");
1218
1219 /* Set post reset register values */
1220 memset(&s->regs[0], 0, sizeof(s->regs));
1221 s->regs[GEM_NWCFG] = 0x00080000;
1222 s->regs[GEM_NWSTATUS] = 0x00000006;
1223 s->regs[GEM_DMACFG] = 0x00020784;
1224 s->regs[GEM_IMR] = 0x07ffffff;
1225 s->regs[GEM_TXPAUSE] = 0x0000ffff;
1226 s->regs[GEM_TXPARTIALSF] = 0x000003ff;
1227 s->regs[GEM_RXPARTIALSF] = 0x000003ff;
1228 s->regs[GEM_MODID] = s->revision;
1229 s->regs[GEM_DESCONF] = 0x02500111;
1230 s->regs[GEM_DESCONF2] = 0x2ab13fff;
1231 s->regs[GEM_DESCONF5] = 0x002f2145;
1232 s->regs[GEM_DESCONF6] = 0x00000200;
1233
1234 /* Set MAC address */
1235 a = &s->conf.macaddr.a[0];
1236 s->regs[GEM_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24);
1237 s->regs[GEM_SPADDR1HI] = a[4] | (a[5] << 8);
1238
1239 for (i = 0; i < 4; i++) {
1240 s->sar_active[i] = false;
1241 }
1242
1243 gem_phy_reset(s);
1244
1245 gem_update_int_status(s);
1246 }
1247
1248 static uint16_t gem_phy_read(CadenceGEMState *s, unsigned reg_num)
1249 {
1250 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]);
1251 return s->phy_regs[reg_num];
1252 }
1253
1254 static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val)
1255 {
1256 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val);
1257
1258 switch (reg_num) {
1259 case PHY_REG_CONTROL:
1260 if (val & PHY_REG_CONTROL_RST) {
1261 /* Phy reset */
1262 gem_phy_reset(s);
1263 val &= ~(PHY_REG_CONTROL_RST | PHY_REG_CONTROL_LOOP);
1264 s->phy_loop = 0;
1265 }
1266 if (val & PHY_REG_CONTROL_ANEG) {
1267 /* Complete autonegotiation immediately */
1268 val &= ~PHY_REG_CONTROL_ANEG;
1269 s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL;
1270 }
1271 if (val & PHY_REG_CONTROL_LOOP) {
1272 DB_PRINT("PHY placed in loopback\n");
1273 s->phy_loop = 1;
1274 } else {
1275 s->phy_loop = 0;
1276 }
1277 break;
1278 }
1279 s->phy_regs[reg_num] = val;
1280 }
1281
1282 /*
1283 * gem_read32:
1284 * Read a GEM register.
1285 */
1286 static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
1287 {
1288 CadenceGEMState *s;
1289 uint32_t retval;
1290 s = (CadenceGEMState *)opaque;
1291
1292 offset >>= 2;
1293 retval = s->regs[offset];
1294
1295 DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval);
1296
1297 switch (offset) {
1298 case GEM_ISR:
1299 DB_PRINT("lowering irqs on ISR read\n");
1300 /* The interrupts get updated at the end of the function. */
1301 break;
1302 case GEM_PHYMNTNC:
1303 if (retval & GEM_PHYMNTNC_OP_R) {
1304 uint32_t phy_addr, reg_num;
1305
1306 phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
1307 if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
1308 reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
1309 retval &= 0xFFFF0000;
1310 retval |= gem_phy_read(s, reg_num);
1311 } else {
1312 retval |= 0xFFFF; /* No device at this address */
1313 }
1314 }
1315 break;
1316 }
1317
1318 /* Squash read to clear bits */
1319 s->regs[offset] &= ~(s->regs_rtc[offset]);
1320
1321 /* Do not provide write only bits */
1322 retval &= ~(s->regs_wo[offset]);
1323
1324 DB_PRINT("0x%08x\n", retval);
1325 gem_update_int_status(s);
1326 return retval;
1327 }
1328
1329 /*
1330 * gem_write32:
1331 * Write a GEM register.
1332 */
1333 static void gem_write(void *opaque, hwaddr offset, uint64_t val,
1334 unsigned size)
1335 {
1336 CadenceGEMState *s = (CadenceGEMState *)opaque;
1337 uint32_t readonly;
1338 int i;
1339
1340 DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val);
1341 offset >>= 2;
1342
1343 /* Squash bits which are read only in write value */
1344 val &= ~(s->regs_ro[offset]);
1345 /* Preserve (only) bits which are read only and wtc in register */
1346 readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]);
1347
1348 /* Copy register write to backing store */
1349 s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly;
1350
1351 /* do w1c */
1352 s->regs[offset] &= ~(s->regs_w1c[offset] & val);
1353
1354 /* Handle register write side effects */
1355 switch (offset) {
1356 case GEM_NWCTRL:
1357 if (val & GEM_NWCTRL_RXENA) {
1358 for (i = 0; i < s->num_priority_queues; ++i) {
1359 gem_get_rx_desc(s, i);
1360 }
1361 }
1362 if (val & GEM_NWCTRL_TXSTART) {
1363 gem_transmit(s);
1364 }
1365 if (!(val & GEM_NWCTRL_TXENA)) {
1366 /* Reset to start of Q when transmit disabled. */
1367 for (i = 0; i < s->num_priority_queues; i++) {
1368 s->tx_desc_addr[i] = s->regs[GEM_TXQBASE];
1369 }
1370 }
1371 if (gem_can_receive(qemu_get_queue(s->nic))) {
1372 qemu_flush_queued_packets(qemu_get_queue(s->nic));
1373 }
1374 break;
1375
1376 case GEM_TXSTATUS:
1377 gem_update_int_status(s);
1378 break;
1379 case GEM_RXQBASE:
1380 s->rx_desc_addr[0] = val;
1381 break;
1382 case GEM_RECEIVE_Q1_PTR ... GEM_RECEIVE_Q7_PTR:
1383 s->rx_desc_addr[offset - GEM_RECEIVE_Q1_PTR + 1] = val;
1384 break;
1385 case GEM_TXQBASE:
1386 s->tx_desc_addr[0] = val;
1387 break;
1388 case GEM_TRANSMIT_Q1_PTR ... GEM_TRANSMIT_Q7_PTR:
1389 s->tx_desc_addr[offset - GEM_TRANSMIT_Q1_PTR + 1] = val;
1390 break;
1391 case GEM_RXSTATUS:
1392 gem_update_int_status(s);
1393 break;
1394 case GEM_IER:
1395 s->regs[GEM_IMR] &= ~val;
1396 gem_update_int_status(s);
1397 break;
1398 case GEM_INT_Q1_ENABLE ... GEM_INT_Q7_ENABLE:
1399 s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_ENABLE] &= ~val;
1400 gem_update_int_status(s);
1401 break;
1402 case GEM_IDR:
1403 s->regs[GEM_IMR] |= val;
1404 gem_update_int_status(s);
1405 break;
1406 case GEM_INT_Q1_DISABLE ... GEM_INT_Q7_DISABLE:
1407 s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_DISABLE] |= val;
1408 gem_update_int_status(s);
1409 break;
1410 case GEM_SPADDR1LO:
1411 case GEM_SPADDR2LO:
1412 case GEM_SPADDR3LO:
1413 case GEM_SPADDR4LO:
1414 s->sar_active[(offset - GEM_SPADDR1LO) / 2] = false;
1415 break;
1416 case GEM_SPADDR1HI:
1417 case GEM_SPADDR2HI:
1418 case GEM_SPADDR3HI:
1419 case GEM_SPADDR4HI:
1420 s->sar_active[(offset - GEM_SPADDR1HI) / 2] = true;
1421 break;
1422 case GEM_PHYMNTNC:
1423 if (val & GEM_PHYMNTNC_OP_W) {
1424 uint32_t phy_addr, reg_num;
1425
1426 phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
1427 if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
1428 reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
1429 gem_phy_write(s, reg_num, val);
1430 }
1431 }
1432 break;
1433 }
1434
1435 DB_PRINT("newval: 0x%08x\n", s->regs[offset]);
1436 }
1437
1438 static const MemoryRegionOps gem_ops = {
1439 .read = gem_read,
1440 .write = gem_write,
1441 .endianness = DEVICE_LITTLE_ENDIAN,
1442 };
1443
1444 static void gem_set_link(NetClientState *nc)
1445 {
1446 CadenceGEMState *s = qemu_get_nic_opaque(nc);
1447
1448 DB_PRINT("\n");
1449 phy_update_link(s);
1450 gem_update_int_status(s);
1451 }
1452
1453 static NetClientInfo net_gem_info = {
1454 .type = NET_CLIENT_DRIVER_NIC,
1455 .size = sizeof(NICState),
1456 .can_receive = gem_can_receive,
1457 .receive = gem_receive,
1458 .link_status_changed = gem_set_link,
1459 };
1460
1461 static void gem_realize(DeviceState *dev, Error **errp)
1462 {
1463 CadenceGEMState *s = CADENCE_GEM(dev);
1464 int i;
1465
1466 if (s->num_priority_queues == 0 ||
1467 s->num_priority_queues > MAX_PRIORITY_QUEUES) {
1468 error_setg(errp, "Invalid num-priority-queues value: %" PRIx8,
1469 s->num_priority_queues);
1470 return;
1471 } else if (s->num_type1_screeners > MAX_TYPE1_SCREENERS) {
1472 error_setg(errp, "Invalid num-type1-screeners value: %" PRIx8,
1473 s->num_type1_screeners);
1474 return;
1475 } else if (s->num_type2_screeners > MAX_TYPE2_SCREENERS) {
1476 error_setg(errp, "Invalid num-type2-screeners value: %" PRIx8,
1477 s->num_type2_screeners);
1478 return;
1479 }
1480
1481 for (i = 0; i < s->num_priority_queues; ++i) {
1482 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
1483 }
1484
1485 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1486
1487 s->nic = qemu_new_nic(&net_gem_info, &s->conf,
1488 object_get_typename(OBJECT(dev)), dev->id, s);
1489 }
1490
1491 static void gem_init(Object *obj)
1492 {
1493 CadenceGEMState *s = CADENCE_GEM(obj);
1494 DeviceState *dev = DEVICE(obj);
1495
1496 DB_PRINT("\n");
1497
1498 gem_init_register_masks(s);
1499 memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s,
1500 "enet", sizeof(s->regs));
1501
1502 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
1503 }
1504
1505 static const VMStateDescription vmstate_cadence_gem = {
1506 .name = "cadence_gem",
1507 .version_id = 4,
1508 .minimum_version_id = 4,
1509 .fields = (VMStateField[]) {
1510 VMSTATE_UINT32_ARRAY(regs, CadenceGEMState, CADENCE_GEM_MAXREG),
1511 VMSTATE_UINT16_ARRAY(phy_regs, CadenceGEMState, 32),
1512 VMSTATE_UINT8(phy_loop, CadenceGEMState),
1513 VMSTATE_UINT32_ARRAY(rx_desc_addr, CadenceGEMState,
1514 MAX_PRIORITY_QUEUES),
1515 VMSTATE_UINT32_ARRAY(tx_desc_addr, CadenceGEMState,
1516 MAX_PRIORITY_QUEUES),
1517 VMSTATE_BOOL_ARRAY(sar_active, CadenceGEMState, 4),
1518 VMSTATE_END_OF_LIST(),
1519 }
1520 };
1521
1522 static Property gem_properties[] = {
1523 DEFINE_NIC_PROPERTIES(CadenceGEMState, conf),
1524 DEFINE_PROP_UINT32("revision", CadenceGEMState, revision,
1525 GEM_MODID_VALUE),
1526 DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState,
1527 num_priority_queues, 1),
1528 DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState,
1529 num_type1_screeners, 4),
1530 DEFINE_PROP_UINT8("num-type2-screeners", CadenceGEMState,
1531 num_type2_screeners, 4),
1532 DEFINE_PROP_END_OF_LIST(),
1533 };
1534
1535 static void gem_class_init(ObjectClass *klass, void *data)
1536 {
1537 DeviceClass *dc = DEVICE_CLASS(klass);
1538
1539 dc->realize = gem_realize;
1540 dc->props = gem_properties;
1541 dc->vmsd = &vmstate_cadence_gem;
1542 dc->reset = gem_reset;
1543 }
1544
1545 static const TypeInfo gem_info = {
1546 .name = TYPE_CADENCE_GEM,
1547 .parent = TYPE_SYS_BUS_DEVICE,
1548 .instance_size = sizeof(CadenceGEMState),
1549 .instance_init = gem_init,
1550 .class_init = gem_class_init,
1551 };
1552
1553 static void gem_register_types(void)
1554 {
1555 type_register_static(&gem_info);
1556 }
1557
1558 type_init(gem_register_types)