hw/arm/raspi: fix CPRMAN base address
[qemu.git] / hw / net / can / can_sja1000.h
1 /*
2 * CAN device - SJA1000 chip emulation for QEMU
3 *
4 * Copyright (c) 2013-2014 Jin Yang
5 * Copyright (c) 2014-2018 Pavel Pisa
6 *
7 * Initial development supported by Google GSoC 2013 from RTEMS project slot
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a copy
10 * of this software and associated documentation files (the "Software"), to deal
11 * in the Software without restriction, including without limitation the rights
12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13 * copies of the Software, and to permit persons to whom the Software is
14 * furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice shall be included in
17 * all copies or substantial portions of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 * THE SOFTWARE.
26 */
27 #ifndef HW_CAN_SJA1000_H
28 #define HW_CAN_SJA1000_H
29
30 #include "exec/hwaddr.h"
31 #include "net/can_emu.h"
32
33 #define CAN_SJA_MEM_SIZE 128
34
35 /* The max size for a message buffer, EFF and DLC=8, DS-p39 */
36 #define SJA_MSG_MAX_LEN 13
37 /* The receive buffer size. */
38 #define SJA_RCV_BUF_LEN 64
39
40 typedef struct CanSJA1000State {
41 /* PeliCAN state and registers sorted by address */
42 uint8_t mode; /* 0 .. Mode register, DS-p26 */
43 /* 1 .. Command register */
44 uint8_t status_pel; /* 2 .. Status register, p15 */
45 uint8_t interrupt_pel; /* 3 .. Interrupt register */
46 uint8_t interrupt_en; /* 4 .. Interrupt Enable register */
47 uint8_t rxmsg_cnt; /* 29 .. RX message counter. DS-p49 */
48 uint8_t rxbuf_start; /* 30 .. RX buffer start address, DS-p49 */
49 uint8_t clock; /* 31 .. Clock Divider register, DS-p55 */
50
51 uint8_t code_mask[8]; /* 16~23 */
52 uint8_t tx_buff[13]; /* 96~108 .. transmit buffer */
53 /* 10~19 .. transmit buffer for BasicCAN */
54
55 uint8_t rx_buff[SJA_RCV_BUF_LEN]; /* 32~95 .. 64bytes Rx FIFO */
56 uint32_t rx_ptr; /* Count by bytes. */
57 uint32_t rx_cnt; /* Count by bytes. */
58
59 /* PeliCAN state and registers sorted by address */
60 uint8_t control; /* 0 .. Control register */
61 /* 1 .. Command register */
62 uint8_t status_bas; /* 2 .. Status register */
63 uint8_t interrupt_bas; /* 3 .. Interrupt register */
64 uint8_t code; /* 4 .. Acceptance code register */
65 uint8_t mask; /* 5 .. Acceptance mask register */
66
67 qemu_can_filter filter[4];
68
69 qemu_irq irq;
70 CanBusClientState bus_client;
71 } CanSJA1000State;
72
73 /* PeliCAN mode */
74 enum SJA1000_PeliCAN_regs {
75 SJA_MOD = 0x00, /* Mode control register */
76 SJA_CMR = 0x01, /* Command register */
77 SJA_SR = 0x02, /* Status register */
78 SJA_IR = 0x03, /* Interrupt register */
79 SJA_IER = 0x04, /* Interrupt Enable */
80 SJA_BTR0 = 0x06, /* Bus Timing register 0 */
81 SJA_BTR1 = 0x07, /* Bus Timing register 1 */
82 SJA_OCR = 0x08, /* Output Control register */
83 SJA_ALC = 0x0b, /* Arbitration Lost Capture */
84 SJA_ECC = 0x0c, /* Error Code Capture */
85 SJA_EWLR = 0x0d, /* Error Warning Limit */
86 SJA_RXERR = 0x0e, /* RX Error Counter */
87 SJA_TXERR0 = 0x0e, /* TX Error Counter */
88 SJA_TXERR1 = 0x0f,
89 SJA_RMC = 0x1d, /* Rx Message Counter
90 * number of messages in RX FIFO
91 */
92 SJA_RBSA = 0x1e, /* Rx Buffer Start Addr
93 * address of current message
94 */
95 SJA_FRM = 0x10, /* Transmit Buffer
96 * write: Receive Buffer
97 * read: Frame Information
98 */
99 /*
100 * ID bytes (11 bits in 0 and 1 for standard message or
101 * 16 bits in 0,1 and 13 bits in 2,3 for extended message)
102 * The most significant bit of ID is placed in MSB
103 * position of ID0 register.
104 */
105 SJA_ID0 = 0x11, /* ID for standard and extended frames */
106 SJA_ID1 = 0x12,
107 SJA_ID2 = 0x13, /* ID cont. for extended frames */
108 SJA_ID3 = 0x14,
109
110 SJA_DATS = 0x13, /* Data start standard frame */
111 SJA_DATE = 0x15, /* Data start extended frame */
112 SJA_ACR0 = 0x10, /* Acceptance Code (4 bytes) in RESET mode */
113 SJA_AMR0 = 0x14, /* Acceptance Mask (4 bytes) in RESET mode */
114 SJA_PeliCAN_AC_LEN = 4, /* 4 bytes */
115 SJA_CDR = 0x1f /* Clock Divider */
116 };
117
118
119 /* BasicCAN mode */
120 enum SJA1000_BasicCAN_regs {
121 SJA_BCAN_CTR = 0x00, /* Control register */
122 SJA_BCAN_CMR = 0x01, /* Command register */
123 SJA_BCAN_SR = 0x02, /* Status register */
124 SJA_BCAN_IR = 0x03 /* Interrupt register */
125 };
126
127 void can_sja_hardware_reset(CanSJA1000State *s);
128
129 void can_sja_mem_write(CanSJA1000State *s, hwaddr addr, uint64_t val,
130 unsigned size);
131
132 uint64_t can_sja_mem_read(CanSJA1000State *s, hwaddr addr, unsigned size);
133
134 int can_sja_connect_to_bus(CanSJA1000State *s, CanBusState *bus);
135
136 void can_sja_disconnect(CanSJA1000State *s);
137
138 int can_sja_init(CanSJA1000State *s, qemu_irq irq);
139
140 bool can_sja_can_receive(CanBusClientState *client);
141
142 ssize_t can_sja_receive(CanBusClientState *client,
143 const qemu_can_frame *frames, size_t frames_cnt);
144
145 extern const VMStateDescription vmstate_can_sja;
146
147 #endif