hw/arm/bcm2836: Only provide "enabled-cpus" property to multicore SoCs
[qemu.git] / hw / net / dp8393x.c
1 /*
2 * QEMU NS SONIC DP8393x netcard
3 *
4 * Copyright (c) 2008-2009 Herve Poussineau
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "hw/irq.h"
22 #include "hw/qdev-properties.h"
23 #include "hw/sysbus.h"
24 #include "migration/vmstate.h"
25 #include "net/net.h"
26 #include "qapi/error.h"
27 #include "qemu/module.h"
28 #include "qemu/timer.h"
29 #include <zlib.h>
30 #include "qom/object.h"
31
32 //#define DEBUG_SONIC
33
34 #define SONIC_PROM_SIZE 0x1000
35
36 #ifdef DEBUG_SONIC
37 #define DPRINTF(fmt, ...) \
38 do { printf("sonic: " fmt , ## __VA_ARGS__); } while (0)
39 static const char* reg_names[] = {
40 "CR", "DCR", "RCR", "TCR", "IMR", "ISR", "UTDA", "CTDA",
41 "TPS", "TFC", "TSA0", "TSA1", "TFS", "URDA", "CRDA", "CRBA0",
42 "CRBA1", "RBWC0", "RBWC1", "EOBC", "URRA", "RSA", "REA", "RRP",
43 "RWP", "TRBA0", "TRBA1", "0x1b", "0x1c", "0x1d", "0x1e", "LLFA",
44 "TTDA", "CEP", "CAP2", "CAP1", "CAP0", "CE", "CDP", "CDC",
45 "SR", "WT0", "WT1", "RSC", "CRCT", "FAET", "MPT", "MDT",
46 "0x30", "0x31", "0x32", "0x33", "0x34", "0x35", "0x36", "0x37",
47 "0x38", "0x39", "0x3a", "0x3b", "0x3c", "0x3d", "0x3e", "DCR2" };
48 #else
49 #define DPRINTF(fmt, ...) do {} while (0)
50 #endif
51
52 #define SONIC_ERROR(fmt, ...) \
53 do { printf("sonic ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
54
55 #define SONIC_CR 0x00
56 #define SONIC_DCR 0x01
57 #define SONIC_RCR 0x02
58 #define SONIC_TCR 0x03
59 #define SONIC_IMR 0x04
60 #define SONIC_ISR 0x05
61 #define SONIC_UTDA 0x06
62 #define SONIC_CTDA 0x07
63 #define SONIC_TPS 0x08
64 #define SONIC_TFC 0x09
65 #define SONIC_TSA0 0x0a
66 #define SONIC_TSA1 0x0b
67 #define SONIC_TFS 0x0c
68 #define SONIC_URDA 0x0d
69 #define SONIC_CRDA 0x0e
70 #define SONIC_CRBA0 0x0f
71 #define SONIC_CRBA1 0x10
72 #define SONIC_RBWC0 0x11
73 #define SONIC_RBWC1 0x12
74 #define SONIC_EOBC 0x13
75 #define SONIC_URRA 0x14
76 #define SONIC_RSA 0x15
77 #define SONIC_REA 0x16
78 #define SONIC_RRP 0x17
79 #define SONIC_RWP 0x18
80 #define SONIC_TRBA0 0x19
81 #define SONIC_TRBA1 0x1a
82 #define SONIC_LLFA 0x1f
83 #define SONIC_TTDA 0x20
84 #define SONIC_CEP 0x21
85 #define SONIC_CAP2 0x22
86 #define SONIC_CAP1 0x23
87 #define SONIC_CAP0 0x24
88 #define SONIC_CE 0x25
89 #define SONIC_CDP 0x26
90 #define SONIC_CDC 0x27
91 #define SONIC_SR 0x28
92 #define SONIC_WT0 0x29
93 #define SONIC_WT1 0x2a
94 #define SONIC_RSC 0x2b
95 #define SONIC_CRCT 0x2c
96 #define SONIC_FAET 0x2d
97 #define SONIC_MPT 0x2e
98 #define SONIC_MDT 0x2f
99 #define SONIC_DCR2 0x3f
100
101 #define SONIC_CR_HTX 0x0001
102 #define SONIC_CR_TXP 0x0002
103 #define SONIC_CR_RXDIS 0x0004
104 #define SONIC_CR_RXEN 0x0008
105 #define SONIC_CR_STP 0x0010
106 #define SONIC_CR_ST 0x0020
107 #define SONIC_CR_RST 0x0080
108 #define SONIC_CR_RRRA 0x0100
109 #define SONIC_CR_LCAM 0x0200
110 #define SONIC_CR_MASK 0x03bf
111
112 #define SONIC_DCR_DW 0x0020
113 #define SONIC_DCR_LBR 0x2000
114 #define SONIC_DCR_EXBUS 0x8000
115
116 #define SONIC_RCR_PRX 0x0001
117 #define SONIC_RCR_LBK 0x0002
118 #define SONIC_RCR_FAER 0x0004
119 #define SONIC_RCR_CRCR 0x0008
120 #define SONIC_RCR_CRS 0x0020
121 #define SONIC_RCR_LPKT 0x0040
122 #define SONIC_RCR_BC 0x0080
123 #define SONIC_RCR_MC 0x0100
124 #define SONIC_RCR_LB0 0x0200
125 #define SONIC_RCR_LB1 0x0400
126 #define SONIC_RCR_AMC 0x0800
127 #define SONIC_RCR_PRO 0x1000
128 #define SONIC_RCR_BRD 0x2000
129 #define SONIC_RCR_RNT 0x4000
130
131 #define SONIC_TCR_PTX 0x0001
132 #define SONIC_TCR_BCM 0x0002
133 #define SONIC_TCR_FU 0x0004
134 #define SONIC_TCR_EXC 0x0040
135 #define SONIC_TCR_CRSL 0x0080
136 #define SONIC_TCR_NCRS 0x0100
137 #define SONIC_TCR_EXD 0x0400
138 #define SONIC_TCR_CRCI 0x2000
139 #define SONIC_TCR_PINT 0x8000
140
141 #define SONIC_ISR_RBAE 0x0010
142 #define SONIC_ISR_RBE 0x0020
143 #define SONIC_ISR_RDE 0x0040
144 #define SONIC_ISR_TC 0x0080
145 #define SONIC_ISR_TXDN 0x0200
146 #define SONIC_ISR_PKTRX 0x0400
147 #define SONIC_ISR_PINT 0x0800
148 #define SONIC_ISR_LCD 0x1000
149
150 #define SONIC_DESC_EOL 0x0001
151 #define SONIC_DESC_ADDR 0xFFFE
152
153 #define TYPE_DP8393X "dp8393x"
154 OBJECT_DECLARE_SIMPLE_TYPE(dp8393xState, DP8393X)
155
156 struct dp8393xState {
157 SysBusDevice parent_obj;
158
159 /* Hardware */
160 uint8_t it_shift;
161 bool big_endian;
162 bool last_rba_is_full;
163 qemu_irq irq;
164 #ifdef DEBUG_SONIC
165 int irq_level;
166 #endif
167 QEMUTimer *watchdog;
168 int64_t wt_last_update;
169 NICConf conf;
170 NICState *nic;
171 MemoryRegion mmio;
172 MemoryRegion prom;
173
174 /* Registers */
175 uint8_t cam[16][6];
176 uint16_t regs[0x40];
177
178 /* Temporaries */
179 uint8_t tx_buffer[0x10000];
180 uint16_t data[12];
181 int loopback_packet;
182
183 /* Memory access */
184 MemoryRegion *dma_mr;
185 AddressSpace as;
186 };
187
188 /* Accessor functions for values which are formed by
189 * concatenating two 16 bit device registers. By putting these
190 * in their own functions with a uint32_t return type we avoid the
191 * pitfall of implicit sign extension where ((x << 16) | y) is a
192 * signed 32 bit integer that might get sign-extended to a 64 bit integer.
193 */
194 static uint32_t dp8393x_cdp(dp8393xState *s)
195 {
196 return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_CDP];
197 }
198
199 static uint32_t dp8393x_crba(dp8393xState *s)
200 {
201 return (s->regs[SONIC_CRBA1] << 16) | s->regs[SONIC_CRBA0];
202 }
203
204 static uint32_t dp8393x_crda(dp8393xState *s)
205 {
206 return (s->regs[SONIC_URDA] << 16) |
207 (s->regs[SONIC_CRDA] & SONIC_DESC_ADDR);
208 }
209
210 static uint32_t dp8393x_rbwc(dp8393xState *s)
211 {
212 return (s->regs[SONIC_RBWC1] << 16) | s->regs[SONIC_RBWC0];
213 }
214
215 static uint32_t dp8393x_rrp(dp8393xState *s)
216 {
217 return (s->regs[SONIC_URRA] << 16) | s->regs[SONIC_RRP];
218 }
219
220 static uint32_t dp8393x_tsa(dp8393xState *s)
221 {
222 return (s->regs[SONIC_TSA1] << 16) | s->regs[SONIC_TSA0];
223 }
224
225 static uint32_t dp8393x_ttda(dp8393xState *s)
226 {
227 return (s->regs[SONIC_UTDA] << 16) |
228 (s->regs[SONIC_TTDA] & SONIC_DESC_ADDR);
229 }
230
231 static uint32_t dp8393x_wt(dp8393xState *s)
232 {
233 return s->regs[SONIC_WT1] << 16 | s->regs[SONIC_WT0];
234 }
235
236 static uint16_t dp8393x_get(dp8393xState *s, int width, int offset)
237 {
238 uint16_t val;
239
240 if (s->big_endian) {
241 val = be16_to_cpu(s->data[offset * width + width - 1]);
242 } else {
243 val = le16_to_cpu(s->data[offset * width]);
244 }
245 return val;
246 }
247
248 static void dp8393x_put(dp8393xState *s, int width, int offset,
249 uint16_t val)
250 {
251 if (s->big_endian) {
252 if (width == 2) {
253 s->data[offset * 2] = 0;
254 s->data[offset * 2 + 1] = cpu_to_be16(val);
255 } else {
256 s->data[offset] = cpu_to_be16(val);
257 }
258 } else {
259 if (width == 2) {
260 s->data[offset * 2] = cpu_to_le16(val);
261 s->data[offset * 2 + 1] = 0;
262 } else {
263 s->data[offset] = cpu_to_le16(val);
264 }
265 }
266 }
267
268 static void dp8393x_update_irq(dp8393xState *s)
269 {
270 int level = (s->regs[SONIC_IMR] & s->regs[SONIC_ISR]) ? 1 : 0;
271
272 #ifdef DEBUG_SONIC
273 if (level != s->irq_level) {
274 s->irq_level = level;
275 if (level) {
276 DPRINTF("raise irq, isr is 0x%04x\n", s->regs[SONIC_ISR]);
277 } else {
278 DPRINTF("lower irq\n");
279 }
280 }
281 #endif
282
283 qemu_set_irq(s->irq, level);
284 }
285
286 static void dp8393x_do_load_cam(dp8393xState *s)
287 {
288 int width, size;
289 uint16_t index = 0;
290
291 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
292 size = sizeof(uint16_t) * 4 * width;
293
294 while (s->regs[SONIC_CDC] & 0x1f) {
295 /* Fill current entry */
296 address_space_read(&s->as, dp8393x_cdp(s),
297 MEMTXATTRS_UNSPECIFIED, s->data, size);
298 s->cam[index][0] = dp8393x_get(s, width, 1) & 0xff;
299 s->cam[index][1] = dp8393x_get(s, width, 1) >> 8;
300 s->cam[index][2] = dp8393x_get(s, width, 2) & 0xff;
301 s->cam[index][3] = dp8393x_get(s, width, 2) >> 8;
302 s->cam[index][4] = dp8393x_get(s, width, 3) & 0xff;
303 s->cam[index][5] = dp8393x_get(s, width, 3) >> 8;
304 DPRINTF("load cam[%d] with %02x%02x%02x%02x%02x%02x\n", index,
305 s->cam[index][0], s->cam[index][1], s->cam[index][2],
306 s->cam[index][3], s->cam[index][4], s->cam[index][5]);
307 /* Move to next entry */
308 s->regs[SONIC_CDC]--;
309 s->regs[SONIC_CDP] += size;
310 index++;
311 }
312
313 /* Read CAM enable */
314 address_space_read(&s->as, dp8393x_cdp(s),
315 MEMTXATTRS_UNSPECIFIED, s->data, size);
316 s->regs[SONIC_CE] = dp8393x_get(s, width, 0);
317 DPRINTF("load cam done. cam enable mask 0x%04x\n", s->regs[SONIC_CE]);
318
319 /* Done */
320 s->regs[SONIC_CR] &= ~SONIC_CR_LCAM;
321 s->regs[SONIC_ISR] |= SONIC_ISR_LCD;
322 dp8393x_update_irq(s);
323 }
324
325 static void dp8393x_do_read_rra(dp8393xState *s)
326 {
327 int width, size;
328
329 /* Read memory */
330 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
331 size = sizeof(uint16_t) * 4 * width;
332 address_space_read(&s->as, dp8393x_rrp(s),
333 MEMTXATTRS_UNSPECIFIED, s->data, size);
334
335 /* Update SONIC registers */
336 s->regs[SONIC_CRBA0] = dp8393x_get(s, width, 0);
337 s->regs[SONIC_CRBA1] = dp8393x_get(s, width, 1);
338 s->regs[SONIC_RBWC0] = dp8393x_get(s, width, 2);
339 s->regs[SONIC_RBWC1] = dp8393x_get(s, width, 3);
340 DPRINTF("CRBA0/1: 0x%04x/0x%04x, RBWC0/1: 0x%04x/0x%04x\n",
341 s->regs[SONIC_CRBA0], s->regs[SONIC_CRBA1],
342 s->regs[SONIC_RBWC0], s->regs[SONIC_RBWC1]);
343
344 /* Go to next entry */
345 s->regs[SONIC_RRP] += size;
346
347 /* Handle wrap */
348 if (s->regs[SONIC_RRP] == s->regs[SONIC_REA]) {
349 s->regs[SONIC_RRP] = s->regs[SONIC_RSA];
350 }
351
352 /* Warn the host if CRBA now has the last available resource */
353 if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP])
354 {
355 s->regs[SONIC_ISR] |= SONIC_ISR_RBE;
356 dp8393x_update_irq(s);
357 }
358
359 /* Allow packet reception */
360 s->last_rba_is_full = false;
361 }
362
363 static void dp8393x_do_software_reset(dp8393xState *s)
364 {
365 timer_del(s->watchdog);
366
367 s->regs[SONIC_CR] &= ~(SONIC_CR_LCAM | SONIC_CR_RRRA | SONIC_CR_TXP | SONIC_CR_HTX);
368 s->regs[SONIC_CR] |= SONIC_CR_RST | SONIC_CR_RXDIS;
369 }
370
371 static void dp8393x_set_next_tick(dp8393xState *s)
372 {
373 uint32_t ticks;
374 int64_t delay;
375
376 if (s->regs[SONIC_CR] & SONIC_CR_STP) {
377 timer_del(s->watchdog);
378 return;
379 }
380
381 ticks = dp8393x_wt(s);
382 s->wt_last_update = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
383 delay = NANOSECONDS_PER_SECOND * ticks / 5000000;
384 timer_mod(s->watchdog, s->wt_last_update + delay);
385 }
386
387 static void dp8393x_update_wt_regs(dp8393xState *s)
388 {
389 int64_t elapsed;
390 uint32_t val;
391
392 if (s->regs[SONIC_CR] & SONIC_CR_STP) {
393 timer_del(s->watchdog);
394 return;
395 }
396
397 elapsed = s->wt_last_update - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
398 val = dp8393x_wt(s);
399 val -= elapsed / 5000000;
400 s->regs[SONIC_WT1] = (val >> 16) & 0xffff;
401 s->regs[SONIC_WT0] = (val >> 0) & 0xffff;
402 dp8393x_set_next_tick(s);
403
404 }
405
406 static void dp8393x_do_start_timer(dp8393xState *s)
407 {
408 s->regs[SONIC_CR] &= ~SONIC_CR_STP;
409 dp8393x_set_next_tick(s);
410 }
411
412 static void dp8393x_do_stop_timer(dp8393xState *s)
413 {
414 s->regs[SONIC_CR] &= ~SONIC_CR_ST;
415 dp8393x_update_wt_regs(s);
416 }
417
418 static bool dp8393x_can_receive(NetClientState *nc);
419
420 static void dp8393x_do_receiver_enable(dp8393xState *s)
421 {
422 s->regs[SONIC_CR] &= ~SONIC_CR_RXDIS;
423 if (dp8393x_can_receive(s->nic->ncs)) {
424 qemu_flush_queued_packets(qemu_get_queue(s->nic));
425 }
426 }
427
428 static void dp8393x_do_receiver_disable(dp8393xState *s)
429 {
430 s->regs[SONIC_CR] &= ~SONIC_CR_RXEN;
431 }
432
433 static void dp8393x_do_transmit_packets(dp8393xState *s)
434 {
435 NetClientState *nc = qemu_get_queue(s->nic);
436 int width, size;
437 int tx_len, len;
438 uint16_t i;
439
440 width = (s->regs[SONIC_DCR] & SONIC_DCR_DW) ? 2 : 1;
441
442 while (1) {
443 /* Read memory */
444 size = sizeof(uint16_t) * 6 * width;
445 s->regs[SONIC_TTDA] = s->regs[SONIC_CTDA];
446 DPRINTF("Transmit packet at %08x\n", dp8393x_ttda(s));
447 address_space_read(&s->as, dp8393x_ttda(s) + sizeof(uint16_t) * width,
448 MEMTXATTRS_UNSPECIFIED, s->data, size);
449 tx_len = 0;
450
451 /* Update registers */
452 s->regs[SONIC_TCR] = dp8393x_get(s, width, 0) & 0xf000;
453 s->regs[SONIC_TPS] = dp8393x_get(s, width, 1);
454 s->regs[SONIC_TFC] = dp8393x_get(s, width, 2);
455 s->regs[SONIC_TSA0] = dp8393x_get(s, width, 3);
456 s->regs[SONIC_TSA1] = dp8393x_get(s, width, 4);
457 s->regs[SONIC_TFS] = dp8393x_get(s, width, 5);
458
459 /* Handle programmable interrupt */
460 if (s->regs[SONIC_TCR] & SONIC_TCR_PINT) {
461 s->regs[SONIC_ISR] |= SONIC_ISR_PINT;
462 } else {
463 s->regs[SONIC_ISR] &= ~SONIC_ISR_PINT;
464 }
465
466 for (i = 0; i < s->regs[SONIC_TFC]; ) {
467 /* Append fragment */
468 len = s->regs[SONIC_TFS];
469 if (tx_len + len > sizeof(s->tx_buffer)) {
470 len = sizeof(s->tx_buffer) - tx_len;
471 }
472 address_space_read(&s->as, dp8393x_tsa(s), MEMTXATTRS_UNSPECIFIED,
473 &s->tx_buffer[tx_len], len);
474 tx_len += len;
475
476 i++;
477 if (i != s->regs[SONIC_TFC]) {
478 /* Read next fragment details */
479 size = sizeof(uint16_t) * 3 * width;
480 address_space_read(&s->as,
481 dp8393x_ttda(s)
482 + sizeof(uint16_t) * width * (4 + 3 * i),
483 MEMTXATTRS_UNSPECIFIED, s->data,
484 size);
485 s->regs[SONIC_TSA0] = dp8393x_get(s, width, 0);
486 s->regs[SONIC_TSA1] = dp8393x_get(s, width, 1);
487 s->regs[SONIC_TFS] = dp8393x_get(s, width, 2);
488 }
489 }
490
491 /* Handle Ethernet checksum */
492 if (!(s->regs[SONIC_TCR] & SONIC_TCR_CRCI)) {
493 /* Don't append FCS there, to look like slirp packets
494 * which don't have one */
495 } else {
496 /* Remove existing FCS */
497 tx_len -= 4;
498 }
499
500 if (s->regs[SONIC_RCR] & (SONIC_RCR_LB1 | SONIC_RCR_LB0)) {
501 /* Loopback */
502 s->regs[SONIC_TCR] |= SONIC_TCR_CRSL;
503 if (nc->info->can_receive(nc)) {
504 s->loopback_packet = 1;
505 nc->info->receive(nc, s->tx_buffer, tx_len);
506 }
507 } else {
508 /* Transmit packet */
509 qemu_send_packet(nc, s->tx_buffer, tx_len);
510 }
511 s->regs[SONIC_TCR] |= SONIC_TCR_PTX;
512
513 /* Write status */
514 dp8393x_put(s, width, 0,
515 s->regs[SONIC_TCR] & 0x0fff); /* status */
516 size = sizeof(uint16_t) * width;
517 address_space_write(&s->as, dp8393x_ttda(s),
518 MEMTXATTRS_UNSPECIFIED, s->data, size);
519
520 if (!(s->regs[SONIC_CR] & SONIC_CR_HTX)) {
521 /* Read footer of packet */
522 size = sizeof(uint16_t) * width;
523 address_space_read(&s->as,
524 dp8393x_ttda(s)
525 + sizeof(uint16_t) * width
526 * (4 + 3 * s->regs[SONIC_TFC]),
527 MEMTXATTRS_UNSPECIFIED, s->data,
528 size);
529 s->regs[SONIC_CTDA] = dp8393x_get(s, width, 0);
530 if (s->regs[SONIC_CTDA] & SONIC_DESC_EOL) {
531 /* EOL detected */
532 break;
533 }
534 }
535 }
536
537 /* Done */
538 s->regs[SONIC_CR] &= ~SONIC_CR_TXP;
539 s->regs[SONIC_ISR] |= SONIC_ISR_TXDN;
540 dp8393x_update_irq(s);
541 }
542
543 static void dp8393x_do_halt_transmission(dp8393xState *s)
544 {
545 /* Nothing to do */
546 }
547
548 static void dp8393x_do_command(dp8393xState *s, uint16_t command)
549 {
550 if ((s->regs[SONIC_CR] & SONIC_CR_RST) && !(command & SONIC_CR_RST)) {
551 s->regs[SONIC_CR] &= ~SONIC_CR_RST;
552 return;
553 }
554
555 s->regs[SONIC_CR] |= (command & SONIC_CR_MASK);
556
557 if (command & SONIC_CR_HTX)
558 dp8393x_do_halt_transmission(s);
559 if (command & SONIC_CR_TXP)
560 dp8393x_do_transmit_packets(s);
561 if (command & SONIC_CR_RXDIS)
562 dp8393x_do_receiver_disable(s);
563 if (command & SONIC_CR_RXEN)
564 dp8393x_do_receiver_enable(s);
565 if (command & SONIC_CR_STP)
566 dp8393x_do_stop_timer(s);
567 if (command & SONIC_CR_ST)
568 dp8393x_do_start_timer(s);
569 if (command & SONIC_CR_RST)
570 dp8393x_do_software_reset(s);
571 if (command & SONIC_CR_RRRA) {
572 dp8393x_do_read_rra(s);
573 s->regs[SONIC_CR] &= ~SONIC_CR_RRRA;
574 }
575 if (command & SONIC_CR_LCAM)
576 dp8393x_do_load_cam(s);
577 }
578
579 static uint64_t dp8393x_read(void *opaque, hwaddr addr, unsigned int size)
580 {
581 dp8393xState *s = opaque;
582 int reg = addr >> s->it_shift;
583 uint16_t val = 0;
584
585 switch (reg) {
586 /* Update data before reading it */
587 case SONIC_WT0:
588 case SONIC_WT1:
589 dp8393x_update_wt_regs(s);
590 val = s->regs[reg];
591 break;
592 /* Accept read to some registers only when in reset mode */
593 case SONIC_CAP2:
594 case SONIC_CAP1:
595 case SONIC_CAP0:
596 if (s->regs[SONIC_CR] & SONIC_CR_RST) {
597 val = s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg) + 1] << 8;
598 val |= s->cam[s->regs[SONIC_CEP] & 0xf][2* (SONIC_CAP0 - reg)];
599 }
600 break;
601 /* All other registers have no special contrainst */
602 default:
603 val = s->regs[reg];
604 }
605
606 DPRINTF("read 0x%04x from reg %s\n", val, reg_names[reg]);
607
608 return s->big_endian ? val << 16 : val;
609 }
610
611 static void dp8393x_write(void *opaque, hwaddr addr, uint64_t data,
612 unsigned int size)
613 {
614 dp8393xState *s = opaque;
615 int reg = addr >> s->it_shift;
616 uint32_t val = s->big_endian ? data >> 16 : data;
617
618 DPRINTF("write 0x%04x to reg %s\n", (uint16_t)val, reg_names[reg]);
619
620 switch (reg) {
621 /* Command register */
622 case SONIC_CR:
623 dp8393x_do_command(s, val);
624 break;
625 /* Prevent write to read-only registers */
626 case SONIC_CAP2:
627 case SONIC_CAP1:
628 case SONIC_CAP0:
629 case SONIC_SR:
630 case SONIC_MDT:
631 DPRINTF("writing to reg %d invalid\n", reg);
632 break;
633 /* Accept write to some registers only when in reset mode */
634 case SONIC_DCR:
635 if (s->regs[SONIC_CR] & SONIC_CR_RST) {
636 s->regs[reg] = val & 0xbfff;
637 } else {
638 DPRINTF("writing to DCR invalid\n");
639 }
640 break;
641 case SONIC_DCR2:
642 if (s->regs[SONIC_CR] & SONIC_CR_RST) {
643 s->regs[reg] = val & 0xf017;
644 } else {
645 DPRINTF("writing to DCR2 invalid\n");
646 }
647 break;
648 /* 12 lower bytes are Read Only */
649 case SONIC_TCR:
650 s->regs[reg] = val & 0xf000;
651 break;
652 /* 9 lower bytes are Read Only */
653 case SONIC_RCR:
654 s->regs[reg] = val & 0xffe0;
655 break;
656 /* Ignore most significant bit */
657 case SONIC_IMR:
658 s->regs[reg] = val & 0x7fff;
659 dp8393x_update_irq(s);
660 break;
661 /* Clear bits by writing 1 to them */
662 case SONIC_ISR:
663 val &= s->regs[reg];
664 s->regs[reg] &= ~val;
665 if (val & SONIC_ISR_RBE) {
666 dp8393x_do_read_rra(s);
667 }
668 dp8393x_update_irq(s);
669 break;
670 /* The guest is required to store aligned pointers here */
671 case SONIC_RSA:
672 case SONIC_REA:
673 case SONIC_RRP:
674 case SONIC_RWP:
675 if (s->regs[SONIC_DCR] & SONIC_DCR_DW) {
676 s->regs[reg] = val & 0xfffc;
677 } else {
678 s->regs[reg] = val & 0xfffe;
679 }
680 break;
681 /* Invert written value for some registers */
682 case SONIC_CRCT:
683 case SONIC_FAET:
684 case SONIC_MPT:
685 s->regs[reg] = val ^ 0xffff;
686 break;
687 /* All other registers have no special contrainst */
688 default:
689 s->regs[reg] = val;
690 }
691
692 if (reg == SONIC_WT0 || reg == SONIC_WT1) {
693 dp8393x_set_next_tick(s);
694 }
695 }
696
697 static const MemoryRegionOps dp8393x_ops = {
698 .read = dp8393x_read,
699 .write = dp8393x_write,
700 .impl.min_access_size = 4,
701 .impl.max_access_size = 4,
702 .endianness = DEVICE_NATIVE_ENDIAN,
703 };
704
705 static void dp8393x_watchdog(void *opaque)
706 {
707 dp8393xState *s = opaque;
708
709 if (s->regs[SONIC_CR] & SONIC_CR_STP) {
710 return;
711 }
712
713 s->regs[SONIC_WT1] = 0xffff;
714 s->regs[SONIC_WT0] = 0xffff;
715 dp8393x_set_next_tick(s);
716
717 /* Signal underflow */
718 s->regs[SONIC_ISR] |= SONIC_ISR_TC;
719 dp8393x_update_irq(s);
720 }
721
722 static bool dp8393x_can_receive(NetClientState *nc)
723 {
724 dp8393xState *s = qemu_get_nic_opaque(nc);
725
726 return !!(s->regs[SONIC_CR] & SONIC_CR_RXEN);
727 }
728
729 static int dp8393x_receive_filter(dp8393xState *s, const uint8_t * buf,
730 int size)
731 {
732 static const uint8_t bcast[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
733 int i;
734
735 /* Check promiscuous mode */
736 if ((s->regs[SONIC_RCR] & SONIC_RCR_PRO) && (buf[0] & 1) == 0) {
737 return 0;
738 }
739
740 /* Check multicast packets */
741 if ((s->regs[SONIC_RCR] & SONIC_RCR_AMC) && (buf[0] & 1) == 1) {
742 return SONIC_RCR_MC;
743 }
744
745 /* Check broadcast */
746 if ((s->regs[SONIC_RCR] & SONIC_RCR_BRD) && !memcmp(buf, bcast, sizeof(bcast))) {
747 return SONIC_RCR_BC;
748 }
749
750 /* Check CAM */
751 for (i = 0; i < 16; i++) {
752 if (s->regs[SONIC_CE] & (1 << i)) {
753 /* Entry enabled */
754 if (!memcmp(buf, s->cam[i], sizeof(s->cam[i]))) {
755 return 0;
756 }
757 }
758 }
759
760 return -1;
761 }
762
763 static ssize_t dp8393x_receive(NetClientState *nc, const uint8_t * buf,
764 size_t pkt_size)
765 {
766 dp8393xState *s = qemu_get_nic_opaque(nc);
767 int packet_type;
768 uint32_t available, address;
769 int width, rx_len, padded_len;
770 uint32_t checksum;
771 int size;
772
773 s->regs[SONIC_RCR] &= ~(SONIC_RCR_PRX | SONIC_RCR_LBK | SONIC_RCR_FAER |
774 SONIC_RCR_CRCR | SONIC_RCR_LPKT | SONIC_RCR_BC | SONIC_RCR_MC);
775
776 if (s->last_rba_is_full) {
777 return pkt_size;
778 }
779
780 rx_len = pkt_size + sizeof(checksum);
781 if (s->regs[SONIC_DCR] & SONIC_DCR_DW) {
782 width = 2;
783 padded_len = ((rx_len - 1) | 3) + 1;
784 } else {
785 width = 1;
786 padded_len = ((rx_len - 1) | 1) + 1;
787 }
788
789 if (padded_len > dp8393x_rbwc(s) * 2) {
790 DPRINTF("oversize packet, pkt_size is %d\n", pkt_size);
791 s->regs[SONIC_ISR] |= SONIC_ISR_RBAE;
792 dp8393x_update_irq(s);
793 s->regs[SONIC_RCR] |= SONIC_RCR_LPKT;
794 goto done;
795 }
796
797 packet_type = dp8393x_receive_filter(s, buf, pkt_size);
798 if (packet_type < 0) {
799 DPRINTF("packet not for netcard\n");
800 return -1;
801 }
802
803 /* Check for EOL */
804 if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) {
805 /* Are we still in resource exhaustion? */
806 size = sizeof(uint16_t) * 1 * width;
807 address = dp8393x_crda(s) + sizeof(uint16_t) * 5 * width;
808 address_space_read(&s->as, address, MEMTXATTRS_UNSPECIFIED,
809 s->data, size);
810 s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0);
811 if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) {
812 /* Still EOL ; stop reception */
813 return -1;
814 }
815 /* Link has been updated by host */
816
817 /* Clear in_use */
818 size = sizeof(uint16_t) * width;
819 address = dp8393x_crda(s) + sizeof(uint16_t) * 6 * width;
820 dp8393x_put(s, width, 0, 0);
821 address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED,
822 (uint8_t *)s->data, size, 1);
823
824 /* Move to next descriptor */
825 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
826 s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX;
827 }
828
829 /* Save current position */
830 s->regs[SONIC_TRBA1] = s->regs[SONIC_CRBA1];
831 s->regs[SONIC_TRBA0] = s->regs[SONIC_CRBA0];
832
833 /* Calculate the ethernet checksum */
834 checksum = cpu_to_le32(crc32(0, buf, pkt_size));
835
836 /* Put packet into RBA */
837 DPRINTF("Receive packet at %08x\n", dp8393x_crba(s));
838 address = dp8393x_crba(s);
839 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED,
840 buf, pkt_size);
841 address += pkt_size;
842
843 /* Put frame checksum into RBA */
844 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED,
845 &checksum, sizeof(checksum));
846 address += sizeof(checksum);
847
848 /* Pad short packets to keep pointers aligned */
849 if (rx_len < padded_len) {
850 size = padded_len - rx_len;
851 address_space_rw(&s->as, address, MEMTXATTRS_UNSPECIFIED,
852 (uint8_t *)"\xFF\xFF\xFF", size, 1);
853 address += size;
854 }
855
856 s->regs[SONIC_CRBA1] = address >> 16;
857 s->regs[SONIC_CRBA0] = address & 0xffff;
858 available = dp8393x_rbwc(s);
859 available -= padded_len >> 1;
860 s->regs[SONIC_RBWC1] = available >> 16;
861 s->regs[SONIC_RBWC0] = available & 0xffff;
862
863 /* Update status */
864 if (dp8393x_rbwc(s) < s->regs[SONIC_EOBC]) {
865 s->regs[SONIC_RCR] |= SONIC_RCR_LPKT;
866 }
867 s->regs[SONIC_RCR] |= packet_type;
868 s->regs[SONIC_RCR] |= SONIC_RCR_PRX;
869 if (s->loopback_packet) {
870 s->regs[SONIC_RCR] |= SONIC_RCR_LBK;
871 s->loopback_packet = 0;
872 }
873
874 /* Write status to memory */
875 DPRINTF("Write status at %08x\n", dp8393x_crda(s));
876 dp8393x_put(s, width, 0, s->regs[SONIC_RCR]); /* status */
877 dp8393x_put(s, width, 1, rx_len); /* byte count */
878 dp8393x_put(s, width, 2, s->regs[SONIC_TRBA0]); /* pkt_ptr0 */
879 dp8393x_put(s, width, 3, s->regs[SONIC_TRBA1]); /* pkt_ptr1 */
880 dp8393x_put(s, width, 4, s->regs[SONIC_RSC]); /* seq_no */
881 size = sizeof(uint16_t) * 5 * width;
882 address_space_write(&s->as, dp8393x_crda(s),
883 MEMTXATTRS_UNSPECIFIED,
884 s->data, size);
885
886 /* Check link field */
887 size = sizeof(uint16_t) * width;
888 address_space_read(&s->as,
889 dp8393x_crda(s) + sizeof(uint16_t) * 5 * width,
890 MEMTXATTRS_UNSPECIFIED, s->data, size);
891 s->regs[SONIC_LLFA] = dp8393x_get(s, width, 0);
892 if (s->regs[SONIC_LLFA] & SONIC_DESC_EOL) {
893 /* EOL detected */
894 s->regs[SONIC_ISR] |= SONIC_ISR_RDE;
895 } else {
896 /* Clear in_use */
897 size = sizeof(uint16_t) * width;
898 address = dp8393x_crda(s) + sizeof(uint16_t) * 6 * width;
899 dp8393x_put(s, width, 0, 0);
900 address_space_write(&s->as, address, MEMTXATTRS_UNSPECIFIED,
901 s->data, size);
902
903 /* Move to next descriptor */
904 s->regs[SONIC_CRDA] = s->regs[SONIC_LLFA];
905 s->regs[SONIC_ISR] |= SONIC_ISR_PKTRX;
906 }
907
908 dp8393x_update_irq(s);
909
910 s->regs[SONIC_RSC] = (s->regs[SONIC_RSC] & 0xff00) |
911 ((s->regs[SONIC_RSC] + 1) & 0x00ff);
912
913 done:
914
915 if (s->regs[SONIC_RCR] & SONIC_RCR_LPKT) {
916 if (s->regs[SONIC_RRP] == s->regs[SONIC_RWP]) {
917 /* Stop packet reception */
918 s->last_rba_is_full = true;
919 } else {
920 /* Read next resource */
921 dp8393x_do_read_rra(s);
922 }
923 }
924
925 return pkt_size;
926 }
927
928 static void dp8393x_reset(DeviceState *dev)
929 {
930 dp8393xState *s = DP8393X(dev);
931 timer_del(s->watchdog);
932
933 memset(s->regs, 0, sizeof(s->regs));
934 s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux/mips */
935 s->regs[SONIC_CR] = SONIC_CR_RST | SONIC_CR_STP | SONIC_CR_RXDIS;
936 s->regs[SONIC_DCR] &= ~(SONIC_DCR_EXBUS | SONIC_DCR_LBR);
937 s->regs[SONIC_RCR] &= ~(SONIC_RCR_LB0 | SONIC_RCR_LB1 | SONIC_RCR_BRD | SONIC_RCR_RNT);
938 s->regs[SONIC_TCR] |= SONIC_TCR_NCRS | SONIC_TCR_PTX;
939 s->regs[SONIC_TCR] &= ~SONIC_TCR_BCM;
940 s->regs[SONIC_IMR] = 0;
941 s->regs[SONIC_ISR] = 0;
942 s->regs[SONIC_DCR2] = 0;
943 s->regs[SONIC_EOBC] = 0x02F8;
944 s->regs[SONIC_RSC] = 0;
945 s->regs[SONIC_CE] = 0;
946 s->regs[SONIC_RSC] = 0;
947
948 /* Network cable is connected */
949 s->regs[SONIC_RCR] |= SONIC_RCR_CRS;
950
951 dp8393x_update_irq(s);
952 }
953
954 static NetClientInfo net_dp83932_info = {
955 .type = NET_CLIENT_DRIVER_NIC,
956 .size = sizeof(NICState),
957 .can_receive = dp8393x_can_receive,
958 .receive = dp8393x_receive,
959 };
960
961 static void dp8393x_instance_init(Object *obj)
962 {
963 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
964 dp8393xState *s = DP8393X(obj);
965
966 sysbus_init_mmio(sbd, &s->mmio);
967 sysbus_init_mmio(sbd, &s->prom);
968 sysbus_init_irq(sbd, &s->irq);
969 }
970
971 static void dp8393x_realize(DeviceState *dev, Error **errp)
972 {
973 dp8393xState *s = DP8393X(dev);
974 int i, checksum;
975 uint8_t *prom;
976 Error *local_err = NULL;
977
978 address_space_init(&s->as, s->dma_mr, "dp8393x");
979 memory_region_init_io(&s->mmio, OBJECT(dev), &dp8393x_ops, s,
980 "dp8393x-regs", 0x40 << s->it_shift);
981
982 s->nic = qemu_new_nic(&net_dp83932_info, &s->conf,
983 object_get_typename(OBJECT(dev)), dev->id, s);
984 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
985
986 s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s);
987
988 memory_region_init_rom(&s->prom, OBJECT(dev), "dp8393x-prom",
989 SONIC_PROM_SIZE, &local_err);
990 if (local_err) {
991 error_propagate(errp, local_err);
992 return;
993 }
994 prom = memory_region_get_ram_ptr(&s->prom);
995 checksum = 0;
996 for (i = 0; i < 6; i++) {
997 prom[i] = s->conf.macaddr.a[i];
998 checksum += prom[i];
999 if (checksum > 0xff) {
1000 checksum = (checksum + 1) & 0xff;
1001 }
1002 }
1003 prom[7] = 0xff - checksum;
1004 }
1005
1006 static const VMStateDescription vmstate_dp8393x = {
1007 .name = "dp8393x",
1008 .version_id = 0,
1009 .minimum_version_id = 0,
1010 .fields = (VMStateField []) {
1011 VMSTATE_BUFFER_UNSAFE(cam, dp8393xState, 0, 16 * 6),
1012 VMSTATE_UINT16_ARRAY(regs, dp8393xState, 0x40),
1013 VMSTATE_END_OF_LIST()
1014 }
1015 };
1016
1017 static Property dp8393x_properties[] = {
1018 DEFINE_NIC_PROPERTIES(dp8393xState, conf),
1019 DEFINE_PROP_LINK("dma_mr", dp8393xState, dma_mr,
1020 TYPE_MEMORY_REGION, MemoryRegion *),
1021 DEFINE_PROP_UINT8("it_shift", dp8393xState, it_shift, 0),
1022 DEFINE_PROP_BOOL("big_endian", dp8393xState, big_endian, false),
1023 DEFINE_PROP_END_OF_LIST(),
1024 };
1025
1026 static void dp8393x_class_init(ObjectClass *klass, void *data)
1027 {
1028 DeviceClass *dc = DEVICE_CLASS(klass);
1029
1030 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
1031 dc->realize = dp8393x_realize;
1032 dc->reset = dp8393x_reset;
1033 dc->vmsd = &vmstate_dp8393x;
1034 device_class_set_props(dc, dp8393x_properties);
1035 }
1036
1037 static const TypeInfo dp8393x_info = {
1038 .name = TYPE_DP8393X,
1039 .parent = TYPE_SYS_BUS_DEVICE,
1040 .instance_size = sizeof(dp8393xState),
1041 .instance_init = dp8393x_instance_init,
1042 .class_init = dp8393x_class_init,
1043 };
1044
1045 static void dp8393x_register_types(void)
1046 {
1047 type_register_static(&dp8393x_info);
1048 }
1049
1050 type_init(dp8393x_register_types)