fsl_etsec: Fix Tx BD ring wrapping handling
[qemu.git] / hw / net / fsl_etsec / rings.c
1 /*
2 * QEMU Freescale eTSEC Emulator
3 *
4 * Copyright (c) 2011-2013 AdaCore
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "qemu/osdep.h"
25 #include "net/checksum.h"
26 #include "qemu/log.h"
27 #include "etsec.h"
28 #include "registers.h"
29
30 /* #define ETSEC_RING_DEBUG */
31 /* #define HEX_DUMP */
32 /* #define DEBUG_BD */
33
34 #ifdef ETSEC_RING_DEBUG
35 static const int debug_etsec = 1;
36 #else
37 static const int debug_etsec;
38 #endif
39
40 #define RING_DEBUG(fmt, ...) do { \
41 if (debug_etsec) { \
42 qemu_log(fmt , ## __VA_ARGS__); \
43 } \
44 } while (0)
45
46 #ifdef DEBUG_BD
47
48 static void print_tx_bd_flags(uint16_t flags)
49 {
50 qemu_log(" Ready: %d\n", !!(flags & BD_TX_READY));
51 qemu_log(" PAD/CRC: %d\n", !!(flags & BD_TX_PADCRC));
52 qemu_log(" Wrap: %d\n", !!(flags & BD_WRAP));
53 qemu_log(" Interrupt: %d\n", !!(flags & BD_INTERRUPT));
54 qemu_log(" Last in frame: %d\n", !!(flags & BD_LAST));
55 qemu_log(" Tx CRC: %d\n", !!(flags & BD_TX_TC));
56 qemu_log(" User-defined preamble / defer: %d\n",
57 !!(flags & BD_TX_PREDEF));
58 qemu_log(" Huge frame enable / Late collision: %d\n",
59 !!(flags & BD_TX_HFELC));
60 qemu_log(" Control frame / Retransmission Limit: %d\n",
61 !!(flags & BD_TX_CFRL));
62 qemu_log(" Retry count: %d\n",
63 (flags >> BD_TX_RC_OFFSET) & BD_TX_RC_MASK);
64 qemu_log(" Underrun / TCP/IP off-load enable: %d\n",
65 !!(flags & BD_TX_TOEUN));
66 qemu_log(" Truncation: %d\n", !!(flags & BD_TX_TR));
67 }
68
69 static void print_rx_bd_flags(uint16_t flags)
70 {
71 qemu_log(" Empty: %d\n", !!(flags & BD_RX_EMPTY));
72 qemu_log(" Receive software ownership: %d\n", !!(flags & BD_RX_RO1));
73 qemu_log(" Wrap: %d\n", !!(flags & BD_WRAP));
74 qemu_log(" Interrupt: %d\n", !!(flags & BD_INTERRUPT));
75 qemu_log(" Last in frame: %d\n", !!(flags & BD_LAST));
76 qemu_log(" First in frame: %d\n", !!(flags & BD_RX_FIRST));
77 qemu_log(" Miss: %d\n", !!(flags & BD_RX_MISS));
78 qemu_log(" Broadcast: %d\n", !!(flags & BD_RX_BROADCAST));
79 qemu_log(" Multicast: %d\n", !!(flags & BD_RX_MULTICAST));
80 qemu_log(" Rx frame length violation: %d\n", !!(flags & BD_RX_LG));
81 qemu_log(" Rx non-octet aligned frame: %d\n", !!(flags & BD_RX_NO));
82 qemu_log(" Short frame: %d\n", !!(flags & BD_RX_SH));
83 qemu_log(" Rx CRC Error: %d\n", !!(flags & BD_RX_CR));
84 qemu_log(" Overrun: %d\n", !!(flags & BD_RX_OV));
85 qemu_log(" Truncation: %d\n", !!(flags & BD_RX_TR));
86 }
87
88
89 static void print_bd(eTSEC_rxtx_bd bd, int mode, uint32_t index)
90 {
91 qemu_log("eTSEC %s Data Buffer Descriptor (%u)\n",
92 mode == eTSEC_TRANSMIT ? "Transmit" : "Receive",
93 index);
94 qemu_log(" Flags : 0x%04x\n", bd.flags);
95 if (mode == eTSEC_TRANSMIT) {
96 print_tx_bd_flags(bd.flags);
97 } else {
98 print_rx_bd_flags(bd.flags);
99 }
100 qemu_log(" Length : 0x%04x\n", bd.length);
101 qemu_log(" Pointer : 0x%08x\n", bd.bufptr);
102 }
103
104 #endif /* DEBUG_BD */
105
106 static void read_buffer_descriptor(eTSEC *etsec,
107 hwaddr addr,
108 eTSEC_rxtx_bd *bd)
109 {
110 assert(bd != NULL);
111
112 RING_DEBUG("READ Buffer Descriptor @ 0x" TARGET_FMT_plx"\n", addr);
113 cpu_physical_memory_read(addr,
114 bd,
115 sizeof(eTSEC_rxtx_bd));
116
117 if (etsec->regs[DMACTRL].value & DMACTRL_LE) {
118 bd->flags = lduw_le_p(&bd->flags);
119 bd->length = lduw_le_p(&bd->length);
120 bd->bufptr = ldl_le_p(&bd->bufptr);
121 } else {
122 bd->flags = lduw_be_p(&bd->flags);
123 bd->length = lduw_be_p(&bd->length);
124 bd->bufptr = ldl_be_p(&bd->bufptr);
125 }
126 }
127
128 static void write_buffer_descriptor(eTSEC *etsec,
129 hwaddr addr,
130 eTSEC_rxtx_bd *bd)
131 {
132 assert(bd != NULL);
133
134 if (etsec->regs[DMACTRL].value & DMACTRL_LE) {
135 stw_le_p(&bd->flags, bd->flags);
136 stw_le_p(&bd->length, bd->length);
137 stl_le_p(&bd->bufptr, bd->bufptr);
138 } else {
139 stw_be_p(&bd->flags, bd->flags);
140 stw_be_p(&bd->length, bd->length);
141 stl_be_p(&bd->bufptr, bd->bufptr);
142 }
143
144 RING_DEBUG("Write Buffer Descriptor @ 0x" TARGET_FMT_plx"\n", addr);
145 cpu_physical_memory_write(addr,
146 bd,
147 sizeof(eTSEC_rxtx_bd));
148 }
149
150 static void ievent_set(eTSEC *etsec,
151 uint32_t flags)
152 {
153 etsec->regs[IEVENT].value |= flags;
154
155 if ((flags & IEVENT_TXB && etsec->regs[IMASK].value & IMASK_TXBEN)
156 || (flags & IEVENT_TXF && etsec->regs[IMASK].value & IMASK_TXFEN)) {
157 qemu_irq_raise(etsec->tx_irq);
158 RING_DEBUG("%s Raise Tx IRQ\n", __func__);
159 }
160
161 if ((flags & IEVENT_RXB && etsec->regs[IMASK].value & IMASK_RXBEN)
162 || (flags & IEVENT_RXF && etsec->regs[IMASK].value & IMASK_RXFEN)) {
163 qemu_irq_raise(etsec->rx_irq);
164 RING_DEBUG("%s Raise Rx IRQ\n", __func__);
165 }
166 }
167
168 static void tx_padding_and_crc(eTSEC *etsec, uint32_t min_frame_len)
169 {
170 int add = min_frame_len - etsec->tx_buffer_len;
171
172 /* Padding */
173 if (add > 0) {
174 RING_DEBUG("pad:%u\n", add);
175 etsec->tx_buffer = g_realloc(etsec->tx_buffer,
176 etsec->tx_buffer_len + add);
177
178 memset(etsec->tx_buffer + etsec->tx_buffer_len, 0x0, add);
179 etsec->tx_buffer_len += add;
180 }
181
182 /* Never add CRC in QEMU */
183 }
184
185 static void process_tx_fcb(eTSEC *etsec)
186 {
187 uint8_t flags = (uint8_t)(*etsec->tx_buffer);
188 /* L3 header offset from start of frame */
189 uint8_t l3_header_offset = (uint8_t)*(etsec->tx_buffer + 3);
190 /* L4 header offset from start of L3 header */
191 uint8_t l4_header_offset = (uint8_t)*(etsec->tx_buffer + 2);
192 /* L3 header */
193 uint8_t *l3_header = etsec->tx_buffer + 8 + l3_header_offset;
194 /* L4 header */
195 uint8_t *l4_header = l3_header + l4_header_offset;
196
197 /* if packet is IP4 and IP checksum is requested */
198 if (flags & FCB_TX_IP && flags & FCB_TX_CIP) {
199 /* do IP4 checksum (TODO This function does TCP/UDP checksum
200 * but not sure if it also does IP4 checksum.) */
201 net_checksum_calculate(etsec->tx_buffer + 8,
202 etsec->tx_buffer_len - 8);
203 }
204 /* TODO Check the correct usage of the PHCS field of the FCB in case the NPH
205 * flag is on */
206
207 /* if packet is IP4 and TCP or UDP */
208 if (flags & FCB_TX_IP && flags & FCB_TX_TUP) {
209 /* if UDP */
210 if (flags & FCB_TX_UDP) {
211 /* if checksum is requested */
212 if (flags & FCB_TX_CTU) {
213 /* do UDP checksum */
214
215 net_checksum_calculate(etsec->tx_buffer + 8,
216 etsec->tx_buffer_len - 8);
217 } else {
218 /* set checksum field to 0 */
219 l4_header[6] = 0;
220 l4_header[7] = 0;
221 }
222 } else if (flags & FCB_TX_CTU) { /* if TCP and checksum is requested */
223 /* do TCP checksum */
224 net_checksum_calculate(etsec->tx_buffer + 8,
225 etsec->tx_buffer_len - 8);
226 }
227 }
228 }
229
230 static void process_tx_bd(eTSEC *etsec,
231 eTSEC_rxtx_bd *bd)
232 {
233 uint8_t *tmp_buff = NULL;
234 hwaddr tbdbth = (hwaddr)(etsec->regs[TBDBPH].value & 0xF) << 32;
235
236 if (bd->length == 0) {
237 /* ERROR */
238 return;
239 }
240
241 if (etsec->tx_buffer_len == 0) {
242 /* It's the first BD */
243 etsec->first_bd = *bd;
244 }
245
246 /* TODO: if TxBD[TOE/UN] skip the Tx Frame Control Block*/
247
248 /* Load this Data Buffer */
249 etsec->tx_buffer = g_realloc(etsec->tx_buffer,
250 etsec->tx_buffer_len + bd->length);
251 tmp_buff = etsec->tx_buffer + etsec->tx_buffer_len;
252 cpu_physical_memory_read(bd->bufptr + tbdbth, tmp_buff, bd->length);
253
254 /* Update buffer length */
255 etsec->tx_buffer_len += bd->length;
256
257
258 if (etsec->tx_buffer_len != 0 && (bd->flags & BD_LAST)) {
259 if (etsec->regs[MACCFG1].value & MACCFG1_TX_EN) {
260 /* MAC Transmit enabled */
261
262 /* Process offload Tx FCB */
263 if (etsec->first_bd.flags & BD_TX_TOEUN) {
264 process_tx_fcb(etsec);
265 }
266
267 if (etsec->first_bd.flags & BD_TX_PADCRC
268 || etsec->regs[MACCFG2].value & MACCFG2_PADCRC) {
269
270 /* Padding and CRC (Padding implies CRC) */
271 tx_padding_and_crc(etsec, 64);
272
273 } else if (etsec->first_bd.flags & BD_TX_TC
274 || etsec->regs[MACCFG2].value & MACCFG2_CRC_EN) {
275
276 /* Only CRC */
277 /* Never add CRC in QEMU */
278 }
279
280 #if defined(HEX_DUMP)
281 qemu_log("eTSEC Send packet size:%d\n", etsec->tx_buffer_len);
282 qemu_hexdump(etsec->tx_buffer, stderr, "", etsec->tx_buffer_len);
283 #endif /* ETSEC_RING_DEBUG */
284
285 if (etsec->first_bd.flags & BD_TX_TOEUN) {
286 qemu_send_packet(qemu_get_queue(etsec->nic),
287 etsec->tx_buffer + 8,
288 etsec->tx_buffer_len - 8);
289 } else {
290 qemu_send_packet(qemu_get_queue(etsec->nic),
291 etsec->tx_buffer,
292 etsec->tx_buffer_len);
293 }
294
295 }
296
297 etsec->tx_buffer_len = 0;
298
299 if (bd->flags & BD_INTERRUPT) {
300 ievent_set(etsec, IEVENT_TXF);
301 }
302 } else {
303 if (bd->flags & BD_INTERRUPT) {
304 ievent_set(etsec, IEVENT_TXB);
305 }
306 }
307
308 /* Update DB flags */
309
310 /* Clear Ready */
311 bd->flags &= ~BD_TX_READY;
312
313 /* Clear Defer */
314 bd->flags &= ~BD_TX_PREDEF;
315
316 /* Clear Late Collision */
317 bd->flags &= ~BD_TX_HFELC;
318
319 /* Clear Retransmission Limit */
320 bd->flags &= ~BD_TX_CFRL;
321
322 /* Clear Retry Count */
323 bd->flags &= ~(BD_TX_RC_MASK << BD_TX_RC_OFFSET);
324
325 /* Clear Underrun */
326 bd->flags &= ~BD_TX_TOEUN;
327
328 /* Clear Truncation */
329 bd->flags &= ~BD_TX_TR;
330 }
331
332 void etsec_walk_tx_ring(eTSEC *etsec, int ring_nbr)
333 {
334 hwaddr ring_base = 0;
335 hwaddr bd_addr = 0;
336 eTSEC_rxtx_bd bd;
337 uint16_t bd_flags;
338
339 if (!(etsec->regs[MACCFG1].value & MACCFG1_TX_EN)) {
340 RING_DEBUG("%s: MAC Transmit not enabled\n", __func__);
341 return;
342 }
343
344 ring_base = (hwaddr)(etsec->regs[TBASEH].value & 0xF) << 32;
345 ring_base += etsec->regs[TBASE0 + ring_nbr].value & ~0x7;
346 bd_addr = etsec->regs[TBPTR0 + ring_nbr].value & ~0x7;
347
348 do {
349 read_buffer_descriptor(etsec, bd_addr, &bd);
350
351 #ifdef DEBUG_BD
352 print_bd(bd,
353 eTSEC_TRANSMIT,
354 (bd_addr - ring_base) / sizeof(eTSEC_rxtx_bd));
355
356 #endif /* DEBUG_BD */
357
358 /* Save flags before BD update */
359 bd_flags = bd.flags;
360
361 if (!(bd_flags & BD_TX_READY)) {
362 break;
363 }
364
365 process_tx_bd(etsec, &bd);
366 /* Write back BD after update */
367 write_buffer_descriptor(etsec, bd_addr, &bd);
368
369 /* Wrap or next BD */
370 if (bd_flags & BD_WRAP) {
371 bd_addr = ring_base;
372 } else {
373 bd_addr += sizeof(eTSEC_rxtx_bd);
374 }
375 } while (TRUE);
376
377 /* Save the Buffer Descriptor Pointers to last bd that was not
378 * succesfully closed */
379 etsec->regs[TBPTR0 + ring_nbr].value = bd_addr;
380
381 /* Set transmit halt THLTx */
382 etsec->regs[TSTAT].value |= 1 << (31 - ring_nbr);
383 }
384
385 static void fill_rx_bd(eTSEC *etsec,
386 eTSEC_rxtx_bd *bd,
387 const uint8_t **buf,
388 size_t *size)
389 {
390 uint16_t to_write;
391 hwaddr bufptr = bd->bufptr +
392 ((hwaddr)(etsec->regs[TBDBPH].value & 0xF) << 32);
393 uint8_t padd[etsec->rx_padding];
394 uint8_t rem;
395
396 RING_DEBUG("eTSEC fill Rx buffer @ 0x%016" HWADDR_PRIx
397 " size:%zu(padding + crc:%u) + fcb:%u\n",
398 bufptr, *size, etsec->rx_padding, etsec->rx_fcb_size);
399
400 bd->length = 0;
401
402 /* This operation will only write FCB */
403 if (etsec->rx_fcb_size != 0) {
404
405 cpu_physical_memory_write(bufptr, etsec->rx_fcb, etsec->rx_fcb_size);
406
407 bufptr += etsec->rx_fcb_size;
408 bd->length += etsec->rx_fcb_size;
409 etsec->rx_fcb_size = 0;
410
411 }
412
413 /* We remove padding from the computation of to_write because it is not
414 * allocated in the buffer.
415 */
416 to_write = MIN(*size - etsec->rx_padding,
417 etsec->regs[MRBLR].value - etsec->rx_fcb_size);
418
419 /* This operation can only write packet data and no padding */
420 if (to_write > 0) {
421 cpu_physical_memory_write(bufptr, *buf, to_write);
422
423 *buf += to_write;
424 bufptr += to_write;
425 *size -= to_write;
426
427 bd->flags &= ~BD_RX_EMPTY;
428 bd->length += to_write;
429 }
430
431 if (*size == etsec->rx_padding) {
432 /* The remaining bytes are only for padding which is not actually
433 * allocated in the data buffer.
434 */
435
436 rem = MIN(etsec->regs[MRBLR].value - bd->length, etsec->rx_padding);
437
438 if (rem > 0) {
439 memset(padd, 0x0, sizeof(padd));
440 etsec->rx_padding -= rem;
441 *size -= rem;
442 bd->length += rem;
443 cpu_physical_memory_write(bufptr, padd, rem);
444 }
445 }
446 }
447
448 static void rx_init_frame(eTSEC *etsec, const uint8_t *buf, size_t size)
449 {
450 uint32_t fcb_size = 0;
451 uint8_t prsdep = (etsec->regs[RCTRL].value >> RCTRL_PRSDEP_OFFSET)
452 & RCTRL_PRSDEP_MASK;
453
454 if (prsdep != 0) {
455 /* Prepend FCB (FCB size + RCTRL[PAL]) */
456 fcb_size = 8 + ((etsec->regs[RCTRL].value >> 16) & 0x1F);
457
458 etsec->rx_fcb_size = fcb_size;
459
460 /* TODO: fill_FCB(etsec); */
461 memset(etsec->rx_fcb, 0x0, sizeof(etsec->rx_fcb));
462
463 } else {
464 etsec->rx_fcb_size = 0;
465 }
466
467 g_free(etsec->rx_buffer);
468
469 /* Do not copy the frame for now */
470 etsec->rx_buffer = (uint8_t *)buf;
471 etsec->rx_buffer_len = size;
472
473 /* CRC padding (We don't have to compute the CRC) */
474 etsec->rx_padding = 4;
475
476 /*
477 * Ensure that payload length + CRC length is at least 802.3
478 * minimum MTU size bytes long (64)
479 */
480 if (etsec->rx_buffer_len < 60) {
481 etsec->rx_padding += 60 - etsec->rx_buffer_len;
482 }
483
484 etsec->rx_first_in_frame = 1;
485 etsec->rx_remaining_data = etsec->rx_buffer_len;
486 RING_DEBUG("%s: rx_buffer_len:%u rx_padding+crc:%u\n", __func__,
487 etsec->rx_buffer_len, etsec->rx_padding);
488 }
489
490 ssize_t etsec_rx_ring_write(eTSEC *etsec, const uint8_t *buf, size_t size)
491 {
492 int ring_nbr = 0; /* Always use ring0 (no filer) */
493
494 if (etsec->rx_buffer_len != 0) {
495 RING_DEBUG("%s: We can't receive now,"
496 " a buffer is already in the pipe\n", __func__);
497 return 0;
498 }
499
500 if (etsec->regs[RSTAT].value & 1 << (23 - ring_nbr)) {
501 RING_DEBUG("%s: The ring is halted\n", __func__);
502 return -1;
503 }
504
505 if (etsec->regs[DMACTRL].value & DMACTRL_GRS) {
506 RING_DEBUG("%s: Graceful receive stop\n", __func__);
507 return -1;
508 }
509
510 if (!(etsec->regs[MACCFG1].value & MACCFG1_RX_EN)) {
511 RING_DEBUG("%s: MAC Receive not enabled\n", __func__);
512 return -1;
513 }
514
515 if ((etsec->regs[RCTRL].value & RCTRL_RSF) && (size < 60)) {
516 /* CRC is not in the packet yet, so short frame is below 60 bytes */
517 RING_DEBUG("%s: Drop short frame\n", __func__);
518 return -1;
519 }
520
521 rx_init_frame(etsec, buf, size);
522
523 etsec_walk_rx_ring(etsec, ring_nbr);
524
525 return size;
526 }
527
528 void etsec_walk_rx_ring(eTSEC *etsec, int ring_nbr)
529 {
530 hwaddr ring_base = 0;
531 hwaddr bd_addr = 0;
532 hwaddr start_bd_addr = 0;
533 eTSEC_rxtx_bd bd;
534 uint16_t bd_flags;
535 size_t remaining_data;
536 const uint8_t *buf;
537 uint8_t *tmp_buf;
538 size_t size;
539
540 if (etsec->rx_buffer_len == 0) {
541 /* No frame to send */
542 RING_DEBUG("No frame to send\n");
543 return;
544 }
545
546 remaining_data = etsec->rx_remaining_data + etsec->rx_padding;
547 buf = etsec->rx_buffer
548 + (etsec->rx_buffer_len - etsec->rx_remaining_data);
549 size = etsec->rx_buffer_len + etsec->rx_padding;
550
551 ring_base = (hwaddr)(etsec->regs[RBASEH].value & 0xF) << 32;
552 ring_base += etsec->regs[RBASE0 + ring_nbr].value & ~0x7;
553 start_bd_addr = bd_addr = etsec->regs[RBPTR0 + ring_nbr].value & ~0x7;
554
555 do {
556 read_buffer_descriptor(etsec, bd_addr, &bd);
557
558 #ifdef DEBUG_BD
559 print_bd(bd,
560 eTSEC_RECEIVE,
561 (bd_addr - ring_base) / sizeof(eTSEC_rxtx_bd));
562
563 #endif /* DEBUG_BD */
564
565 /* Save flags before BD update */
566 bd_flags = bd.flags;
567
568 if (bd_flags & BD_RX_EMPTY) {
569 fill_rx_bd(etsec, &bd, &buf, &remaining_data);
570
571 if (etsec->rx_first_in_frame) {
572 bd.flags |= BD_RX_FIRST;
573 etsec->rx_first_in_frame = 0;
574 etsec->rx_first_bd = bd;
575 }
576
577 /* Last in frame */
578 if (remaining_data == 0) {
579
580 /* Clear flags */
581
582 bd.flags &= ~0x7ff;
583
584 bd.flags |= BD_LAST;
585
586 /* NOTE: non-octet aligned frame is impossible in qemu */
587
588 if (size >= etsec->regs[MAXFRM].value) {
589 /* frame length violation */
590 qemu_log("%s frame length violation: size:%zu MAXFRM:%d\n",
591 __func__, size, etsec->regs[MAXFRM].value);
592
593 bd.flags |= BD_RX_LG;
594 }
595
596 if (size < 64) {
597 /* Short frame */
598 bd.flags |= BD_RX_SH;
599 }
600
601 /* TODO: Broadcast and Multicast */
602
603 if (bd.flags & BD_INTERRUPT) {
604 /* Set RXFx */
605 etsec->regs[RSTAT].value |= 1 << (7 - ring_nbr);
606
607 /* Set IEVENT */
608 ievent_set(etsec, IEVENT_RXF);
609 }
610
611 } else {
612 if (bd.flags & BD_INTERRUPT) {
613 /* Set IEVENT */
614 ievent_set(etsec, IEVENT_RXB);
615 }
616 }
617
618 /* Write back BD after update */
619 write_buffer_descriptor(etsec, bd_addr, &bd);
620 }
621
622 /* Wrap or next BD */
623 if (bd_flags & BD_WRAP) {
624 bd_addr = ring_base;
625 } else {
626 bd_addr += sizeof(eTSEC_rxtx_bd);
627 }
628 } while (remaining_data != 0
629 && (bd_flags & BD_RX_EMPTY)
630 && bd_addr != start_bd_addr);
631
632 /* Reset ring ptr */
633 etsec->regs[RBPTR0 + ring_nbr].value = bd_addr;
634
635 /* The frame is too large to fit in the Rx ring */
636 if (remaining_data > 0) {
637
638 /* Set RSTAT[QHLTx] */
639 etsec->regs[RSTAT].value |= 1 << (23 - ring_nbr);
640
641 /* Save remaining data to send the end of the frame when the ring will
642 * be restarted
643 */
644 etsec->rx_remaining_data = remaining_data;
645
646 /* Copy the frame */
647 tmp_buf = g_malloc(size);
648 memcpy(tmp_buf, etsec->rx_buffer, size);
649 etsec->rx_buffer = tmp_buf;
650
651 RING_DEBUG("no empty RxBD available any more\n");
652 } else {
653 etsec->rx_buffer_len = 0;
654 etsec->rx_buffer = NULL;
655 if (etsec->need_flush) {
656 qemu_flush_queued_packets(qemu_get_queue(etsec->nic));
657 }
658 }
659
660 RING_DEBUG("eTSEC End of ring_write: remaining_data:%zu\n", remaining_data);
661 }