sm501: Add missing arbitration control register
[qemu.git] / hw / net / mcf_fec.c
1 /*
2 * ColdFire Fast Ethernet Controller emulation.
3 *
4 * Copyright (c) 2007 CodeSourcery.
5 *
6 * This code is licensed under the GPL
7 */
8 #include "qemu/osdep.h"
9 #include "hw/hw.h"
10 #include "net/net.h"
11 #include "hw/m68k/mcf.h"
12 #include "hw/m68k/mcf_fec.h"
13 #include "hw/net/mii.h"
14 #include "hw/sysbus.h"
15 /* For crc32 */
16 #include <zlib.h>
17 #include "exec/address-spaces.h"
18
19 //#define DEBUG_FEC 1
20
21 #ifdef DEBUG_FEC
22 #define DPRINTF(fmt, ...) \
23 do { printf("mcf_fec: " fmt , ## __VA_ARGS__); } while (0)
24 #else
25 #define DPRINTF(fmt, ...) do {} while(0)
26 #endif
27
28 #define FEC_MAX_DESC 1024
29 #define FEC_MAX_FRAME_SIZE 2032
30 #define FEC_MIB_SIZE 64
31
32 typedef struct {
33 SysBusDevice parent_obj;
34
35 MemoryRegion iomem;
36 qemu_irq irq[FEC_NUM_IRQ];
37 NICState *nic;
38 NICConf conf;
39 uint32_t irq_state;
40 uint32_t eir;
41 uint32_t eimr;
42 int rx_enabled;
43 uint32_t rx_descriptor;
44 uint32_t tx_descriptor;
45 uint32_t ecr;
46 uint32_t mmfr;
47 uint32_t mscr;
48 uint32_t rcr;
49 uint32_t tcr;
50 uint32_t tfwr;
51 uint32_t rfsr;
52 uint32_t erdsr;
53 uint32_t etdsr;
54 uint32_t emrbr;
55 uint32_t mib[FEC_MIB_SIZE];
56 } mcf_fec_state;
57
58 #define FEC_INT_HB 0x80000000
59 #define FEC_INT_BABR 0x40000000
60 #define FEC_INT_BABT 0x20000000
61 #define FEC_INT_GRA 0x10000000
62 #define FEC_INT_TXF 0x08000000
63 #define FEC_INT_TXB 0x04000000
64 #define FEC_INT_RXF 0x02000000
65 #define FEC_INT_RXB 0x01000000
66 #define FEC_INT_MII 0x00800000
67 #define FEC_INT_EB 0x00400000
68 #define FEC_INT_LC 0x00200000
69 #define FEC_INT_RL 0x00100000
70 #define FEC_INT_UN 0x00080000
71
72 #define FEC_EN 2
73 #define FEC_RESET 1
74
75 /* Map interrupt flags onto IRQ lines. */
76 static const uint32_t mcf_fec_irq_map[FEC_NUM_IRQ] = {
77 FEC_INT_TXF,
78 FEC_INT_TXB,
79 FEC_INT_UN,
80 FEC_INT_RL,
81 FEC_INT_RXF,
82 FEC_INT_RXB,
83 FEC_INT_MII,
84 FEC_INT_LC,
85 FEC_INT_HB,
86 FEC_INT_GRA,
87 FEC_INT_EB,
88 FEC_INT_BABT,
89 FEC_INT_BABR
90 };
91
92 /* Buffer Descriptor. */
93 typedef struct {
94 uint16_t flags;
95 uint16_t length;
96 uint32_t data;
97 } mcf_fec_bd;
98
99 #define FEC_BD_R 0x8000
100 #define FEC_BD_E 0x8000
101 #define FEC_BD_O1 0x4000
102 #define FEC_BD_W 0x2000
103 #define FEC_BD_O2 0x1000
104 #define FEC_BD_L 0x0800
105 #define FEC_BD_TC 0x0400
106 #define FEC_BD_ABC 0x0200
107 #define FEC_BD_M 0x0100
108 #define FEC_BD_BC 0x0080
109 #define FEC_BD_MC 0x0040
110 #define FEC_BD_LG 0x0020
111 #define FEC_BD_NO 0x0010
112 #define FEC_BD_CR 0x0004
113 #define FEC_BD_OV 0x0002
114 #define FEC_BD_TR 0x0001
115
116 #define MIB_RMON_T_DROP 0
117 #define MIB_RMON_T_PACKETS 1
118 #define MIB_RMON_T_BC_PKT 2
119 #define MIB_RMON_T_MC_PKT 3
120 #define MIB_RMON_T_CRC_ALIGN 4
121 #define MIB_RMON_T_UNDERSIZE 5
122 #define MIB_RMON_T_OVERSIZE 6
123 #define MIB_RMON_T_FRAG 7
124 #define MIB_RMON_T_JAB 8
125 #define MIB_RMON_T_COL 9
126 #define MIB_RMON_T_P64 10
127 #define MIB_RMON_T_P65TO127 11
128 #define MIB_RMON_T_P128TO255 12
129 #define MIB_RMON_T_P256TO511 13
130 #define MIB_RMON_T_P512TO1023 14
131 #define MIB_RMON_T_P1024TO2047 15
132 #define MIB_RMON_T_P_GTE2048 16
133 #define MIB_RMON_T_OCTETS 17
134 #define MIB_IEEE_T_DROP 18
135 #define MIB_IEEE_T_FRAME_OK 19
136 #define MIB_IEEE_T_1COL 20
137 #define MIB_IEEE_T_MCOL 21
138 #define MIB_IEEE_T_DEF 22
139 #define MIB_IEEE_T_LCOL 23
140 #define MIB_IEEE_T_EXCOL 24
141 #define MIB_IEEE_T_MACERR 25
142 #define MIB_IEEE_T_CSERR 26
143 #define MIB_IEEE_T_SQE 27
144 #define MIB_IEEE_T_FDXFC 28
145 #define MIB_IEEE_T_OCTETS_OK 29
146
147 #define MIB_RMON_R_DROP 32
148 #define MIB_RMON_R_PACKETS 33
149 #define MIB_RMON_R_BC_PKT 34
150 #define MIB_RMON_R_MC_PKT 35
151 #define MIB_RMON_R_CRC_ALIGN 36
152 #define MIB_RMON_R_UNDERSIZE 37
153 #define MIB_RMON_R_OVERSIZE 38
154 #define MIB_RMON_R_FRAG 39
155 #define MIB_RMON_R_JAB 40
156 #define MIB_RMON_R_RESVD_0 41
157 #define MIB_RMON_R_P64 42
158 #define MIB_RMON_R_P65TO127 43
159 #define MIB_RMON_R_P128TO255 44
160 #define MIB_RMON_R_P256TO511 45
161 #define MIB_RMON_R_P512TO1023 46
162 #define MIB_RMON_R_P1024TO2047 47
163 #define MIB_RMON_R_P_GTE2048 48
164 #define MIB_RMON_R_OCTETS 49
165 #define MIB_IEEE_R_DROP 50
166 #define MIB_IEEE_R_FRAME_OK 51
167 #define MIB_IEEE_R_CRC 52
168 #define MIB_IEEE_R_ALIGN 53
169 #define MIB_IEEE_R_MACERR 54
170 #define MIB_IEEE_R_FDXFC 55
171 #define MIB_IEEE_R_OCTETS_OK 56
172
173 static void mcf_fec_read_bd(mcf_fec_bd *bd, uint32_t addr)
174 {
175 cpu_physical_memory_read(addr, bd, sizeof(*bd));
176 be16_to_cpus(&bd->flags);
177 be16_to_cpus(&bd->length);
178 be32_to_cpus(&bd->data);
179 }
180
181 static void mcf_fec_write_bd(mcf_fec_bd *bd, uint32_t addr)
182 {
183 mcf_fec_bd tmp;
184 tmp.flags = cpu_to_be16(bd->flags);
185 tmp.length = cpu_to_be16(bd->length);
186 tmp.data = cpu_to_be32(bd->data);
187 cpu_physical_memory_write(addr, &tmp, sizeof(tmp));
188 }
189
190 static void mcf_fec_update(mcf_fec_state *s)
191 {
192 uint32_t active;
193 uint32_t changed;
194 uint32_t mask;
195 int i;
196
197 active = s->eir & s->eimr;
198 changed = active ^s->irq_state;
199 for (i = 0; i < FEC_NUM_IRQ; i++) {
200 mask = mcf_fec_irq_map[i];
201 if (changed & mask) {
202 DPRINTF("IRQ %d = %d\n", i, (active & mask) != 0);
203 qemu_set_irq(s->irq[i], (active & mask) != 0);
204 }
205 }
206 s->irq_state = active;
207 }
208
209 static void mcf_fec_tx_stats(mcf_fec_state *s, int size)
210 {
211 s->mib[MIB_RMON_T_PACKETS]++;
212 s->mib[MIB_RMON_T_OCTETS] += size;
213 if (size < 64) {
214 s->mib[MIB_RMON_T_FRAG]++;
215 } else if (size == 64) {
216 s->mib[MIB_RMON_T_P64]++;
217 } else if (size < 128) {
218 s->mib[MIB_RMON_T_P65TO127]++;
219 } else if (size < 256) {
220 s->mib[MIB_RMON_T_P128TO255]++;
221 } else if (size < 512) {
222 s->mib[MIB_RMON_T_P256TO511]++;
223 } else if (size < 1024) {
224 s->mib[MIB_RMON_T_P512TO1023]++;
225 } else if (size < 2048) {
226 s->mib[MIB_RMON_T_P1024TO2047]++;
227 } else {
228 s->mib[MIB_RMON_T_P_GTE2048]++;
229 }
230 s->mib[MIB_IEEE_T_FRAME_OK]++;
231 s->mib[MIB_IEEE_T_OCTETS_OK] += size;
232 }
233
234 static void mcf_fec_do_tx(mcf_fec_state *s)
235 {
236 uint32_t addr;
237 mcf_fec_bd bd;
238 int frame_size;
239 int len, descnt = 0;
240 uint8_t frame[FEC_MAX_FRAME_SIZE];
241 uint8_t *ptr;
242
243 DPRINTF("do_tx\n");
244 ptr = frame;
245 frame_size = 0;
246 addr = s->tx_descriptor;
247 while (descnt++ < FEC_MAX_DESC) {
248 mcf_fec_read_bd(&bd, addr);
249 DPRINTF("tx_bd %x flags %04x len %d data %08x\n",
250 addr, bd.flags, bd.length, bd.data);
251 if ((bd.flags & FEC_BD_R) == 0) {
252 /* Run out of descriptors to transmit. */
253 break;
254 }
255 len = bd.length;
256 if (frame_size + len > FEC_MAX_FRAME_SIZE) {
257 len = FEC_MAX_FRAME_SIZE - frame_size;
258 s->eir |= FEC_INT_BABT;
259 }
260 cpu_physical_memory_read(bd.data, ptr, len);
261 ptr += len;
262 frame_size += len;
263 if (bd.flags & FEC_BD_L) {
264 /* Last buffer in frame. */
265 DPRINTF("Sending packet\n");
266 qemu_send_packet(qemu_get_queue(s->nic), frame, frame_size);
267 mcf_fec_tx_stats(s, frame_size);
268 ptr = frame;
269 frame_size = 0;
270 s->eir |= FEC_INT_TXF;
271 }
272 s->eir |= FEC_INT_TXB;
273 bd.flags &= ~FEC_BD_R;
274 /* Write back the modified descriptor. */
275 mcf_fec_write_bd(&bd, addr);
276 /* Advance to the next descriptor. */
277 if ((bd.flags & FEC_BD_W) != 0) {
278 addr = s->etdsr;
279 } else {
280 addr += 8;
281 }
282 }
283 s->tx_descriptor = addr;
284 }
285
286 static void mcf_fec_enable_rx(mcf_fec_state *s)
287 {
288 NetClientState *nc = qemu_get_queue(s->nic);
289 mcf_fec_bd bd;
290
291 mcf_fec_read_bd(&bd, s->rx_descriptor);
292 s->rx_enabled = ((bd.flags & FEC_BD_E) != 0);
293 if (s->rx_enabled) {
294 qemu_flush_queued_packets(nc);
295 }
296 }
297
298 static void mcf_fec_reset(DeviceState *dev)
299 {
300 mcf_fec_state *s = MCF_FEC_NET(dev);
301
302 s->eir = 0;
303 s->eimr = 0;
304 s->rx_enabled = 0;
305 s->ecr = 0;
306 s->mscr = 0;
307 s->rcr = 0x05ee0001;
308 s->tcr = 0;
309 s->tfwr = 0;
310 s->rfsr = 0x500;
311 }
312
313 #define MMFR_WRITE_OP (1 << 28)
314 #define MMFR_READ_OP (2 << 28)
315 #define MMFR_PHYADDR(v) (((v) >> 23) & 0x1f)
316 #define MMFR_REGNUM(v) (((v) >> 18) & 0x1f)
317
318 static uint64_t mcf_fec_read_mdio(mcf_fec_state *s)
319 {
320 uint64_t v;
321
322 if (s->mmfr & MMFR_WRITE_OP)
323 return s->mmfr;
324 if (MMFR_PHYADDR(s->mmfr) != 1)
325 return s->mmfr |= 0xffff;
326
327 switch (MMFR_REGNUM(s->mmfr)) {
328 case MII_BMCR:
329 v = MII_BMCR_SPEED | MII_BMCR_AUTOEN | MII_BMCR_FD;
330 break;
331 case MII_BMSR:
332 v = MII_BMSR_100TX_FD | MII_BMSR_100TX_HD | MII_BMSR_10T_FD |
333 MII_BMSR_10T_HD | MII_BMSR_MFPS | MII_BMSR_AN_COMP |
334 MII_BMSR_AUTONEG | MII_BMSR_LINK_ST;
335 break;
336 case MII_PHYID1:
337 v = DP83848_PHYID1;
338 break;
339 case MII_PHYID2:
340 v = DP83848_PHYID2;
341 break;
342 case MII_ANAR:
343 v = MII_ANAR_TXFD | MII_ANAR_TX | MII_ANAR_10FD |
344 MII_ANAR_10 | MII_ANAR_CSMACD;
345 break;
346 case MII_ANLPAR:
347 v = MII_ANLPAR_ACK | MII_ANLPAR_TXFD | MII_ANLPAR_TX |
348 MII_ANLPAR_10FD | MII_ANLPAR_10 | MII_ANLPAR_CSMACD;
349 break;
350 default:
351 v = 0xffff;
352 break;
353 }
354 s->mmfr = (s->mmfr & ~0xffff) | v;
355 return s->mmfr;
356 }
357
358 static uint64_t mcf_fec_read(void *opaque, hwaddr addr,
359 unsigned size)
360 {
361 mcf_fec_state *s = (mcf_fec_state *)opaque;
362 switch (addr & 0x3ff) {
363 case 0x004: return s->eir;
364 case 0x008: return s->eimr;
365 case 0x010: return s->rx_enabled ? (1 << 24) : 0; /* RDAR */
366 case 0x014: return 0; /* TDAR */
367 case 0x024: return s->ecr;
368 case 0x040: return mcf_fec_read_mdio(s);
369 case 0x044: return s->mscr;
370 case 0x064: return 0; /* MIBC */
371 case 0x084: return s->rcr;
372 case 0x0c4: return s->tcr;
373 case 0x0e4: /* PALR */
374 return (s->conf.macaddr.a[0] << 24) | (s->conf.macaddr.a[1] << 16)
375 | (s->conf.macaddr.a[2] << 8) | s->conf.macaddr.a[3];
376 break;
377 case 0x0e8: /* PAUR */
378 return (s->conf.macaddr.a[4] << 24) | (s->conf.macaddr.a[5] << 16) | 0x8808;
379 case 0x0ec: return 0x10000; /* OPD */
380 case 0x118: return 0;
381 case 0x11c: return 0;
382 case 0x120: return 0;
383 case 0x124: return 0;
384 case 0x144: return s->tfwr;
385 case 0x14c: return 0x600;
386 case 0x150: return s->rfsr;
387 case 0x180: return s->erdsr;
388 case 0x184: return s->etdsr;
389 case 0x188: return s->emrbr;
390 case 0x200 ... 0x2e0: return s->mib[(addr & 0x1ff) / 4];
391 default:
392 hw_error("mcf_fec_read: Bad address 0x%x\n", (int)addr);
393 return 0;
394 }
395 }
396
397 static void mcf_fec_write(void *opaque, hwaddr addr,
398 uint64_t value, unsigned size)
399 {
400 mcf_fec_state *s = (mcf_fec_state *)opaque;
401 switch (addr & 0x3ff) {
402 case 0x004:
403 s->eir &= ~value;
404 break;
405 case 0x008:
406 s->eimr = value;
407 break;
408 case 0x010: /* RDAR */
409 if ((s->ecr & FEC_EN) && !s->rx_enabled) {
410 DPRINTF("RX enable\n");
411 mcf_fec_enable_rx(s);
412 }
413 break;
414 case 0x014: /* TDAR */
415 if (s->ecr & FEC_EN) {
416 mcf_fec_do_tx(s);
417 }
418 break;
419 case 0x024:
420 s->ecr = value;
421 if (value & FEC_RESET) {
422 DPRINTF("Reset\n");
423 mcf_fec_reset(opaque);
424 }
425 if ((s->ecr & FEC_EN) == 0) {
426 s->rx_enabled = 0;
427 }
428 break;
429 case 0x040:
430 s->mmfr = value;
431 s->eir |= FEC_INT_MII;
432 break;
433 case 0x044:
434 s->mscr = value & 0xfe;
435 break;
436 case 0x064:
437 /* TODO: Implement MIB. */
438 break;
439 case 0x084:
440 s->rcr = value & 0x07ff003f;
441 /* TODO: Implement LOOP mode. */
442 break;
443 case 0x0c4: /* TCR */
444 /* We transmit immediately, so raise GRA immediately. */
445 s->tcr = value;
446 if (value & 1)
447 s->eir |= FEC_INT_GRA;
448 break;
449 case 0x0e4: /* PALR */
450 s->conf.macaddr.a[0] = value >> 24;
451 s->conf.macaddr.a[1] = value >> 16;
452 s->conf.macaddr.a[2] = value >> 8;
453 s->conf.macaddr.a[3] = value;
454 break;
455 case 0x0e8: /* PAUR */
456 s->conf.macaddr.a[4] = value >> 24;
457 s->conf.macaddr.a[5] = value >> 16;
458 break;
459 case 0x0ec:
460 /* OPD */
461 break;
462 case 0x118:
463 case 0x11c:
464 case 0x120:
465 case 0x124:
466 /* TODO: implement MAC hash filtering. */
467 break;
468 case 0x144:
469 s->tfwr = value & 3;
470 break;
471 case 0x14c:
472 /* FRBR writes ignored. */
473 break;
474 case 0x150:
475 s->rfsr = (value & 0x3fc) | 0x400;
476 break;
477 case 0x180:
478 s->erdsr = value & ~3;
479 s->rx_descriptor = s->erdsr;
480 break;
481 case 0x184:
482 s->etdsr = value & ~3;
483 s->tx_descriptor = s->etdsr;
484 break;
485 case 0x188:
486 s->emrbr = value > 0 ? value & 0x7F0 : 0x7F0;
487 break;
488 case 0x200 ... 0x2e0:
489 s->mib[(addr & 0x1ff) / 4] = value;
490 break;
491 default:
492 hw_error("mcf_fec_write Bad address 0x%x\n", (int)addr);
493 }
494 mcf_fec_update(s);
495 }
496
497 static void mcf_fec_rx_stats(mcf_fec_state *s, int size)
498 {
499 s->mib[MIB_RMON_R_PACKETS]++;
500 s->mib[MIB_RMON_R_OCTETS] += size;
501 if (size < 64) {
502 s->mib[MIB_RMON_R_FRAG]++;
503 } else if (size == 64) {
504 s->mib[MIB_RMON_R_P64]++;
505 } else if (size < 128) {
506 s->mib[MIB_RMON_R_P65TO127]++;
507 } else if (size < 256) {
508 s->mib[MIB_RMON_R_P128TO255]++;
509 } else if (size < 512) {
510 s->mib[MIB_RMON_R_P256TO511]++;
511 } else if (size < 1024) {
512 s->mib[MIB_RMON_R_P512TO1023]++;
513 } else if (size < 2048) {
514 s->mib[MIB_RMON_R_P1024TO2047]++;
515 } else {
516 s->mib[MIB_RMON_R_P_GTE2048]++;
517 }
518 s->mib[MIB_IEEE_R_FRAME_OK]++;
519 s->mib[MIB_IEEE_R_OCTETS_OK] += size;
520 }
521
522 static int mcf_fec_have_receive_space(mcf_fec_state *s, size_t want)
523 {
524 mcf_fec_bd bd;
525 uint32_t addr;
526
527 /* Walk descriptor list to determine if we have enough buffer */
528 addr = s->rx_descriptor;
529 while (want > 0) {
530 mcf_fec_read_bd(&bd, addr);
531 if ((bd.flags & FEC_BD_E) == 0) {
532 return 0;
533 }
534 if (want < s->emrbr) {
535 return 1;
536 }
537 want -= s->emrbr;
538 /* Advance to the next descriptor. */
539 if ((bd.flags & FEC_BD_W) != 0) {
540 addr = s->erdsr;
541 } else {
542 addr += 8;
543 }
544 }
545 return 0;
546 }
547
548 static ssize_t mcf_fec_receive(NetClientState *nc, const uint8_t *buf, size_t size)
549 {
550 mcf_fec_state *s = qemu_get_nic_opaque(nc);
551 mcf_fec_bd bd;
552 uint32_t flags = 0;
553 uint32_t addr;
554 uint32_t crc;
555 uint32_t buf_addr;
556 uint8_t *crc_ptr;
557 unsigned int buf_len;
558 size_t retsize;
559
560 DPRINTF("do_rx len %d\n", size);
561 if (!s->rx_enabled) {
562 return -1;
563 }
564 /* 4 bytes for the CRC. */
565 size += 4;
566 crc = cpu_to_be32(crc32(~0, buf, size));
567 crc_ptr = (uint8_t *)&crc;
568 /* Huge frames are truncted. */
569 if (size > FEC_MAX_FRAME_SIZE) {
570 size = FEC_MAX_FRAME_SIZE;
571 flags |= FEC_BD_TR | FEC_BD_LG;
572 }
573 /* Frames larger than the user limit just set error flags. */
574 if (size > (s->rcr >> 16)) {
575 flags |= FEC_BD_LG;
576 }
577 /* Check if we have enough space in current descriptors */
578 if (!mcf_fec_have_receive_space(s, size)) {
579 return 0;
580 }
581 addr = s->rx_descriptor;
582 retsize = size;
583 while (size > 0) {
584 mcf_fec_read_bd(&bd, addr);
585 buf_len = (size <= s->emrbr) ? size: s->emrbr;
586 bd.length = buf_len;
587 size -= buf_len;
588 DPRINTF("rx_bd %x length %d\n", addr, bd.length);
589 /* The last 4 bytes are the CRC. */
590 if (size < 4)
591 buf_len += size - 4;
592 buf_addr = bd.data;
593 cpu_physical_memory_write(buf_addr, buf, buf_len);
594 buf += buf_len;
595 if (size < 4) {
596 cpu_physical_memory_write(buf_addr + buf_len, crc_ptr, 4 - size);
597 crc_ptr += 4 - size;
598 }
599 bd.flags &= ~FEC_BD_E;
600 if (size == 0) {
601 /* Last buffer in frame. */
602 bd.flags |= flags | FEC_BD_L;
603 DPRINTF("rx frame flags %04x\n", bd.flags);
604 s->eir |= FEC_INT_RXF;
605 } else {
606 s->eir |= FEC_INT_RXB;
607 }
608 mcf_fec_write_bd(&bd, addr);
609 /* Advance to the next descriptor. */
610 if ((bd.flags & FEC_BD_W) != 0) {
611 addr = s->erdsr;
612 } else {
613 addr += 8;
614 }
615 }
616 s->rx_descriptor = addr;
617 mcf_fec_rx_stats(s, retsize);
618 mcf_fec_enable_rx(s);
619 mcf_fec_update(s);
620 return retsize;
621 }
622
623 static const MemoryRegionOps mcf_fec_ops = {
624 .read = mcf_fec_read,
625 .write = mcf_fec_write,
626 .endianness = DEVICE_NATIVE_ENDIAN,
627 };
628
629 static NetClientInfo net_mcf_fec_info = {
630 .type = NET_CLIENT_DRIVER_NIC,
631 .size = sizeof(NICState),
632 .receive = mcf_fec_receive,
633 };
634
635 static void mcf_fec_realize(DeviceState *dev, Error **errp)
636 {
637 mcf_fec_state *s = MCF_FEC_NET(dev);
638
639 s->nic = qemu_new_nic(&net_mcf_fec_info, &s->conf,
640 object_get_typename(OBJECT(dev)), dev->id, s);
641 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
642 }
643
644 static void mcf_fec_instance_init(Object *obj)
645 {
646 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
647 mcf_fec_state *s = MCF_FEC_NET(obj);
648 int i;
649
650 memory_region_init_io(&s->iomem, obj, &mcf_fec_ops, s, "fec", 0x400);
651 sysbus_init_mmio(sbd, &s->iomem);
652 for (i = 0; i < FEC_NUM_IRQ; i++) {
653 sysbus_init_irq(sbd, &s->irq[i]);
654 }
655 }
656
657 static Property mcf_fec_properties[] = {
658 DEFINE_NIC_PROPERTIES(mcf_fec_state, conf),
659 DEFINE_PROP_END_OF_LIST(),
660 };
661
662 static void mcf_fec_class_init(ObjectClass *oc, void *data)
663 {
664 DeviceClass *dc = DEVICE_CLASS(oc);
665
666 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
667 dc->realize = mcf_fec_realize;
668 dc->desc = "MCF Fast Ethernet Controller network device";
669 dc->reset = mcf_fec_reset;
670 dc->props = mcf_fec_properties;
671 }
672
673 static const TypeInfo mcf_fec_info = {
674 .name = TYPE_MCF_FEC_NET,
675 .parent = TYPE_SYS_BUS_DEVICE,
676 .instance_size = sizeof(mcf_fec_state),
677 .instance_init = mcf_fec_instance_init,
678 .class_init = mcf_fec_class_init,
679 };
680
681 static void mcf_fec_register_types(void)
682 {
683 type_register_static(&mcf_fec_info);
684 }
685
686 type_init(mcf_fec_register_types)