sm501: Add missing arbitration control register
[qemu.git] / hw / net / ne2000.c
1 /*
2 * QEMU NE2000 emulation
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "qemu/osdep.h"
25 #include "hw/hw.h"
26 #include "hw/pci/pci.h"
27 #include "net/net.h"
28 #include "ne2000.h"
29 #include "hw/loader.h"
30 #include "sysemu/sysemu.h"
31
32 /* debug NE2000 card */
33 //#define DEBUG_NE2000
34
35 #define MAX_ETH_FRAME_SIZE 1514
36
37 #define E8390_CMD 0x00 /* The command register (for all pages) */
38 /* Page 0 register offsets. */
39 #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */
40 #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */
41 #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */
42 #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */
43 #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */
44 #define EN0_TSR 0x04 /* Transmit status reg RD */
45 #define EN0_TPSR 0x04 /* Transmit starting page WR */
46 #define EN0_NCR 0x05 /* Number of collision reg RD */
47 #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */
48 #define EN0_FIFO 0x06 /* FIFO RD */
49 #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */
50 #define EN0_ISR 0x07 /* Interrupt status reg RD WR */
51 #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */
52 #define EN0_RSARLO 0x08 /* Remote start address reg 0 */
53 #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */
54 #define EN0_RSARHI 0x09 /* Remote start address reg 1 */
55 #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */
56 #define EN0_RTL8029ID0 0x0a /* Realtek ID byte #1 RD */
57 #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */
58 #define EN0_RTL8029ID1 0x0b /* Realtek ID byte #2 RD */
59 #define EN0_RSR 0x0c /* rx status reg RD */
60 #define EN0_RXCR 0x0c /* RX configuration reg WR */
61 #define EN0_TXCR 0x0d /* TX configuration reg WR */
62 #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */
63 #define EN0_DCFG 0x0e /* Data configuration reg WR */
64 #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */
65 #define EN0_IMR 0x0f /* Interrupt mask reg WR */
66 #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */
67
68 #define EN1_PHYS 0x11
69 #define EN1_CURPAG 0x17
70 #define EN1_MULT 0x18
71
72 #define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */
73 #define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */
74
75 #define EN3_CONFIG0 0x33
76 #define EN3_CONFIG1 0x34
77 #define EN3_CONFIG2 0x35
78 #define EN3_CONFIG3 0x36
79
80 /* Register accessed at EN_CMD, the 8390 base addr. */
81 #define E8390_STOP 0x01 /* Stop and reset the chip */
82 #define E8390_START 0x02 /* Start the chip, clear reset */
83 #define E8390_TRANS 0x04 /* Transmit a frame */
84 #define E8390_RREAD 0x08 /* Remote read */
85 #define E8390_RWRITE 0x10 /* Remote write */
86 #define E8390_NODMA 0x20 /* Remote DMA */
87 #define E8390_PAGE0 0x00 /* Select page chip registers */
88 #define E8390_PAGE1 0x40 /* using the two high-order bits */
89 #define E8390_PAGE2 0x80 /* Page 3 is invalid. */
90
91 /* Bits in EN0_ISR - Interrupt status register */
92 #define ENISR_RX 0x01 /* Receiver, no error */
93 #define ENISR_TX 0x02 /* Transmitter, no error */
94 #define ENISR_RX_ERR 0x04 /* Receiver, with error */
95 #define ENISR_TX_ERR 0x08 /* Transmitter, with error */
96 #define ENISR_OVER 0x10 /* Receiver overwrote the ring */
97 #define ENISR_COUNTERS 0x20 /* Counters need emptying */
98 #define ENISR_RDC 0x40 /* remote dma complete */
99 #define ENISR_RESET 0x80 /* Reset completed */
100 #define ENISR_ALL 0x3f /* Interrupts we will enable */
101
102 /* Bits in received packet status byte and EN0_RSR*/
103 #define ENRSR_RXOK 0x01 /* Received a good packet */
104 #define ENRSR_CRC 0x02 /* CRC error */
105 #define ENRSR_FAE 0x04 /* frame alignment error */
106 #define ENRSR_FO 0x08 /* FIFO overrun */
107 #define ENRSR_MPA 0x10 /* missed pkt */
108 #define ENRSR_PHY 0x20 /* physical/multicast address */
109 #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */
110 #define ENRSR_DEF 0x80 /* deferring */
111
112 /* Transmitted packet status, EN0_TSR. */
113 #define ENTSR_PTX 0x01 /* Packet transmitted without error */
114 #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */
115 #define ENTSR_COL 0x04 /* The transmit collided at least once. */
116 #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */
117 #define ENTSR_CRS 0x10 /* The carrier sense was lost. */
118 #define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */
119 #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */
120 #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */
121
122 typedef struct PCINE2000State {
123 PCIDevice dev;
124 NE2000State ne2000;
125 } PCINE2000State;
126
127 void ne2000_reset(NE2000State *s)
128 {
129 int i;
130
131 s->isr = ENISR_RESET;
132 memcpy(s->mem, &s->c.macaddr, 6);
133 s->mem[14] = 0x57;
134 s->mem[15] = 0x57;
135
136 /* duplicate prom data */
137 for(i = 15;i >= 0; i--) {
138 s->mem[2 * i] = s->mem[i];
139 s->mem[2 * i + 1] = s->mem[i];
140 }
141 }
142
143 static void ne2000_update_irq(NE2000State *s)
144 {
145 int isr;
146 isr = (s->isr & s->imr) & 0x7f;
147 #if defined(DEBUG_NE2000)
148 printf("NE2000: Set IRQ to %d (%02x %02x)\n",
149 isr ? 1 : 0, s->isr, s->imr);
150 #endif
151 qemu_set_irq(s->irq, (isr != 0));
152 }
153
154 static int ne2000_buffer_full(NE2000State *s)
155 {
156 int avail, index, boundary;
157
158 if (s->stop <= s->start) {
159 return 1;
160 }
161
162 index = s->curpag << 8;
163 boundary = s->boundary << 8;
164 if (index < boundary)
165 avail = boundary - index;
166 else
167 avail = (s->stop - s->start) - (index - boundary);
168 if (avail < (MAX_ETH_FRAME_SIZE + 4))
169 return 1;
170 return 0;
171 }
172
173 #define MIN_BUF_SIZE 60
174
175 ssize_t ne2000_receive(NetClientState *nc, const uint8_t *buf, size_t size_)
176 {
177 NE2000State *s = qemu_get_nic_opaque(nc);
178 int size = size_;
179 uint8_t *p;
180 unsigned int total_len, next, avail, len, index, mcast_idx;
181 uint8_t buf1[60];
182 static const uint8_t broadcast_macaddr[6] =
183 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
184
185 #if defined(DEBUG_NE2000)
186 printf("NE2000: received len=%d\n", size);
187 #endif
188
189 if (s->cmd & E8390_STOP || ne2000_buffer_full(s))
190 return -1;
191
192 /* XXX: check this */
193 if (s->rxcr & 0x10) {
194 /* promiscuous: receive all */
195 } else {
196 if (!memcmp(buf, broadcast_macaddr, 6)) {
197 /* broadcast address */
198 if (!(s->rxcr & 0x04))
199 return size;
200 } else if (buf[0] & 0x01) {
201 /* multicast */
202 if (!(s->rxcr & 0x08))
203 return size;
204 mcast_idx = compute_mcast_idx(buf);
205 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
206 return size;
207 } else if (s->mem[0] == buf[0] &&
208 s->mem[2] == buf[1] &&
209 s->mem[4] == buf[2] &&
210 s->mem[6] == buf[3] &&
211 s->mem[8] == buf[4] &&
212 s->mem[10] == buf[5]) {
213 /* match */
214 } else {
215 return size;
216 }
217 }
218
219
220 /* if too small buffer, then expand it */
221 if (size < MIN_BUF_SIZE) {
222 memcpy(buf1, buf, size);
223 memset(buf1 + size, 0, MIN_BUF_SIZE - size);
224 buf = buf1;
225 size = MIN_BUF_SIZE;
226 }
227
228 index = s->curpag << 8;
229 if (index >= NE2000_PMEM_END) {
230 index = s->start;
231 }
232 /* 4 bytes for header */
233 total_len = size + 4;
234 /* address for next packet (4 bytes for CRC) */
235 next = index + ((total_len + 4 + 255) & ~0xff);
236 if (next >= s->stop)
237 next -= (s->stop - s->start);
238 /* prepare packet header */
239 p = s->mem + index;
240 s->rsr = ENRSR_RXOK; /* receive status */
241 /* XXX: check this */
242 if (buf[0] & 0x01)
243 s->rsr |= ENRSR_PHY;
244 p[0] = s->rsr;
245 p[1] = next >> 8;
246 p[2] = total_len;
247 p[3] = total_len >> 8;
248 index += 4;
249
250 /* write packet data */
251 while (size > 0) {
252 if (index <= s->stop)
253 avail = s->stop - index;
254 else
255 break;
256 len = size;
257 if (len > avail)
258 len = avail;
259 memcpy(s->mem + index, buf, len);
260 buf += len;
261 index += len;
262 if (index == s->stop)
263 index = s->start;
264 size -= len;
265 }
266 s->curpag = next >> 8;
267
268 /* now we can signal we have received something */
269 s->isr |= ENISR_RX;
270 ne2000_update_irq(s);
271
272 return size_;
273 }
274
275 static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
276 {
277 NE2000State *s = opaque;
278 int offset, page, index;
279
280 addr &= 0xf;
281 #ifdef DEBUG_NE2000
282 printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
283 #endif
284 if (addr == E8390_CMD) {
285 /* control register */
286 s->cmd = val;
287 if (!(val & E8390_STOP)) { /* START bit makes no sense on RTL8029... */
288 s->isr &= ~ENISR_RESET;
289 /* test specific case: zero length transfer */
290 if ((val & (E8390_RREAD | E8390_RWRITE)) &&
291 s->rcnt == 0) {
292 s->isr |= ENISR_RDC;
293 ne2000_update_irq(s);
294 }
295 if (val & E8390_TRANS) {
296 index = (s->tpsr << 8);
297 /* XXX: next 2 lines are a hack to make netware 3.11 work */
298 if (index >= NE2000_PMEM_END)
299 index -= NE2000_PMEM_SIZE;
300 /* fail safe: check range on the transmitted length */
301 if (index + s->tcnt <= NE2000_PMEM_END) {
302 qemu_send_packet(qemu_get_queue(s->nic), s->mem + index,
303 s->tcnt);
304 }
305 /* signal end of transfer */
306 s->tsr = ENTSR_PTX;
307 s->isr |= ENISR_TX;
308 s->cmd &= ~E8390_TRANS;
309 ne2000_update_irq(s);
310 }
311 }
312 } else {
313 page = s->cmd >> 6;
314 offset = addr | (page << 4);
315 switch(offset) {
316 case EN0_STARTPG:
317 if (val << 8 <= NE2000_PMEM_END) {
318 s->start = val << 8;
319 }
320 break;
321 case EN0_STOPPG:
322 if (val << 8 <= NE2000_PMEM_END) {
323 s->stop = val << 8;
324 }
325 break;
326 case EN0_BOUNDARY:
327 if (val << 8 < NE2000_PMEM_END) {
328 s->boundary = val;
329 }
330 break;
331 case EN0_IMR:
332 s->imr = val;
333 ne2000_update_irq(s);
334 break;
335 case EN0_TPSR:
336 s->tpsr = val;
337 break;
338 case EN0_TCNTLO:
339 s->tcnt = (s->tcnt & 0xff00) | val;
340 break;
341 case EN0_TCNTHI:
342 s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
343 break;
344 case EN0_RSARLO:
345 s->rsar = (s->rsar & 0xff00) | val;
346 break;
347 case EN0_RSARHI:
348 s->rsar = (s->rsar & 0x00ff) | (val << 8);
349 break;
350 case EN0_RCNTLO:
351 s->rcnt = (s->rcnt & 0xff00) | val;
352 break;
353 case EN0_RCNTHI:
354 s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
355 break;
356 case EN0_RXCR:
357 s->rxcr = val;
358 break;
359 case EN0_DCFG:
360 s->dcfg = val;
361 break;
362 case EN0_ISR:
363 s->isr &= ~(val & 0x7f);
364 ne2000_update_irq(s);
365 break;
366 case EN1_PHYS ... EN1_PHYS + 5:
367 s->phys[offset - EN1_PHYS] = val;
368 break;
369 case EN1_CURPAG:
370 if (val << 8 < NE2000_PMEM_END) {
371 s->curpag = val;
372 }
373 break;
374 case EN1_MULT ... EN1_MULT + 7:
375 s->mult[offset - EN1_MULT] = val;
376 break;
377 }
378 }
379 }
380
381 static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
382 {
383 NE2000State *s = opaque;
384 int offset, page, ret;
385
386 addr &= 0xf;
387 if (addr == E8390_CMD) {
388 ret = s->cmd;
389 } else {
390 page = s->cmd >> 6;
391 offset = addr | (page << 4);
392 switch(offset) {
393 case EN0_TSR:
394 ret = s->tsr;
395 break;
396 case EN0_BOUNDARY:
397 ret = s->boundary;
398 break;
399 case EN0_ISR:
400 ret = s->isr;
401 break;
402 case EN0_RSARLO:
403 ret = s->rsar & 0x00ff;
404 break;
405 case EN0_RSARHI:
406 ret = s->rsar >> 8;
407 break;
408 case EN1_PHYS ... EN1_PHYS + 5:
409 ret = s->phys[offset - EN1_PHYS];
410 break;
411 case EN1_CURPAG:
412 ret = s->curpag;
413 break;
414 case EN1_MULT ... EN1_MULT + 7:
415 ret = s->mult[offset - EN1_MULT];
416 break;
417 case EN0_RSR:
418 ret = s->rsr;
419 break;
420 case EN2_STARTPG:
421 ret = s->start >> 8;
422 break;
423 case EN2_STOPPG:
424 ret = s->stop >> 8;
425 break;
426 case EN0_RTL8029ID0:
427 ret = 0x50;
428 break;
429 case EN0_RTL8029ID1:
430 ret = 0x43;
431 break;
432 case EN3_CONFIG0:
433 ret = 0; /* 10baseT media */
434 break;
435 case EN3_CONFIG2:
436 ret = 0x40; /* 10baseT active */
437 break;
438 case EN3_CONFIG3:
439 ret = 0x40; /* Full duplex */
440 break;
441 default:
442 ret = 0x00;
443 break;
444 }
445 }
446 #ifdef DEBUG_NE2000
447 printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
448 #endif
449 return ret;
450 }
451
452 static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr,
453 uint32_t val)
454 {
455 if (addr < 32 ||
456 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
457 s->mem[addr] = val;
458 }
459 }
460
461 static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr,
462 uint32_t val)
463 {
464 addr &= ~1; /* XXX: check exact behaviour if not even */
465 if (addr < 32 ||
466 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
467 *(uint16_t *)(s->mem + addr) = cpu_to_le16(val);
468 }
469 }
470
471 static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr,
472 uint32_t val)
473 {
474 addr &= ~1; /* XXX: check exact behaviour if not even */
475 if (addr < 32
476 || (addr >= NE2000_PMEM_START
477 && addr + sizeof(uint32_t) <= NE2000_MEM_SIZE)) {
478 stl_le_p(s->mem + addr, val);
479 }
480 }
481
482 static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr)
483 {
484 if (addr < 32 ||
485 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
486 return s->mem[addr];
487 } else {
488 return 0xff;
489 }
490 }
491
492 static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr)
493 {
494 addr &= ~1; /* XXX: check exact behaviour if not even */
495 if (addr < 32 ||
496 (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
497 return le16_to_cpu(*(uint16_t *)(s->mem + addr));
498 } else {
499 return 0xffff;
500 }
501 }
502
503 static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr)
504 {
505 addr &= ~1; /* XXX: check exact behaviour if not even */
506 if (addr < 32
507 || (addr >= NE2000_PMEM_START
508 && addr + sizeof(uint32_t) <= NE2000_MEM_SIZE)) {
509 return ldl_le_p(s->mem + addr);
510 } else {
511 return 0xffffffff;
512 }
513 }
514
515 static inline void ne2000_dma_update(NE2000State *s, int len)
516 {
517 s->rsar += len;
518 /* wrap */
519 /* XXX: check what to do if rsar > stop */
520 if (s->rsar == s->stop)
521 s->rsar = s->start;
522
523 if (s->rcnt <= len) {
524 s->rcnt = 0;
525 /* signal end of transfer */
526 s->isr |= ENISR_RDC;
527 ne2000_update_irq(s);
528 } else {
529 s->rcnt -= len;
530 }
531 }
532
533 static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
534 {
535 NE2000State *s = opaque;
536
537 #ifdef DEBUG_NE2000
538 printf("NE2000: asic write val=0x%04x\n", val);
539 #endif
540 if (s->rcnt == 0)
541 return;
542 if (s->dcfg & 0x01) {
543 /* 16 bit access */
544 ne2000_mem_writew(s, s->rsar, val);
545 ne2000_dma_update(s, 2);
546 } else {
547 /* 8 bit access */
548 ne2000_mem_writeb(s, s->rsar, val);
549 ne2000_dma_update(s, 1);
550 }
551 }
552
553 static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
554 {
555 NE2000State *s = opaque;
556 int ret;
557
558 if (s->dcfg & 0x01) {
559 /* 16 bit access */
560 ret = ne2000_mem_readw(s, s->rsar);
561 ne2000_dma_update(s, 2);
562 } else {
563 /* 8 bit access */
564 ret = ne2000_mem_readb(s, s->rsar);
565 ne2000_dma_update(s, 1);
566 }
567 #ifdef DEBUG_NE2000
568 printf("NE2000: asic read val=0x%04x\n", ret);
569 #endif
570 return ret;
571 }
572
573 static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
574 {
575 NE2000State *s = opaque;
576
577 #ifdef DEBUG_NE2000
578 printf("NE2000: asic writel val=0x%04x\n", val);
579 #endif
580 if (s->rcnt == 0)
581 return;
582 /* 32 bit access */
583 ne2000_mem_writel(s, s->rsar, val);
584 ne2000_dma_update(s, 4);
585 }
586
587 static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr)
588 {
589 NE2000State *s = opaque;
590 int ret;
591
592 /* 32 bit access */
593 ret = ne2000_mem_readl(s, s->rsar);
594 ne2000_dma_update(s, 4);
595 #ifdef DEBUG_NE2000
596 printf("NE2000: asic readl val=0x%04x\n", ret);
597 #endif
598 return ret;
599 }
600
601 static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val)
602 {
603 /* nothing to do (end of reset pulse) */
604 }
605
606 static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
607 {
608 NE2000State *s = opaque;
609 ne2000_reset(s);
610 return 0;
611 }
612
613 static int ne2000_post_load(void* opaque, int version_id)
614 {
615 NE2000State* s = opaque;
616
617 if (version_id < 2) {
618 s->rxcr = 0x0c;
619 }
620 return 0;
621 }
622
623 const VMStateDescription vmstate_ne2000 = {
624 .name = "ne2000",
625 .version_id = 2,
626 .minimum_version_id = 0,
627 .post_load = ne2000_post_load,
628 .fields = (VMStateField[]) {
629 VMSTATE_UINT8_V(rxcr, NE2000State, 2),
630 VMSTATE_UINT8(cmd, NE2000State),
631 VMSTATE_UINT32(start, NE2000State),
632 VMSTATE_UINT32(stop, NE2000State),
633 VMSTATE_UINT8(boundary, NE2000State),
634 VMSTATE_UINT8(tsr, NE2000State),
635 VMSTATE_UINT8(tpsr, NE2000State),
636 VMSTATE_UINT16(tcnt, NE2000State),
637 VMSTATE_UINT16(rcnt, NE2000State),
638 VMSTATE_UINT32(rsar, NE2000State),
639 VMSTATE_UINT8(rsr, NE2000State),
640 VMSTATE_UINT8(isr, NE2000State),
641 VMSTATE_UINT8(dcfg, NE2000State),
642 VMSTATE_UINT8(imr, NE2000State),
643 VMSTATE_BUFFER(phys, NE2000State),
644 VMSTATE_UINT8(curpag, NE2000State),
645 VMSTATE_BUFFER(mult, NE2000State),
646 VMSTATE_UNUSED(4), /* was irq */
647 VMSTATE_BUFFER(mem, NE2000State),
648 VMSTATE_END_OF_LIST()
649 }
650 };
651
652 static const VMStateDescription vmstate_pci_ne2000 = {
653 .name = "ne2000",
654 .version_id = 3,
655 .minimum_version_id = 3,
656 .fields = (VMStateField[]) {
657 VMSTATE_PCI_DEVICE(dev, PCINE2000State),
658 VMSTATE_STRUCT(ne2000, PCINE2000State, 0, vmstate_ne2000, NE2000State),
659 VMSTATE_END_OF_LIST()
660 }
661 };
662
663 static uint64_t ne2000_read(void *opaque, hwaddr addr,
664 unsigned size)
665 {
666 NE2000State *s = opaque;
667
668 if (addr < 0x10 && size == 1) {
669 return ne2000_ioport_read(s, addr);
670 } else if (addr == 0x10) {
671 if (size <= 2) {
672 return ne2000_asic_ioport_read(s, addr);
673 } else {
674 return ne2000_asic_ioport_readl(s, addr);
675 }
676 } else if (addr == 0x1f && size == 1) {
677 return ne2000_reset_ioport_read(s, addr);
678 }
679 return ((uint64_t)1 << (size * 8)) - 1;
680 }
681
682 static void ne2000_write(void *opaque, hwaddr addr,
683 uint64_t data, unsigned size)
684 {
685 NE2000State *s = opaque;
686
687 if (addr < 0x10 && size == 1) {
688 ne2000_ioport_write(s, addr, data);
689 } else if (addr == 0x10) {
690 if (size <= 2) {
691 ne2000_asic_ioport_write(s, addr, data);
692 } else {
693 ne2000_asic_ioport_writel(s, addr, data);
694 }
695 } else if (addr == 0x1f && size == 1) {
696 ne2000_reset_ioport_write(s, addr, data);
697 }
698 }
699
700 static const MemoryRegionOps ne2000_ops = {
701 .read = ne2000_read,
702 .write = ne2000_write,
703 .endianness = DEVICE_LITTLE_ENDIAN,
704 };
705
706 /***********************************************************/
707 /* PCI NE2000 definitions */
708
709 void ne2000_setup_io(NE2000State *s, DeviceState *dev, unsigned size)
710 {
711 memory_region_init_io(&s->io, OBJECT(dev), &ne2000_ops, s, "ne2000", size);
712 }
713
714 static NetClientInfo net_ne2000_info = {
715 .type = NET_CLIENT_DRIVER_NIC,
716 .size = sizeof(NICState),
717 .receive = ne2000_receive,
718 };
719
720 static void pci_ne2000_realize(PCIDevice *pci_dev, Error **errp)
721 {
722 PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
723 NE2000State *s;
724 uint8_t *pci_conf;
725
726 pci_conf = d->dev.config;
727 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
728
729 s = &d->ne2000;
730 ne2000_setup_io(s, DEVICE(pci_dev), 0x100);
731 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
732 s->irq = pci_allocate_irq(&d->dev);
733
734 qemu_macaddr_default_if_unset(&s->c.macaddr);
735 ne2000_reset(s);
736
737 s->nic = qemu_new_nic(&net_ne2000_info, &s->c,
738 object_get_typename(OBJECT(pci_dev)), pci_dev->qdev.id, s);
739 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->c.macaddr.a);
740 }
741
742 static void pci_ne2000_exit(PCIDevice *pci_dev)
743 {
744 PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
745 NE2000State *s = &d->ne2000;
746
747 qemu_del_nic(s->nic);
748 qemu_free_irq(s->irq);
749 }
750
751 static void ne2000_instance_init(Object *obj)
752 {
753 PCIDevice *pci_dev = PCI_DEVICE(obj);
754 PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
755 NE2000State *s = &d->ne2000;
756
757 device_add_bootindex_property(obj, &s->c.bootindex,
758 "bootindex", "/ethernet-phy@0",
759 &pci_dev->qdev, NULL);
760 }
761
762 static Property ne2000_properties[] = {
763 DEFINE_NIC_PROPERTIES(PCINE2000State, ne2000.c),
764 DEFINE_PROP_END_OF_LIST(),
765 };
766
767 static void ne2000_class_init(ObjectClass *klass, void *data)
768 {
769 DeviceClass *dc = DEVICE_CLASS(klass);
770 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
771
772 k->realize = pci_ne2000_realize;
773 k->exit = pci_ne2000_exit;
774 k->romfile = "efi-ne2k_pci.rom",
775 k->vendor_id = PCI_VENDOR_ID_REALTEK;
776 k->device_id = PCI_DEVICE_ID_REALTEK_8029;
777 k->class_id = PCI_CLASS_NETWORK_ETHERNET;
778 dc->vmsd = &vmstate_pci_ne2000;
779 dc->props = ne2000_properties;
780 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
781 }
782
783 static const TypeInfo ne2000_info = {
784 .name = "ne2k_pci",
785 .parent = TYPE_PCI_DEVICE,
786 .instance_size = sizeof(PCINE2000State),
787 .class_init = ne2000_class_init,
788 .instance_init = ne2000_instance_init,
789 };
790
791 static void ne2000_register_types(void)
792 {
793 type_register_static(&ne2000_info);
794 }
795
796 type_init(ne2000_register_types)