rtl8139: check TCP Data Offset field (CVE-2015-5165)
[qemu.git] / hw / net / rtl8139.c
1 /**
2 * QEMU RTL8139 emulation
3 *
4 * Copyright (c) 2006 Igor Kovalenko
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23
24 * Modifications:
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
26 *
27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28 * HW revision ID changes for FreeBSD driver
29 *
30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31 * Corrected packet transfer reassembly routine for 8139C+ mode
32 * Rearranged debugging print statements
33 * Implemented PCI timer interrupt (disabled by default)
34 * Implemented Tally Counters, increased VM load/save version
35 * Implemented IP/TCP/UDP checksum task offloading
36 *
37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
38 * Fixed MTU=1500 for produced ethernet frames
39 *
40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
41 * segmentation offloading
42 * Removed slirp.h dependency
43 * Added rx/tx buffer reset when enabling rx/tx operation
44 *
45 * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only
46 * when strictly needed (required for for
47 * Darwin)
48 * 2011-Mar-22 Benjamin Poirier: Implemented VLAN offloading
49 */
50
51 /* For crc32 */
52 #include <zlib.h>
53
54 #include "hw/hw.h"
55 #include "hw/pci/pci.h"
56 #include "sysemu/dma.h"
57 #include "qemu/timer.h"
58 #include "net/net.h"
59 #include "hw/loader.h"
60 #include "sysemu/sysemu.h"
61 #include "qemu/iov.h"
62
63 /* debug RTL8139 card */
64 //#define DEBUG_RTL8139 1
65
66 #define PCI_FREQUENCY 33000000L
67
68 #define SET_MASKED(input, mask, curr) \
69 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
70
71 /* arg % size for size which is a power of 2 */
72 #define MOD2(input, size) \
73 ( ( input ) & ( size - 1 ) )
74
75 #define ETHER_ADDR_LEN 6
76 #define ETHER_TYPE_LEN 2
77 #define ETH_HLEN (ETHER_ADDR_LEN * 2 + ETHER_TYPE_LEN)
78 #define ETH_P_IP 0x0800 /* Internet Protocol packet */
79 #define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
80 #define ETH_MTU 1500
81
82 #define VLAN_TCI_LEN 2
83 #define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN)
84
85 #if defined (DEBUG_RTL8139)
86 # define DPRINTF(fmt, ...) \
87 do { fprintf(stderr, "RTL8139: " fmt, ## __VA_ARGS__); } while (0)
88 #else
89 static inline GCC_FMT_ATTR(1, 2) int DPRINTF(const char *fmt, ...)
90 {
91 return 0;
92 }
93 #endif
94
95 #define TYPE_RTL8139 "rtl8139"
96
97 #define RTL8139(obj) \
98 OBJECT_CHECK(RTL8139State, (obj), TYPE_RTL8139)
99
100 /* Symbolic offsets to registers. */
101 enum RTL8139_registers {
102 MAC0 = 0, /* Ethernet hardware address. */
103 MAR0 = 8, /* Multicast filter. */
104 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
105 /* Dump Tally Conter control register(64bit). C+ mode only */
106 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
107 RxBuf = 0x30,
108 ChipCmd = 0x37,
109 RxBufPtr = 0x38,
110 RxBufAddr = 0x3A,
111 IntrMask = 0x3C,
112 IntrStatus = 0x3E,
113 TxConfig = 0x40,
114 RxConfig = 0x44,
115 Timer = 0x48, /* A general-purpose counter. */
116 RxMissed = 0x4C, /* 24 bits valid, write clears. */
117 Cfg9346 = 0x50,
118 Config0 = 0x51,
119 Config1 = 0x52,
120 FlashReg = 0x54,
121 MediaStatus = 0x58,
122 Config3 = 0x59,
123 Config4 = 0x5A, /* absent on RTL-8139A */
124 HltClk = 0x5B,
125 MultiIntr = 0x5C,
126 PCIRevisionID = 0x5E,
127 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
128 BasicModeCtrl = 0x62,
129 BasicModeStatus = 0x64,
130 NWayAdvert = 0x66,
131 NWayLPAR = 0x68,
132 NWayExpansion = 0x6A,
133 /* Undocumented registers, but required for proper operation. */
134 FIFOTMS = 0x70, /* FIFO Control and test. */
135 CSCR = 0x74, /* Chip Status and Configuration Register. */
136 PARA78 = 0x78,
137 PARA7c = 0x7c, /* Magic transceiver parameter register. */
138 Config5 = 0xD8, /* absent on RTL-8139A */
139 /* C+ mode */
140 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
141 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
142 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
143 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
144 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
145 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
146 TxThresh = 0xEC, /* Early Tx threshold */
147 };
148
149 enum ClearBitMasks {
150 MultiIntrClear = 0xF000,
151 ChipCmdClear = 0xE2,
152 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
153 };
154
155 enum ChipCmdBits {
156 CmdReset = 0x10,
157 CmdRxEnb = 0x08,
158 CmdTxEnb = 0x04,
159 RxBufEmpty = 0x01,
160 };
161
162 /* C+ mode */
163 enum CplusCmdBits {
164 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */
165 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
166 CPlusRxEnb = 0x0002,
167 CPlusTxEnb = 0x0001,
168 };
169
170 /* Interrupt register bits, using my own meaningful names. */
171 enum IntrStatusBits {
172 PCIErr = 0x8000,
173 PCSTimeout = 0x4000,
174 RxFIFOOver = 0x40,
175 RxUnderrun = 0x20, /* Packet Underrun / Link Change */
176 RxOverflow = 0x10,
177 TxErr = 0x08,
178 TxOK = 0x04,
179 RxErr = 0x02,
180 RxOK = 0x01,
181
182 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
183 };
184
185 enum TxStatusBits {
186 TxHostOwns = 0x2000,
187 TxUnderrun = 0x4000,
188 TxStatOK = 0x8000,
189 TxOutOfWindow = 0x20000000,
190 TxAborted = 0x40000000,
191 TxCarrierLost = 0x80000000,
192 };
193 enum RxStatusBits {
194 RxMulticast = 0x8000,
195 RxPhysical = 0x4000,
196 RxBroadcast = 0x2000,
197 RxBadSymbol = 0x0020,
198 RxRunt = 0x0010,
199 RxTooLong = 0x0008,
200 RxCRCErr = 0x0004,
201 RxBadAlign = 0x0002,
202 RxStatusOK = 0x0001,
203 };
204
205 /* Bits in RxConfig. */
206 enum rx_mode_bits {
207 AcceptErr = 0x20,
208 AcceptRunt = 0x10,
209 AcceptBroadcast = 0x08,
210 AcceptMulticast = 0x04,
211 AcceptMyPhys = 0x02,
212 AcceptAllPhys = 0x01,
213 };
214
215 /* Bits in TxConfig. */
216 enum tx_config_bits {
217
218 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
219 TxIFGShift = 24,
220 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
221 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
222 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
223 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
224
225 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
226 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
227 TxClearAbt = (1 << 0), /* Clear abort (WO) */
228 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
229 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
230
231 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
232 };
233
234
235 /* Transmit Status of All Descriptors (TSAD) Register */
236 enum TSAD_bits {
237 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
238 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
239 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
240 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
241 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
242 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
243 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
244 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
245 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
246 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
247 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
248 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
249 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
250 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
251 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
252 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
253 };
254
255
256 /* Bits in Config1 */
257 enum Config1Bits {
258 Cfg1_PM_Enable = 0x01,
259 Cfg1_VPD_Enable = 0x02,
260 Cfg1_PIO = 0x04,
261 Cfg1_MMIO = 0x08,
262 LWAKE = 0x10, /* not on 8139, 8139A */
263 Cfg1_Driver_Load = 0x20,
264 Cfg1_LED0 = 0x40,
265 Cfg1_LED1 = 0x80,
266 SLEEP = (1 << 1), /* only on 8139, 8139A */
267 PWRDN = (1 << 0), /* only on 8139, 8139A */
268 };
269
270 /* Bits in Config3 */
271 enum Config3Bits {
272 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
273 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
274 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
275 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
276 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
277 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
278 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
279 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
280 };
281
282 /* Bits in Config4 */
283 enum Config4Bits {
284 LWPTN = (1 << 2), /* not on 8139, 8139A */
285 };
286
287 /* Bits in Config5 */
288 enum Config5Bits {
289 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
290 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
291 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
292 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
293 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
294 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
295 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
296 };
297
298 enum RxConfigBits {
299 /* rx fifo threshold */
300 RxCfgFIFOShift = 13,
301 RxCfgFIFONone = (7 << RxCfgFIFOShift),
302
303 /* Max DMA burst */
304 RxCfgDMAShift = 8,
305 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
306
307 /* rx ring buffer length */
308 RxCfgRcv8K = 0,
309 RxCfgRcv16K = (1 << 11),
310 RxCfgRcv32K = (1 << 12),
311 RxCfgRcv64K = (1 << 11) | (1 << 12),
312
313 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
314 RxNoWrap = (1 << 7),
315 };
316
317 /* Twister tuning parameters from RealTek.
318 Completely undocumented, but required to tune bad links on some boards. */
319 /*
320 enum CSCRBits {
321 CSCR_LinkOKBit = 0x0400,
322 CSCR_LinkChangeBit = 0x0800,
323 CSCR_LinkStatusBits = 0x0f000,
324 CSCR_LinkDownOffCmd = 0x003c0,
325 CSCR_LinkDownCmd = 0x0f3c0,
326 */
327 enum CSCRBits {
328 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
329 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
330 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
331 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
332 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
333 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
334 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
335 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
336 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
337 };
338
339 enum Cfg9346Bits {
340 Cfg9346_Normal = 0x00,
341 Cfg9346_Autoload = 0x40,
342 Cfg9346_Programming = 0x80,
343 Cfg9346_ConfigWrite = 0xC0,
344 };
345
346 typedef enum {
347 CH_8139 = 0,
348 CH_8139_K,
349 CH_8139A,
350 CH_8139A_G,
351 CH_8139B,
352 CH_8130,
353 CH_8139C,
354 CH_8100,
355 CH_8100B_8139D,
356 CH_8101,
357 } chip_t;
358
359 enum chip_flags {
360 HasHltClk = (1 << 0),
361 HasLWake = (1 << 1),
362 };
363
364 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
365 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
366 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
367
368 #define RTL8139_PCI_REVID_8139 0x10
369 #define RTL8139_PCI_REVID_8139CPLUS 0x20
370
371 #define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
372
373 /* Size is 64 * 16bit words */
374 #define EEPROM_9346_ADDR_BITS 6
375 #define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
376 #define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
377
378 enum Chip9346Operation
379 {
380 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */
381 Chip9346_op_read = 0x80, /* 10 AAAAAA */
382 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */
383 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */
384 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */
385 Chip9346_op_write_all = 0x10, /* 00 01zzzz */
386 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
387 };
388
389 enum Chip9346Mode
390 {
391 Chip9346_none = 0,
392 Chip9346_enter_command_mode,
393 Chip9346_read_command,
394 Chip9346_data_read, /* from output register */
395 Chip9346_data_write, /* to input register, then to contents at specified address */
396 Chip9346_data_write_all, /* to input register, then filling contents */
397 };
398
399 typedef struct EEprom9346
400 {
401 uint16_t contents[EEPROM_9346_SIZE];
402 int mode;
403 uint32_t tick;
404 uint8_t address;
405 uint16_t input;
406 uint16_t output;
407
408 uint8_t eecs;
409 uint8_t eesk;
410 uint8_t eedi;
411 uint8_t eedo;
412 } EEprom9346;
413
414 typedef struct RTL8139TallyCounters
415 {
416 /* Tally counters */
417 uint64_t TxOk;
418 uint64_t RxOk;
419 uint64_t TxERR;
420 uint32_t RxERR;
421 uint16_t MissPkt;
422 uint16_t FAE;
423 uint32_t Tx1Col;
424 uint32_t TxMCol;
425 uint64_t RxOkPhy;
426 uint64_t RxOkBrd;
427 uint32_t RxOkMul;
428 uint16_t TxAbt;
429 uint16_t TxUndrn;
430 } RTL8139TallyCounters;
431
432 /* Clears all tally counters */
433 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
434
435 typedef struct RTL8139State {
436 /*< private >*/
437 PCIDevice parent_obj;
438 /*< public >*/
439
440 uint8_t phys[8]; /* mac address */
441 uint8_t mult[8]; /* multicast mask array */
442
443 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
444 uint32_t TxAddr[4]; /* TxAddr0 */
445 uint32_t RxBuf; /* Receive buffer */
446 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
447 uint32_t RxBufPtr;
448 uint32_t RxBufAddr;
449
450 uint16_t IntrStatus;
451 uint16_t IntrMask;
452
453 uint32_t TxConfig;
454 uint32_t RxConfig;
455 uint32_t RxMissed;
456
457 uint16_t CSCR;
458
459 uint8_t Cfg9346;
460 uint8_t Config0;
461 uint8_t Config1;
462 uint8_t Config3;
463 uint8_t Config4;
464 uint8_t Config5;
465
466 uint8_t clock_enabled;
467 uint8_t bChipCmdState;
468
469 uint16_t MultiIntr;
470
471 uint16_t BasicModeCtrl;
472 uint16_t BasicModeStatus;
473 uint16_t NWayAdvert;
474 uint16_t NWayLPAR;
475 uint16_t NWayExpansion;
476
477 uint16_t CpCmd;
478 uint8_t TxThresh;
479
480 NICState *nic;
481 NICConf conf;
482
483 /* C ring mode */
484 uint32_t currTxDesc;
485
486 /* C+ mode */
487 uint32_t cplus_enabled;
488
489 uint32_t currCPlusRxDesc;
490 uint32_t currCPlusTxDesc;
491
492 uint32_t RxRingAddrLO;
493 uint32_t RxRingAddrHI;
494
495 EEprom9346 eeprom;
496
497 uint32_t TCTR;
498 uint32_t TimerInt;
499 int64_t TCTR_base;
500
501 /* Tally counters */
502 RTL8139TallyCounters tally_counters;
503
504 /* Non-persistent data */
505 uint8_t *cplus_txbuffer;
506 int cplus_txbuffer_len;
507 int cplus_txbuffer_offset;
508
509 /* PCI interrupt timer */
510 QEMUTimer *timer;
511
512 MemoryRegion bar_io;
513 MemoryRegion bar_mem;
514
515 /* Support migration to/from old versions */
516 int rtl8139_mmio_io_addr_dummy;
517 } RTL8139State;
518
519 /* Writes tally counters to memory via DMA */
520 static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr);
521
522 static void rtl8139_set_next_tctr_time(RTL8139State *s);
523
524 static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
525 {
526 DPRINTF("eeprom command 0x%02x\n", command);
527
528 switch (command & Chip9346_op_mask)
529 {
530 case Chip9346_op_read:
531 {
532 eeprom->address = command & EEPROM_9346_ADDR_MASK;
533 eeprom->output = eeprom->contents[eeprom->address];
534 eeprom->eedo = 0;
535 eeprom->tick = 0;
536 eeprom->mode = Chip9346_data_read;
537 DPRINTF("eeprom read from address 0x%02x data=0x%04x\n",
538 eeprom->address, eeprom->output);
539 }
540 break;
541
542 case Chip9346_op_write:
543 {
544 eeprom->address = command & EEPROM_9346_ADDR_MASK;
545 eeprom->input = 0;
546 eeprom->tick = 0;
547 eeprom->mode = Chip9346_none; /* Chip9346_data_write */
548 DPRINTF("eeprom begin write to address 0x%02x\n",
549 eeprom->address);
550 }
551 break;
552 default:
553 eeprom->mode = Chip9346_none;
554 switch (command & Chip9346_op_ext_mask)
555 {
556 case Chip9346_op_write_enable:
557 DPRINTF("eeprom write enabled\n");
558 break;
559 case Chip9346_op_write_all:
560 DPRINTF("eeprom begin write all\n");
561 break;
562 case Chip9346_op_write_disable:
563 DPRINTF("eeprom write disabled\n");
564 break;
565 }
566 break;
567 }
568 }
569
570 static void prom9346_shift_clock(EEprom9346 *eeprom)
571 {
572 int bit = eeprom->eedi?1:0;
573
574 ++ eeprom->tick;
575
576 DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi,
577 eeprom->eedo);
578
579 switch (eeprom->mode)
580 {
581 case Chip9346_enter_command_mode:
582 if (bit)
583 {
584 eeprom->mode = Chip9346_read_command;
585 eeprom->tick = 0;
586 eeprom->input = 0;
587 DPRINTF("eeprom: +++ synchronized, begin command read\n");
588 }
589 break;
590
591 case Chip9346_read_command:
592 eeprom->input = (eeprom->input << 1) | (bit & 1);
593 if (eeprom->tick == 8)
594 {
595 prom9346_decode_command(eeprom, eeprom->input & 0xff);
596 }
597 break;
598
599 case Chip9346_data_read:
600 eeprom->eedo = (eeprom->output & 0x8000)?1:0;
601 eeprom->output <<= 1;
602 if (eeprom->tick == 16)
603 {
604 #if 1
605 // the FreeBSD drivers (rl and re) don't explicitly toggle
606 // CS between reads (or does setting Cfg9346 to 0 count too?),
607 // so we need to enter wait-for-command state here
608 eeprom->mode = Chip9346_enter_command_mode;
609 eeprom->input = 0;
610 eeprom->tick = 0;
611
612 DPRINTF("eeprom: +++ end of read, awaiting next command\n");
613 #else
614 // original behaviour
615 ++eeprom->address;
616 eeprom->address &= EEPROM_9346_ADDR_MASK;
617 eeprom->output = eeprom->contents[eeprom->address];
618 eeprom->tick = 0;
619
620 DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n",
621 eeprom->address, eeprom->output);
622 #endif
623 }
624 break;
625
626 case Chip9346_data_write:
627 eeprom->input = (eeprom->input << 1) | (bit & 1);
628 if (eeprom->tick == 16)
629 {
630 DPRINTF("eeprom write to address 0x%02x data=0x%04x\n",
631 eeprom->address, eeprom->input);
632
633 eeprom->contents[eeprom->address] = eeprom->input;
634 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
635 eeprom->tick = 0;
636 eeprom->input = 0;
637 }
638 break;
639
640 case Chip9346_data_write_all:
641 eeprom->input = (eeprom->input << 1) | (bit & 1);
642 if (eeprom->tick == 16)
643 {
644 int i;
645 for (i = 0; i < EEPROM_9346_SIZE; i++)
646 {
647 eeprom->contents[i] = eeprom->input;
648 }
649 DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input);
650
651 eeprom->mode = Chip9346_enter_command_mode;
652 eeprom->tick = 0;
653 eeprom->input = 0;
654 }
655 break;
656
657 default:
658 break;
659 }
660 }
661
662 static int prom9346_get_wire(RTL8139State *s)
663 {
664 EEprom9346 *eeprom = &s->eeprom;
665 if (!eeprom->eecs)
666 return 0;
667
668 return eeprom->eedo;
669 }
670
671 /* FIXME: This should be merged into/replaced by eeprom93xx.c. */
672 static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
673 {
674 EEprom9346 *eeprom = &s->eeprom;
675 uint8_t old_eecs = eeprom->eecs;
676 uint8_t old_eesk = eeprom->eesk;
677
678 eeprom->eecs = eecs;
679 eeprom->eesk = eesk;
680 eeprom->eedi = eedi;
681
682 DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs,
683 eeprom->eesk, eeprom->eedi, eeprom->eedo);
684
685 if (!old_eecs && eecs)
686 {
687 /* Synchronize start */
688 eeprom->tick = 0;
689 eeprom->input = 0;
690 eeprom->output = 0;
691 eeprom->mode = Chip9346_enter_command_mode;
692
693 DPRINTF("=== eeprom: begin access, enter command mode\n");
694 }
695
696 if (!eecs)
697 {
698 DPRINTF("=== eeprom: end access\n");
699 return;
700 }
701
702 if (!old_eesk && eesk)
703 {
704 /* SK front rules */
705 prom9346_shift_clock(eeprom);
706 }
707 }
708
709 static void rtl8139_update_irq(RTL8139State *s)
710 {
711 PCIDevice *d = PCI_DEVICE(s);
712 int isr;
713 isr = (s->IntrStatus & s->IntrMask) & 0xffff;
714
715 DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus,
716 s->IntrMask);
717
718 pci_set_irq(d, (isr != 0));
719 }
720
721 static int rtl8139_RxWrap(RTL8139State *s)
722 {
723 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
724 return (s->RxConfig & (1 << 7));
725 }
726
727 static int rtl8139_receiver_enabled(RTL8139State *s)
728 {
729 return s->bChipCmdState & CmdRxEnb;
730 }
731
732 static int rtl8139_transmitter_enabled(RTL8139State *s)
733 {
734 return s->bChipCmdState & CmdTxEnb;
735 }
736
737 static int rtl8139_cp_receiver_enabled(RTL8139State *s)
738 {
739 return s->CpCmd & CPlusRxEnb;
740 }
741
742 static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
743 {
744 return s->CpCmd & CPlusTxEnb;
745 }
746
747 static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
748 {
749 PCIDevice *d = PCI_DEVICE(s);
750
751 if (s->RxBufAddr + size > s->RxBufferSize)
752 {
753 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
754
755 /* write packet data */
756 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
757 {
758 DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped);
759
760 if (size > wrapped)
761 {
762 pci_dma_write(d, s->RxBuf + s->RxBufAddr,
763 buf, size-wrapped);
764 }
765
766 /* reset buffer pointer */
767 s->RxBufAddr = 0;
768
769 pci_dma_write(d, s->RxBuf + s->RxBufAddr,
770 buf + (size-wrapped), wrapped);
771
772 s->RxBufAddr = wrapped;
773
774 return;
775 }
776 }
777
778 /* non-wrapping path or overwrapping enabled */
779 pci_dma_write(d, s->RxBuf + s->RxBufAddr, buf, size);
780
781 s->RxBufAddr += size;
782 }
783
784 #define MIN_BUF_SIZE 60
785 static inline dma_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
786 {
787 return low | ((uint64_t)high << 32);
788 }
789
790 /* Workaround for buggy guest driver such as linux who allocates rx
791 * rings after the receiver were enabled. */
792 static bool rtl8139_cp_rx_valid(RTL8139State *s)
793 {
794 return !(s->RxRingAddrLO == 0 && s->RxRingAddrHI == 0);
795 }
796
797 static int rtl8139_can_receive(NetClientState *nc)
798 {
799 RTL8139State *s = qemu_get_nic_opaque(nc);
800 int avail;
801
802 /* Receive (drop) packets if card is disabled. */
803 if (!s->clock_enabled)
804 return 1;
805 if (!rtl8139_receiver_enabled(s))
806 return 1;
807
808 if (rtl8139_cp_receiver_enabled(s) && rtl8139_cp_rx_valid(s)) {
809 /* ??? Flow control not implemented in c+ mode.
810 This is a hack to work around slirp deficiencies anyway. */
811 return 1;
812 } else {
813 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
814 s->RxBufferSize);
815 return (avail == 0 || avail >= 1514 || (s->IntrMask & RxOverflow));
816 }
817 }
818
819 static ssize_t rtl8139_do_receive(NetClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt)
820 {
821 RTL8139State *s = qemu_get_nic_opaque(nc);
822 PCIDevice *d = PCI_DEVICE(s);
823 /* size is the length of the buffer passed to the driver */
824 int size = size_;
825 const uint8_t *dot1q_buf = NULL;
826
827 uint32_t packet_header = 0;
828
829 uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN];
830 static const uint8_t broadcast_macaddr[6] =
831 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
832
833 DPRINTF(">>> received len=%d\n", size);
834
835 /* test if board clock is stopped */
836 if (!s->clock_enabled)
837 {
838 DPRINTF("stopped ==========================\n");
839 return -1;
840 }
841
842 /* first check if receiver is enabled */
843
844 if (!rtl8139_receiver_enabled(s))
845 {
846 DPRINTF("receiver disabled ================\n");
847 return -1;
848 }
849
850 /* XXX: check this */
851 if (s->RxConfig & AcceptAllPhys) {
852 /* promiscuous: receive all */
853 DPRINTF(">>> packet received in promiscuous mode\n");
854
855 } else {
856 if (!memcmp(buf, broadcast_macaddr, 6)) {
857 /* broadcast address */
858 if (!(s->RxConfig & AcceptBroadcast))
859 {
860 DPRINTF(">>> broadcast packet rejected\n");
861
862 /* update tally counter */
863 ++s->tally_counters.RxERR;
864
865 return size;
866 }
867
868 packet_header |= RxBroadcast;
869
870 DPRINTF(">>> broadcast packet received\n");
871
872 /* update tally counter */
873 ++s->tally_counters.RxOkBrd;
874
875 } else if (buf[0] & 0x01) {
876 /* multicast */
877 if (!(s->RxConfig & AcceptMulticast))
878 {
879 DPRINTF(">>> multicast packet rejected\n");
880
881 /* update tally counter */
882 ++s->tally_counters.RxERR;
883
884 return size;
885 }
886
887 int mcast_idx = compute_mcast_idx(buf);
888
889 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
890 {
891 DPRINTF(">>> multicast address mismatch\n");
892
893 /* update tally counter */
894 ++s->tally_counters.RxERR;
895
896 return size;
897 }
898
899 packet_header |= RxMulticast;
900
901 DPRINTF(">>> multicast packet received\n");
902
903 /* update tally counter */
904 ++s->tally_counters.RxOkMul;
905
906 } else if (s->phys[0] == buf[0] &&
907 s->phys[1] == buf[1] &&
908 s->phys[2] == buf[2] &&
909 s->phys[3] == buf[3] &&
910 s->phys[4] == buf[4] &&
911 s->phys[5] == buf[5]) {
912 /* match */
913 if (!(s->RxConfig & AcceptMyPhys))
914 {
915 DPRINTF(">>> rejecting physical address matching packet\n");
916
917 /* update tally counter */
918 ++s->tally_counters.RxERR;
919
920 return size;
921 }
922
923 packet_header |= RxPhysical;
924
925 DPRINTF(">>> physical address matching packet received\n");
926
927 /* update tally counter */
928 ++s->tally_counters.RxOkPhy;
929
930 } else {
931
932 DPRINTF(">>> unknown packet\n");
933
934 /* update tally counter */
935 ++s->tally_counters.RxERR;
936
937 return size;
938 }
939 }
940
941 /* if too small buffer, then expand it
942 * Include some tailroom in case a vlan tag is later removed. */
943 if (size < MIN_BUF_SIZE + VLAN_HLEN) {
944 memcpy(buf1, buf, size);
945 memset(buf1 + size, 0, MIN_BUF_SIZE + VLAN_HLEN - size);
946 buf = buf1;
947 if (size < MIN_BUF_SIZE) {
948 size = MIN_BUF_SIZE;
949 }
950 }
951
952 if (rtl8139_cp_receiver_enabled(s))
953 {
954 if (!rtl8139_cp_rx_valid(s)) {
955 return size;
956 }
957
958 DPRINTF("in C+ Rx mode ================\n");
959
960 /* begin C+ receiver mode */
961
962 /* w0 ownership flag */
963 #define CP_RX_OWN (1<<31)
964 /* w0 end of ring flag */
965 #define CP_RX_EOR (1<<30)
966 /* w0 bits 0...12 : buffer size */
967 #define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
968 /* w1 tag available flag */
969 #define CP_RX_TAVA (1<<16)
970 /* w1 bits 0...15 : VLAN tag */
971 #define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
972 /* w2 low 32bit of Rx buffer ptr */
973 /* w3 high 32bit of Rx buffer ptr */
974
975 int descriptor = s->currCPlusRxDesc;
976 dma_addr_t cplus_rx_ring_desc;
977
978 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
979 cplus_rx_ring_desc += 16 * descriptor;
980
981 DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at "
982 "%08x %08x = "DMA_ADDR_FMT"\n", descriptor, s->RxRingAddrHI,
983 s->RxRingAddrLO, cplus_rx_ring_desc);
984
985 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
986
987 pci_dma_read(d, cplus_rx_ring_desc, &val, 4);
988 rxdw0 = le32_to_cpu(val);
989 pci_dma_read(d, cplus_rx_ring_desc+4, &val, 4);
990 rxdw1 = le32_to_cpu(val);
991 pci_dma_read(d, cplus_rx_ring_desc+8, &val, 4);
992 rxbufLO = le32_to_cpu(val);
993 pci_dma_read(d, cplus_rx_ring_desc+12, &val, 4);
994 rxbufHI = le32_to_cpu(val);
995
996 DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
997 descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI);
998
999 if (!(rxdw0 & CP_RX_OWN))
1000 {
1001 DPRINTF("C+ Rx mode : descriptor %d is owned by host\n",
1002 descriptor);
1003
1004 s->IntrStatus |= RxOverflow;
1005 ++s->RxMissed;
1006
1007 /* update tally counter */
1008 ++s->tally_counters.RxERR;
1009 ++s->tally_counters.MissPkt;
1010
1011 rtl8139_update_irq(s);
1012 return size_;
1013 }
1014
1015 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
1016
1017 /* write VLAN info to descriptor variables. */
1018 if (s->CpCmd & CPlusRxVLAN && be16_to_cpup((uint16_t *)
1019 &buf[ETHER_ADDR_LEN * 2]) == ETH_P_8021Q) {
1020 dot1q_buf = &buf[ETHER_ADDR_LEN * 2];
1021 size -= VLAN_HLEN;
1022 /* if too small buffer, use the tailroom added duing expansion */
1023 if (size < MIN_BUF_SIZE) {
1024 size = MIN_BUF_SIZE;
1025 }
1026
1027 rxdw1 &= ~CP_RX_VLAN_TAG_MASK;
1028 /* BE + ~le_to_cpu()~ + cpu_to_le() = BE */
1029 rxdw1 |= CP_RX_TAVA | le16_to_cpup((uint16_t *)
1030 &dot1q_buf[ETHER_TYPE_LEN]);
1031
1032 DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n",
1033 be16_to_cpup((uint16_t *)&dot1q_buf[ETHER_TYPE_LEN]));
1034 } else {
1035 /* reset VLAN tag flag */
1036 rxdw1 &= ~CP_RX_TAVA;
1037 }
1038
1039 /* TODO: scatter the packet over available receive ring descriptors space */
1040
1041 if (size+4 > rx_space)
1042 {
1043 DPRINTF("C+ Rx mode : descriptor %d size %d received %d + 4\n",
1044 descriptor, rx_space, size);
1045
1046 s->IntrStatus |= RxOverflow;
1047 ++s->RxMissed;
1048
1049 /* update tally counter */
1050 ++s->tally_counters.RxERR;
1051 ++s->tally_counters.MissPkt;
1052
1053 rtl8139_update_irq(s);
1054 return size_;
1055 }
1056
1057 dma_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
1058
1059 /* receive/copy to target memory */
1060 if (dot1q_buf) {
1061 pci_dma_write(d, rx_addr, buf, 2 * ETHER_ADDR_LEN);
1062 pci_dma_write(d, rx_addr + 2 * ETHER_ADDR_LEN,
1063 buf + 2 * ETHER_ADDR_LEN + VLAN_HLEN,
1064 size - 2 * ETHER_ADDR_LEN);
1065 } else {
1066 pci_dma_write(d, rx_addr, buf, size);
1067 }
1068
1069 if (s->CpCmd & CPlusRxChkSum)
1070 {
1071 /* do some packet checksumming */
1072 }
1073
1074 /* write checksum */
1075 val = cpu_to_le32(crc32(0, buf, size_));
1076 pci_dma_write(d, rx_addr+size, (uint8_t *)&val, 4);
1077
1078 /* first segment of received packet flag */
1079 #define CP_RX_STATUS_FS (1<<29)
1080 /* last segment of received packet flag */
1081 #define CP_RX_STATUS_LS (1<<28)
1082 /* multicast packet flag */
1083 #define CP_RX_STATUS_MAR (1<<26)
1084 /* physical-matching packet flag */
1085 #define CP_RX_STATUS_PAM (1<<25)
1086 /* broadcast packet flag */
1087 #define CP_RX_STATUS_BAR (1<<24)
1088 /* runt packet flag */
1089 #define CP_RX_STATUS_RUNT (1<<19)
1090 /* crc error flag */
1091 #define CP_RX_STATUS_CRC (1<<18)
1092 /* IP checksum error flag */
1093 #define CP_RX_STATUS_IPF (1<<15)
1094 /* UDP checksum error flag */
1095 #define CP_RX_STATUS_UDPF (1<<14)
1096 /* TCP checksum error flag */
1097 #define CP_RX_STATUS_TCPF (1<<13)
1098
1099 /* transfer ownership to target */
1100 rxdw0 &= ~CP_RX_OWN;
1101
1102 /* set first segment bit */
1103 rxdw0 |= CP_RX_STATUS_FS;
1104
1105 /* set last segment bit */
1106 rxdw0 |= CP_RX_STATUS_LS;
1107
1108 /* set received packet type flags */
1109 if (packet_header & RxBroadcast)
1110 rxdw0 |= CP_RX_STATUS_BAR;
1111 if (packet_header & RxMulticast)
1112 rxdw0 |= CP_RX_STATUS_MAR;
1113 if (packet_header & RxPhysical)
1114 rxdw0 |= CP_RX_STATUS_PAM;
1115
1116 /* set received size */
1117 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
1118 rxdw0 |= (size+4);
1119
1120 /* update ring data */
1121 val = cpu_to_le32(rxdw0);
1122 pci_dma_write(d, cplus_rx_ring_desc, (uint8_t *)&val, 4);
1123 val = cpu_to_le32(rxdw1);
1124 pci_dma_write(d, cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
1125
1126 /* update tally counter */
1127 ++s->tally_counters.RxOk;
1128
1129 /* seek to next Rx descriptor */
1130 if (rxdw0 & CP_RX_EOR)
1131 {
1132 s->currCPlusRxDesc = 0;
1133 }
1134 else
1135 {
1136 ++s->currCPlusRxDesc;
1137 }
1138
1139 DPRINTF("done C+ Rx mode ----------------\n");
1140
1141 }
1142 else
1143 {
1144 DPRINTF("in ring Rx mode ================\n");
1145
1146 /* begin ring receiver mode */
1147 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
1148
1149 /* if receiver buffer is empty then avail == 0 */
1150
1151 if (avail != 0 && size + 8 >= avail)
1152 {
1153 DPRINTF("rx overflow: rx buffer length %d head 0x%04x "
1154 "read 0x%04x === available 0x%04x need 0x%04x\n",
1155 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8);
1156
1157 s->IntrStatus |= RxOverflow;
1158 ++s->RxMissed;
1159 rtl8139_update_irq(s);
1160 return size_;
1161 }
1162
1163 packet_header |= RxStatusOK;
1164
1165 packet_header |= (((size+4) << 16) & 0xffff0000);
1166
1167 /* write header */
1168 uint32_t val = cpu_to_le32(packet_header);
1169
1170 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1171
1172 rtl8139_write_buffer(s, buf, size);
1173
1174 /* write checksum */
1175 val = cpu_to_le32(crc32(0, buf, size));
1176 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1177
1178 /* correct buffer write pointer */
1179 s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize);
1180
1181 /* now we can signal we have received something */
1182
1183 DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n",
1184 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
1185 }
1186
1187 s->IntrStatus |= RxOK;
1188
1189 if (do_interrupt)
1190 {
1191 rtl8139_update_irq(s);
1192 }
1193
1194 return size_;
1195 }
1196
1197 static ssize_t rtl8139_receive(NetClientState *nc, const uint8_t *buf, size_t size)
1198 {
1199 return rtl8139_do_receive(nc, buf, size, 1);
1200 }
1201
1202 static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
1203 {
1204 s->RxBufferSize = bufferSize;
1205 s->RxBufPtr = 0;
1206 s->RxBufAddr = 0;
1207 }
1208
1209 static void rtl8139_reset(DeviceState *d)
1210 {
1211 RTL8139State *s = RTL8139(d);
1212 int i;
1213
1214 /* restore MAC address */
1215 memcpy(s->phys, s->conf.macaddr.a, 6);
1216 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->phys);
1217
1218 /* reset interrupt mask */
1219 s->IntrStatus = 0;
1220 s->IntrMask = 0;
1221
1222 rtl8139_update_irq(s);
1223
1224 /* mark all status registers as owned by host */
1225 for (i = 0; i < 4; ++i)
1226 {
1227 s->TxStatus[i] = TxHostOwns;
1228 }
1229
1230 s->currTxDesc = 0;
1231 s->currCPlusRxDesc = 0;
1232 s->currCPlusTxDesc = 0;
1233
1234 s->RxRingAddrLO = 0;
1235 s->RxRingAddrHI = 0;
1236
1237 s->RxBuf = 0;
1238
1239 rtl8139_reset_rxring(s, 8192);
1240
1241 /* ACK the reset */
1242 s->TxConfig = 0;
1243
1244 #if 0
1245 // s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1246 s->clock_enabled = 0;
1247 #else
1248 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
1249 s->clock_enabled = 1;
1250 #endif
1251
1252 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1253
1254 /* set initial state data */
1255 s->Config0 = 0x0; /* No boot ROM */
1256 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
1257 s->Config3 = 0x1; /* fast back-to-back compatible */
1258 s->Config5 = 0x0;
1259
1260 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
1261
1262 s->CpCmd = 0x0; /* reset C+ mode */
1263 s->cplus_enabled = 0;
1264
1265
1266 // s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1267 // s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1268 s->BasicModeCtrl = 0x1000; // autonegotiation
1269
1270 s->BasicModeStatus = 0x7809;
1271 //s->BasicModeStatus |= 0x0040; /* UTP medium */
1272 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
1273 /* preserve link state */
1274 s->BasicModeStatus |= qemu_get_queue(s->nic)->link_down ? 0 : 0x04;
1275
1276 s->NWayAdvert = 0x05e1; /* all modes, full duplex */
1277 s->NWayLPAR = 0x05e1; /* all modes, full duplex */
1278 s->NWayExpansion = 0x0001; /* autonegotiation supported */
1279
1280 /* also reset timer and disable timer interrupt */
1281 s->TCTR = 0;
1282 s->TimerInt = 0;
1283 s->TCTR_base = 0;
1284 rtl8139_set_next_tctr_time(s);
1285
1286 /* reset tally counters */
1287 RTL8139TallyCounters_clear(&s->tally_counters);
1288 }
1289
1290 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
1291 {
1292 counters->TxOk = 0;
1293 counters->RxOk = 0;
1294 counters->TxERR = 0;
1295 counters->RxERR = 0;
1296 counters->MissPkt = 0;
1297 counters->FAE = 0;
1298 counters->Tx1Col = 0;
1299 counters->TxMCol = 0;
1300 counters->RxOkPhy = 0;
1301 counters->RxOkBrd = 0;
1302 counters->RxOkMul = 0;
1303 counters->TxAbt = 0;
1304 counters->TxUndrn = 0;
1305 }
1306
1307 static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr)
1308 {
1309 PCIDevice *d = PCI_DEVICE(s);
1310 RTL8139TallyCounters *tally_counters = &s->tally_counters;
1311 uint16_t val16;
1312 uint32_t val32;
1313 uint64_t val64;
1314
1315 val64 = cpu_to_le64(tally_counters->TxOk);
1316 pci_dma_write(d, tc_addr + 0, (uint8_t *)&val64, 8);
1317
1318 val64 = cpu_to_le64(tally_counters->RxOk);
1319 pci_dma_write(d, tc_addr + 8, (uint8_t *)&val64, 8);
1320
1321 val64 = cpu_to_le64(tally_counters->TxERR);
1322 pci_dma_write(d, tc_addr + 16, (uint8_t *)&val64, 8);
1323
1324 val32 = cpu_to_le32(tally_counters->RxERR);
1325 pci_dma_write(d, tc_addr + 24, (uint8_t *)&val32, 4);
1326
1327 val16 = cpu_to_le16(tally_counters->MissPkt);
1328 pci_dma_write(d, tc_addr + 28, (uint8_t *)&val16, 2);
1329
1330 val16 = cpu_to_le16(tally_counters->FAE);
1331 pci_dma_write(d, tc_addr + 30, (uint8_t *)&val16, 2);
1332
1333 val32 = cpu_to_le32(tally_counters->Tx1Col);
1334 pci_dma_write(d, tc_addr + 32, (uint8_t *)&val32, 4);
1335
1336 val32 = cpu_to_le32(tally_counters->TxMCol);
1337 pci_dma_write(d, tc_addr + 36, (uint8_t *)&val32, 4);
1338
1339 val64 = cpu_to_le64(tally_counters->RxOkPhy);
1340 pci_dma_write(d, tc_addr + 40, (uint8_t *)&val64, 8);
1341
1342 val64 = cpu_to_le64(tally_counters->RxOkBrd);
1343 pci_dma_write(d, tc_addr + 48, (uint8_t *)&val64, 8);
1344
1345 val32 = cpu_to_le32(tally_counters->RxOkMul);
1346 pci_dma_write(d, tc_addr + 56, (uint8_t *)&val32, 4);
1347
1348 val16 = cpu_to_le16(tally_counters->TxAbt);
1349 pci_dma_write(d, tc_addr + 60, (uint8_t *)&val16, 2);
1350
1351 val16 = cpu_to_le16(tally_counters->TxUndrn);
1352 pci_dma_write(d, tc_addr + 62, (uint8_t *)&val16, 2);
1353 }
1354
1355 /* Loads values of tally counters from VM state file */
1356
1357 static const VMStateDescription vmstate_tally_counters = {
1358 .name = "tally_counters",
1359 .version_id = 1,
1360 .minimum_version_id = 1,
1361 .fields = (VMStateField[]) {
1362 VMSTATE_UINT64(TxOk, RTL8139TallyCounters),
1363 VMSTATE_UINT64(RxOk, RTL8139TallyCounters),
1364 VMSTATE_UINT64(TxERR, RTL8139TallyCounters),
1365 VMSTATE_UINT32(RxERR, RTL8139TallyCounters),
1366 VMSTATE_UINT16(MissPkt, RTL8139TallyCounters),
1367 VMSTATE_UINT16(FAE, RTL8139TallyCounters),
1368 VMSTATE_UINT32(Tx1Col, RTL8139TallyCounters),
1369 VMSTATE_UINT32(TxMCol, RTL8139TallyCounters),
1370 VMSTATE_UINT64(RxOkPhy, RTL8139TallyCounters),
1371 VMSTATE_UINT64(RxOkBrd, RTL8139TallyCounters),
1372 VMSTATE_UINT16(TxAbt, RTL8139TallyCounters),
1373 VMSTATE_UINT16(TxUndrn, RTL8139TallyCounters),
1374 VMSTATE_END_OF_LIST()
1375 }
1376 };
1377
1378 static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
1379 {
1380 DeviceState *d = DEVICE(s);
1381
1382 val &= 0xff;
1383
1384 DPRINTF("ChipCmd write val=0x%08x\n", val);
1385
1386 if (val & CmdReset)
1387 {
1388 DPRINTF("ChipCmd reset\n");
1389 rtl8139_reset(d);
1390 }
1391 if (val & CmdRxEnb)
1392 {
1393 DPRINTF("ChipCmd enable receiver\n");
1394
1395 s->currCPlusRxDesc = 0;
1396 }
1397 if (val & CmdTxEnb)
1398 {
1399 DPRINTF("ChipCmd enable transmitter\n");
1400
1401 s->currCPlusTxDesc = 0;
1402 }
1403
1404 /* mask unwritable bits */
1405 val = SET_MASKED(val, 0xe3, s->bChipCmdState);
1406
1407 /* Deassert reset pin before next read */
1408 val &= ~CmdReset;
1409
1410 s->bChipCmdState = val;
1411 }
1412
1413 static int rtl8139_RxBufferEmpty(RTL8139State *s)
1414 {
1415 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
1416
1417 if (unread != 0)
1418 {
1419 DPRINTF("receiver buffer data available 0x%04x\n", unread);
1420 return 0;
1421 }
1422
1423 DPRINTF("receiver buffer is empty\n");
1424
1425 return 1;
1426 }
1427
1428 static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
1429 {
1430 uint32_t ret = s->bChipCmdState;
1431
1432 if (rtl8139_RxBufferEmpty(s))
1433 ret |= RxBufEmpty;
1434
1435 DPRINTF("ChipCmd read val=0x%04x\n", ret);
1436
1437 return ret;
1438 }
1439
1440 static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
1441 {
1442 val &= 0xffff;
1443
1444 DPRINTF("C+ command register write(w) val=0x%04x\n", val);
1445
1446 s->cplus_enabled = 1;
1447
1448 /* mask unwritable bits */
1449 val = SET_MASKED(val, 0xff84, s->CpCmd);
1450
1451 s->CpCmd = val;
1452 }
1453
1454 static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
1455 {
1456 uint32_t ret = s->CpCmd;
1457
1458 DPRINTF("C+ command register read(w) val=0x%04x\n", ret);
1459
1460 return ret;
1461 }
1462
1463 static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
1464 {
1465 DPRINTF("C+ IntrMitigate register write(w) val=0x%04x\n", val);
1466 }
1467
1468 static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
1469 {
1470 uint32_t ret = 0;
1471
1472 DPRINTF("C+ IntrMitigate register read(w) val=0x%04x\n", ret);
1473
1474 return ret;
1475 }
1476
1477 static int rtl8139_config_writable(RTL8139State *s)
1478 {
1479 if ((s->Cfg9346 & Chip9346_op_mask) == Cfg9346_ConfigWrite)
1480 {
1481 return 1;
1482 }
1483
1484 DPRINTF("Configuration registers are write-protected\n");
1485
1486 return 0;
1487 }
1488
1489 static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
1490 {
1491 val &= 0xffff;
1492
1493 DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val);
1494
1495 /* mask unwritable bits */
1496 uint32_t mask = 0x4cff;
1497
1498 if (1 || !rtl8139_config_writable(s))
1499 {
1500 /* Speed setting and autonegotiation enable bits are read-only */
1501 mask |= 0x3000;
1502 /* Duplex mode setting is read-only */
1503 mask |= 0x0100;
1504 }
1505
1506 val = SET_MASKED(val, mask, s->BasicModeCtrl);
1507
1508 s->BasicModeCtrl = val;
1509 }
1510
1511 static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
1512 {
1513 uint32_t ret = s->BasicModeCtrl;
1514
1515 DPRINTF("BasicModeCtrl register read(w) val=0x%04x\n", ret);
1516
1517 return ret;
1518 }
1519
1520 static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
1521 {
1522 val &= 0xffff;
1523
1524 DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val);
1525
1526 /* mask unwritable bits */
1527 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
1528
1529 s->BasicModeStatus = val;
1530 }
1531
1532 static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
1533 {
1534 uint32_t ret = s->BasicModeStatus;
1535
1536 DPRINTF("BasicModeStatus register read(w) val=0x%04x\n", ret);
1537
1538 return ret;
1539 }
1540
1541 static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
1542 {
1543 DeviceState *d = DEVICE(s);
1544
1545 val &= 0xff;
1546
1547 DPRINTF("Cfg9346 write val=0x%02x\n", val);
1548
1549 /* mask unwritable bits */
1550 val = SET_MASKED(val, 0x31, s->Cfg9346);
1551
1552 uint32_t opmode = val & 0xc0;
1553 uint32_t eeprom_val = val & 0xf;
1554
1555 if (opmode == 0x80) {
1556 /* eeprom access */
1557 int eecs = (eeprom_val & 0x08)?1:0;
1558 int eesk = (eeprom_val & 0x04)?1:0;
1559 int eedi = (eeprom_val & 0x02)?1:0;
1560 prom9346_set_wire(s, eecs, eesk, eedi);
1561 } else if (opmode == 0x40) {
1562 /* Reset. */
1563 val = 0;
1564 rtl8139_reset(d);
1565 }
1566
1567 s->Cfg9346 = val;
1568 }
1569
1570 static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
1571 {
1572 uint32_t ret = s->Cfg9346;
1573
1574 uint32_t opmode = ret & 0xc0;
1575
1576 if (opmode == 0x80)
1577 {
1578 /* eeprom access */
1579 int eedo = prom9346_get_wire(s);
1580 if (eedo)
1581 {
1582 ret |= 0x01;
1583 }
1584 else
1585 {
1586 ret &= ~0x01;
1587 }
1588 }
1589
1590 DPRINTF("Cfg9346 read val=0x%02x\n", ret);
1591
1592 return ret;
1593 }
1594
1595 static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
1596 {
1597 val &= 0xff;
1598
1599 DPRINTF("Config0 write val=0x%02x\n", val);
1600
1601 if (!rtl8139_config_writable(s)) {
1602 return;
1603 }
1604
1605 /* mask unwritable bits */
1606 val = SET_MASKED(val, 0xf8, s->Config0);
1607
1608 s->Config0 = val;
1609 }
1610
1611 static uint32_t rtl8139_Config0_read(RTL8139State *s)
1612 {
1613 uint32_t ret = s->Config0;
1614
1615 DPRINTF("Config0 read val=0x%02x\n", ret);
1616
1617 return ret;
1618 }
1619
1620 static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
1621 {
1622 val &= 0xff;
1623
1624 DPRINTF("Config1 write val=0x%02x\n", val);
1625
1626 if (!rtl8139_config_writable(s)) {
1627 return;
1628 }
1629
1630 /* mask unwritable bits */
1631 val = SET_MASKED(val, 0xC, s->Config1);
1632
1633 s->Config1 = val;
1634 }
1635
1636 static uint32_t rtl8139_Config1_read(RTL8139State *s)
1637 {
1638 uint32_t ret = s->Config1;
1639
1640 DPRINTF("Config1 read val=0x%02x\n", ret);
1641
1642 return ret;
1643 }
1644
1645 static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
1646 {
1647 val &= 0xff;
1648
1649 DPRINTF("Config3 write val=0x%02x\n", val);
1650
1651 if (!rtl8139_config_writable(s)) {
1652 return;
1653 }
1654
1655 /* mask unwritable bits */
1656 val = SET_MASKED(val, 0x8F, s->Config3);
1657
1658 s->Config3 = val;
1659 }
1660
1661 static uint32_t rtl8139_Config3_read(RTL8139State *s)
1662 {
1663 uint32_t ret = s->Config3;
1664
1665 DPRINTF("Config3 read val=0x%02x\n", ret);
1666
1667 return ret;
1668 }
1669
1670 static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
1671 {
1672 val &= 0xff;
1673
1674 DPRINTF("Config4 write val=0x%02x\n", val);
1675
1676 if (!rtl8139_config_writable(s)) {
1677 return;
1678 }
1679
1680 /* mask unwritable bits */
1681 val = SET_MASKED(val, 0x0a, s->Config4);
1682
1683 s->Config4 = val;
1684 }
1685
1686 static uint32_t rtl8139_Config4_read(RTL8139State *s)
1687 {
1688 uint32_t ret = s->Config4;
1689
1690 DPRINTF("Config4 read val=0x%02x\n", ret);
1691
1692 return ret;
1693 }
1694
1695 static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
1696 {
1697 val &= 0xff;
1698
1699 DPRINTF("Config5 write val=0x%02x\n", val);
1700
1701 /* mask unwritable bits */
1702 val = SET_MASKED(val, 0x80, s->Config5);
1703
1704 s->Config5 = val;
1705 }
1706
1707 static uint32_t rtl8139_Config5_read(RTL8139State *s)
1708 {
1709 uint32_t ret = s->Config5;
1710
1711 DPRINTF("Config5 read val=0x%02x\n", ret);
1712
1713 return ret;
1714 }
1715
1716 static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
1717 {
1718 if (!rtl8139_transmitter_enabled(s))
1719 {
1720 DPRINTF("transmitter disabled; no TxConfig write val=0x%08x\n", val);
1721 return;
1722 }
1723
1724 DPRINTF("TxConfig write val=0x%08x\n", val);
1725
1726 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
1727
1728 s->TxConfig = val;
1729 }
1730
1731 static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
1732 {
1733 DPRINTF("RTL8139C TxConfig via write(b) val=0x%02x\n", val);
1734
1735 uint32_t tc = s->TxConfig;
1736 tc &= 0xFFFFFF00;
1737 tc |= (val & 0x000000FF);
1738 rtl8139_TxConfig_write(s, tc);
1739 }
1740
1741 static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
1742 {
1743 uint32_t ret = s->TxConfig;
1744
1745 DPRINTF("TxConfig read val=0x%04x\n", ret);
1746
1747 return ret;
1748 }
1749
1750 static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
1751 {
1752 DPRINTF("RxConfig write val=0x%08x\n", val);
1753
1754 /* mask unwritable bits */
1755 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
1756
1757 s->RxConfig = val;
1758
1759 /* reset buffer size and read/write pointers */
1760 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
1761
1762 DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize);
1763 }
1764
1765 static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
1766 {
1767 uint32_t ret = s->RxConfig;
1768
1769 DPRINTF("RxConfig read val=0x%08x\n", ret);
1770
1771 return ret;
1772 }
1773
1774 static void rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size,
1775 int do_interrupt, const uint8_t *dot1q_buf)
1776 {
1777 struct iovec *iov = NULL;
1778 struct iovec vlan_iov[3];
1779
1780 if (!size)
1781 {
1782 DPRINTF("+++ empty ethernet frame\n");
1783 return;
1784 }
1785
1786 if (dot1q_buf && size >= ETHER_ADDR_LEN * 2) {
1787 iov = (struct iovec[3]) {
1788 { .iov_base = buf, .iov_len = ETHER_ADDR_LEN * 2 },
1789 { .iov_base = (void *) dot1q_buf, .iov_len = VLAN_HLEN },
1790 { .iov_base = buf + ETHER_ADDR_LEN * 2,
1791 .iov_len = size - ETHER_ADDR_LEN * 2 },
1792 };
1793
1794 memcpy(vlan_iov, iov, sizeof(vlan_iov));
1795 iov = vlan_iov;
1796 }
1797
1798 if (TxLoopBack == (s->TxConfig & TxLoopBack))
1799 {
1800 size_t buf2_size;
1801 uint8_t *buf2;
1802
1803 if (iov) {
1804 buf2_size = iov_size(iov, 3);
1805 buf2 = g_malloc(buf2_size);
1806 iov_to_buf(iov, 3, 0, buf2, buf2_size);
1807 buf = buf2;
1808 }
1809
1810 DPRINTF("+++ transmit loopback mode\n");
1811 rtl8139_do_receive(qemu_get_queue(s->nic), buf, size, do_interrupt);
1812
1813 if (iov) {
1814 g_free(buf2);
1815 }
1816 }
1817 else
1818 {
1819 if (iov) {
1820 qemu_sendv_packet(qemu_get_queue(s->nic), iov, 3);
1821 } else {
1822 qemu_send_packet(qemu_get_queue(s->nic), buf, size);
1823 }
1824 }
1825 }
1826
1827 static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
1828 {
1829 if (!rtl8139_transmitter_enabled(s))
1830 {
1831 DPRINTF("+++ cannot transmit from descriptor %d: transmitter "
1832 "disabled\n", descriptor);
1833 return 0;
1834 }
1835
1836 if (s->TxStatus[descriptor] & TxHostOwns)
1837 {
1838 DPRINTF("+++ cannot transmit from descriptor %d: owned by host "
1839 "(%08x)\n", descriptor, s->TxStatus[descriptor]);
1840 return 0;
1841 }
1842
1843 DPRINTF("+++ transmitting from descriptor %d\n", descriptor);
1844
1845 PCIDevice *d = PCI_DEVICE(s);
1846 int txsize = s->TxStatus[descriptor] & 0x1fff;
1847 uint8_t txbuffer[0x2000];
1848
1849 DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n",
1850 txsize, s->TxAddr[descriptor]);
1851
1852 pci_dma_read(d, s->TxAddr[descriptor], txbuffer, txsize);
1853
1854 /* Mark descriptor as transferred */
1855 s->TxStatus[descriptor] |= TxHostOwns;
1856 s->TxStatus[descriptor] |= TxStatOK;
1857
1858 rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL);
1859
1860 DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize,
1861 descriptor);
1862
1863 /* update interrupt */
1864 s->IntrStatus |= TxOK;
1865 rtl8139_update_irq(s);
1866
1867 return 1;
1868 }
1869
1870 /* structures and macros for task offloading */
1871 typedef struct ip_header
1872 {
1873 uint8_t ip_ver_len; /* version and header length */
1874 uint8_t ip_tos; /* type of service */
1875 uint16_t ip_len; /* total length */
1876 uint16_t ip_id; /* identification */
1877 uint16_t ip_off; /* fragment offset field */
1878 uint8_t ip_ttl; /* time to live */
1879 uint8_t ip_p; /* protocol */
1880 uint16_t ip_sum; /* checksum */
1881 uint32_t ip_src,ip_dst; /* source and dest address */
1882 } ip_header;
1883
1884 #define IP_HEADER_VERSION_4 4
1885 #define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf)
1886 #define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2)
1887
1888 typedef struct tcp_header
1889 {
1890 uint16_t th_sport; /* source port */
1891 uint16_t th_dport; /* destination port */
1892 uint32_t th_seq; /* sequence number */
1893 uint32_t th_ack; /* acknowledgement number */
1894 uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */
1895 uint16_t th_win; /* window */
1896 uint16_t th_sum; /* checksum */
1897 uint16_t th_urp; /* urgent pointer */
1898 } tcp_header;
1899
1900 typedef struct udp_header
1901 {
1902 uint16_t uh_sport; /* source port */
1903 uint16_t uh_dport; /* destination port */
1904 uint16_t uh_ulen; /* udp length */
1905 uint16_t uh_sum; /* udp checksum */
1906 } udp_header;
1907
1908 typedef struct ip_pseudo_header
1909 {
1910 uint32_t ip_src;
1911 uint32_t ip_dst;
1912 uint8_t zeros;
1913 uint8_t ip_proto;
1914 uint16_t ip_payload;
1915 } ip_pseudo_header;
1916
1917 #define IP_PROTO_TCP 6
1918 #define IP_PROTO_UDP 17
1919
1920 #define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2)
1921 #define TCP_FLAGS_ONLY(flags) ((flags)&0x3f)
1922 #define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
1923
1924 #define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1925
1926 #define TCP_FLAG_FIN 0x01
1927 #define TCP_FLAG_PUSH 0x08
1928
1929 /* produces ones' complement sum of data */
1930 static uint16_t ones_complement_sum(uint8_t *data, size_t len)
1931 {
1932 uint32_t result = 0;
1933
1934 for (; len > 1; data+=2, len-=2)
1935 {
1936 result += *(uint16_t*)data;
1937 }
1938
1939 /* add the remainder byte */
1940 if (len)
1941 {
1942 uint8_t odd[2] = {*data, 0};
1943 result += *(uint16_t*)odd;
1944 }
1945
1946 while (result>>16)
1947 result = (result & 0xffff) + (result >> 16);
1948
1949 return result;
1950 }
1951
1952 static uint16_t ip_checksum(void *data, size_t len)
1953 {
1954 return ~ones_complement_sum((uint8_t*)data, len);
1955 }
1956
1957 static int rtl8139_cplus_transmit_one(RTL8139State *s)
1958 {
1959 if (!rtl8139_transmitter_enabled(s))
1960 {
1961 DPRINTF("+++ C+ mode: transmitter disabled\n");
1962 return 0;
1963 }
1964
1965 if (!rtl8139_cp_transmitter_enabled(s))
1966 {
1967 DPRINTF("+++ C+ mode: C+ transmitter disabled\n");
1968 return 0 ;
1969 }
1970
1971 PCIDevice *d = PCI_DEVICE(s);
1972 int descriptor = s->currCPlusTxDesc;
1973
1974 dma_addr_t cplus_tx_ring_desc = rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
1975
1976 /* Normal priority ring */
1977 cplus_tx_ring_desc += 16 * descriptor;
1978
1979 DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at "
1980 "%08x %08x = 0x"DMA_ADDR_FMT"\n", descriptor, s->TxAddr[1],
1981 s->TxAddr[0], cplus_tx_ring_desc);
1982
1983 uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1984
1985 pci_dma_read(d, cplus_tx_ring_desc, (uint8_t *)&val, 4);
1986 txdw0 = le32_to_cpu(val);
1987 pci_dma_read(d, cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
1988 txdw1 = le32_to_cpu(val);
1989 pci_dma_read(d, cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
1990 txbufLO = le32_to_cpu(val);
1991 pci_dma_read(d, cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
1992 txbufHI = le32_to_cpu(val);
1993
1994 DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor,
1995 txdw0, txdw1, txbufLO, txbufHI);
1996
1997 /* w0 ownership flag */
1998 #define CP_TX_OWN (1<<31)
1999 /* w0 end of ring flag */
2000 #define CP_TX_EOR (1<<30)
2001 /* first segment of received packet flag */
2002 #define CP_TX_FS (1<<29)
2003 /* last segment of received packet flag */
2004 #define CP_TX_LS (1<<28)
2005 /* large send packet flag */
2006 #define CP_TX_LGSEN (1<<27)
2007 /* large send MSS mask, bits 16...25 */
2008 #define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
2009
2010 /* IP checksum offload flag */
2011 #define CP_TX_IPCS (1<<18)
2012 /* UDP checksum offload flag */
2013 #define CP_TX_UDPCS (1<<17)
2014 /* TCP checksum offload flag */
2015 #define CP_TX_TCPCS (1<<16)
2016
2017 /* w0 bits 0...15 : buffer size */
2018 #define CP_TX_BUFFER_SIZE (1<<16)
2019 #define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
2020 /* w1 add tag flag */
2021 #define CP_TX_TAGC (1<<17)
2022 /* w1 bits 0...15 : VLAN tag (big endian) */
2023 #define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
2024 /* w2 low 32bit of Rx buffer ptr */
2025 /* w3 high 32bit of Rx buffer ptr */
2026
2027 /* set after transmission */
2028 /* FIFO underrun flag */
2029 #define CP_TX_STATUS_UNF (1<<25)
2030 /* transmit error summary flag, valid if set any of three below */
2031 #define CP_TX_STATUS_TES (1<<23)
2032 /* out-of-window collision flag */
2033 #define CP_TX_STATUS_OWC (1<<22)
2034 /* link failure flag */
2035 #define CP_TX_STATUS_LNKF (1<<21)
2036 /* excessive collisions flag */
2037 #define CP_TX_STATUS_EXC (1<<20)
2038
2039 if (!(txdw0 & CP_TX_OWN))
2040 {
2041 DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor);
2042 return 0 ;
2043 }
2044
2045 DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor);
2046
2047 if (txdw0 & CP_TX_FS)
2048 {
2049 DPRINTF("+++ C+ Tx mode : descriptor %d is first segment "
2050 "descriptor\n", descriptor);
2051
2052 /* reset internal buffer offset */
2053 s->cplus_txbuffer_offset = 0;
2054 }
2055
2056 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
2057 dma_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
2058
2059 /* make sure we have enough space to assemble the packet */
2060 if (!s->cplus_txbuffer)
2061 {
2062 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
2063 s->cplus_txbuffer = g_malloc(s->cplus_txbuffer_len);
2064 s->cplus_txbuffer_offset = 0;
2065
2066 DPRINTF("+++ C+ mode transmission buffer allocated space %d\n",
2067 s->cplus_txbuffer_len);
2068 }
2069
2070 if (s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
2071 {
2072 /* The spec didn't tell the maximum size, stick to CP_TX_BUFFER_SIZE */
2073 txsize = s->cplus_txbuffer_len - s->cplus_txbuffer_offset;
2074 DPRINTF("+++ C+ mode transmission buffer overrun, truncated descriptor"
2075 "length to %d\n", txsize);
2076 }
2077
2078 /* append more data to the packet */
2079
2080 DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at "
2081 DMA_ADDR_FMT" to offset %d\n", txsize, tx_addr,
2082 s->cplus_txbuffer_offset);
2083
2084 pci_dma_read(d, tx_addr,
2085 s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
2086 s->cplus_txbuffer_offset += txsize;
2087
2088 /* seek to next Rx descriptor */
2089 if (txdw0 & CP_TX_EOR)
2090 {
2091 s->currCPlusTxDesc = 0;
2092 }
2093 else
2094 {
2095 ++s->currCPlusTxDesc;
2096 if (s->currCPlusTxDesc >= 64)
2097 s->currCPlusTxDesc = 0;
2098 }
2099
2100 /* transfer ownership to target */
2101 txdw0 &= ~CP_RX_OWN;
2102
2103 /* reset error indicator bits */
2104 txdw0 &= ~CP_TX_STATUS_UNF;
2105 txdw0 &= ~CP_TX_STATUS_TES;
2106 txdw0 &= ~CP_TX_STATUS_OWC;
2107 txdw0 &= ~CP_TX_STATUS_LNKF;
2108 txdw0 &= ~CP_TX_STATUS_EXC;
2109
2110 /* update ring data */
2111 val = cpu_to_le32(txdw0);
2112 pci_dma_write(d, cplus_tx_ring_desc, (uint8_t *)&val, 4);
2113
2114 /* Now decide if descriptor being processed is holding the last segment of packet */
2115 if (txdw0 & CP_TX_LS)
2116 {
2117 uint8_t dot1q_buffer_space[VLAN_HLEN];
2118 uint16_t *dot1q_buffer;
2119
2120 DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n",
2121 descriptor);
2122
2123 /* can transfer fully assembled packet */
2124
2125 uint8_t *saved_buffer = s->cplus_txbuffer;
2126 int saved_size = s->cplus_txbuffer_offset;
2127 int saved_buffer_len = s->cplus_txbuffer_len;
2128
2129 /* create vlan tag */
2130 if (txdw1 & CP_TX_TAGC) {
2131 /* the vlan tag is in BE byte order in the descriptor
2132 * BE + le_to_cpu() + ~swap()~ = cpu */
2133 DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n",
2134 bswap16(txdw1 & CP_TX_VLAN_TAG_MASK));
2135
2136 dot1q_buffer = (uint16_t *) dot1q_buffer_space;
2137 dot1q_buffer[0] = cpu_to_be16(ETH_P_8021Q);
2138 /* BE + le_to_cpu() + ~cpu_to_le()~ = BE */
2139 dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK);
2140 } else {
2141 dot1q_buffer = NULL;
2142 }
2143
2144 /* reset the card space to protect from recursive call */
2145 s->cplus_txbuffer = NULL;
2146 s->cplus_txbuffer_offset = 0;
2147 s->cplus_txbuffer_len = 0;
2148
2149 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
2150 {
2151 DPRINTF("+++ C+ mode offloaded task checksum\n");
2152
2153 /* Large enough for Ethernet and IP headers? */
2154 if (saved_size < ETH_HLEN + sizeof(ip_header)) {
2155 goto skip_offload;
2156 }
2157
2158 /* ip packet header */
2159 ip_header *ip = NULL;
2160 int hlen = 0;
2161 uint8_t ip_protocol = 0;
2162 uint16_t ip_data_len = 0;
2163
2164 uint8_t *eth_payload_data = NULL;
2165 size_t eth_payload_len = 0;
2166
2167 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
2168 if (proto != ETH_P_IP)
2169 {
2170 goto skip_offload;
2171 }
2172
2173 DPRINTF("+++ C+ mode has IP packet\n");
2174
2175 /* not aligned */
2176 eth_payload_data = saved_buffer + ETH_HLEN;
2177 eth_payload_len = saved_size - ETH_HLEN;
2178
2179 ip = (ip_header*)eth_payload_data;
2180
2181 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
2182 DPRINTF("+++ C+ mode packet has bad IP version %d "
2183 "expected %d\n", IP_HEADER_VERSION(ip),
2184 IP_HEADER_VERSION_4);
2185 goto skip_offload;
2186 }
2187
2188 hlen = IP_HEADER_LENGTH(ip);
2189 if (hlen < sizeof(ip_header) || hlen > eth_payload_len) {
2190 goto skip_offload;
2191 }
2192
2193 ip_protocol = ip->ip_p;
2194
2195 ip_data_len = be16_to_cpu(ip->ip_len);
2196 if (ip_data_len < hlen || ip_data_len > eth_payload_len) {
2197 goto skip_offload;
2198 }
2199 ip_data_len -= hlen;
2200
2201 if (txdw0 & CP_TX_IPCS)
2202 {
2203 DPRINTF("+++ C+ mode need IP checksum\n");
2204
2205 ip->ip_sum = 0;
2206 ip->ip_sum = ip_checksum(ip, hlen);
2207 DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n",
2208 hlen, ip->ip_sum);
2209 }
2210
2211 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
2212 {
2213 /* Large enough for the TCP header? */
2214 if (ip_data_len < sizeof(tcp_header)) {
2215 goto skip_offload;
2216 }
2217
2218 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;
2219
2220 DPRINTF("+++ C+ mode offloaded task TSO MTU=%d IP data %d "
2221 "frame data %d specified MSS=%d\n", ETH_MTU,
2222 ip_data_len, saved_size - ETH_HLEN, large_send_mss);
2223
2224 int tcp_send_offset = 0;
2225 int send_count = 0;
2226
2227 /* maximum IP header length is 60 bytes */
2228 uint8_t saved_ip_header[60];
2229
2230 /* save IP header template; data area is used in tcp checksum calculation */
2231 memcpy(saved_ip_header, eth_payload_data, hlen);
2232
2233 /* a placeholder for checksum calculation routine in tcp case */
2234 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2235 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2236
2237 /* pointer to TCP header */
2238 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen);
2239
2240 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
2241
2242 /* Invalid TCP data offset? */
2243 if (tcp_hlen < sizeof(tcp_header) || tcp_hlen > ip_data_len) {
2244 goto skip_offload;
2245 }
2246
2247 /* ETH_MTU = ip header len + tcp header len + payload */
2248 int tcp_data_len = ip_data_len - tcp_hlen;
2249 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
2250
2251 DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP "
2252 "data len %d TCP chunk size %d\n", ip_data_len,
2253 tcp_hlen, tcp_data_len, tcp_chunk_size);
2254
2255 /* note the cycle below overwrites IP header data,
2256 but restores it from saved_ip_header before sending packet */
2257
2258 int is_last_frame = 0;
2259
2260 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size)
2261 {
2262 uint16_t chunk_size = tcp_chunk_size;
2263
2264 /* check if this is the last frame */
2265 if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
2266 {
2267 is_last_frame = 1;
2268 chunk_size = tcp_data_len - tcp_send_offset;
2269 }
2270
2271 DPRINTF("+++ C+ mode TSO TCP seqno %08x\n",
2272 be32_to_cpu(p_tcp_hdr->th_seq));
2273
2274 /* add 4 TCP pseudoheader fields */
2275 /* copy IP source and destination fields */
2276 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2277
2278 DPRINTF("+++ C+ mode TSO calculating TCP checksum for "
2279 "packet with %d bytes data\n", tcp_hlen +
2280 chunk_size);
2281
2282 if (tcp_send_offset)
2283 {
2284 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
2285 }
2286
2287 /* keep PUSH and FIN flags only for the last frame */
2288 if (!is_last_frame)
2289 {
2290 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN);
2291 }
2292
2293 /* recalculate TCP checksum */
2294 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2295 p_tcpip_hdr->zeros = 0;
2296 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2297 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
2298
2299 p_tcp_hdr->th_sum = 0;
2300
2301 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
2302 DPRINTF("+++ C+ mode TSO TCP checksum %04x\n",
2303 tcp_checksum);
2304
2305 p_tcp_hdr->th_sum = tcp_checksum;
2306
2307 /* restore IP header */
2308 memcpy(eth_payload_data, saved_ip_header, hlen);
2309
2310 /* set IP data length and recalculate IP checksum */
2311 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
2312
2313 /* increment IP id for subsequent frames */
2314 ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id));
2315
2316 ip->ip_sum = 0;
2317 ip->ip_sum = ip_checksum(eth_payload_data, hlen);
2318 DPRINTF("+++ C+ mode TSO IP header len=%d "
2319 "checksum=%04x\n", hlen, ip->ip_sum);
2320
2321 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
2322 DPRINTF("+++ C+ mode TSO transferring packet size "
2323 "%d\n", tso_send_size);
2324 rtl8139_transfer_frame(s, saved_buffer, tso_send_size,
2325 0, (uint8_t *) dot1q_buffer);
2326
2327 /* add transferred count to TCP sequence number */
2328 p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq));
2329 ++send_count;
2330 }
2331
2332 /* Stop sending this frame */
2333 saved_size = 0;
2334 }
2335 else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
2336 {
2337 DPRINTF("+++ C+ mode need TCP or UDP checksum\n");
2338
2339 /* maximum IP header length is 60 bytes */
2340 uint8_t saved_ip_header[60];
2341 memcpy(saved_ip_header, eth_payload_data, hlen);
2342
2343 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2344 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2345
2346 /* add 4 TCP pseudoheader fields */
2347 /* copy IP source and destination fields */
2348 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2349
2350 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
2351 {
2352 DPRINTF("+++ C+ mode calculating TCP checksum for "
2353 "packet with %d bytes data\n", ip_data_len);
2354
2355 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2356 p_tcpip_hdr->zeros = 0;
2357 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2358 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2359
2360 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
2361
2362 p_tcp_hdr->th_sum = 0;
2363
2364 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2365 DPRINTF("+++ C+ mode TCP checksum %04x\n",
2366 tcp_checksum);
2367
2368 p_tcp_hdr->th_sum = tcp_checksum;
2369 }
2370 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
2371 {
2372 DPRINTF("+++ C+ mode calculating UDP checksum for "
2373 "packet with %d bytes data\n", ip_data_len);
2374
2375 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
2376 p_udpip_hdr->zeros = 0;
2377 p_udpip_hdr->ip_proto = IP_PROTO_UDP;
2378 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2379
2380 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
2381
2382 p_udp_hdr->uh_sum = 0;
2383
2384 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2385 DPRINTF("+++ C+ mode UDP checksum %04x\n",
2386 udp_checksum);
2387
2388 p_udp_hdr->uh_sum = udp_checksum;
2389 }
2390
2391 /* restore IP header */
2392 memcpy(eth_payload_data, saved_ip_header, hlen);
2393 }
2394 }
2395
2396 skip_offload:
2397 /* update tally counter */
2398 ++s->tally_counters.TxOk;
2399
2400 DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size);
2401
2402 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1,
2403 (uint8_t *) dot1q_buffer);
2404
2405 /* restore card space if there was no recursion and reset offset */
2406 if (!s->cplus_txbuffer)
2407 {
2408 s->cplus_txbuffer = saved_buffer;
2409 s->cplus_txbuffer_len = saved_buffer_len;
2410 s->cplus_txbuffer_offset = 0;
2411 }
2412 else
2413 {
2414 g_free(saved_buffer);
2415 }
2416 }
2417 else
2418 {
2419 DPRINTF("+++ C+ mode transmission continue to next descriptor\n");
2420 }
2421
2422 return 1;
2423 }
2424
2425 static void rtl8139_cplus_transmit(RTL8139State *s)
2426 {
2427 int txcount = 0;
2428
2429 while (rtl8139_cplus_transmit_one(s))
2430 {
2431 ++txcount;
2432 }
2433
2434 /* Mark transfer completed */
2435 if (!txcount)
2436 {
2437 DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2438 s->currCPlusTxDesc);
2439 }
2440 else
2441 {
2442 /* update interrupt status */
2443 s->IntrStatus |= TxOK;
2444 rtl8139_update_irq(s);
2445 }
2446 }
2447
2448 static void rtl8139_transmit(RTL8139State *s)
2449 {
2450 int descriptor = s->currTxDesc, txcount = 0;
2451
2452 /*while*/
2453 if (rtl8139_transmit_one(s, descriptor))
2454 {
2455 ++s->currTxDesc;
2456 s->currTxDesc %= 4;
2457 ++txcount;
2458 }
2459
2460 /* Mark transfer completed */
2461 if (!txcount)
2462 {
2463 DPRINTF("transmitter queue stalled, current TxDesc = %d\n",
2464 s->currTxDesc);
2465 }
2466 }
2467
2468 static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
2469 {
2470
2471 int descriptor = txRegOffset/4;
2472
2473 /* handle C+ transmit mode register configuration */
2474
2475 if (s->cplus_enabled)
2476 {
2477 DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x "
2478 "descriptor=%d\n", txRegOffset, val, descriptor);
2479
2480 /* handle Dump Tally Counters command */
2481 s->TxStatus[descriptor] = val;
2482
2483 if (descriptor == 0 && (val & 0x8))
2484 {
2485 hwaddr tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
2486
2487 /* dump tally counters to specified memory location */
2488 RTL8139TallyCounters_dma_write(s, tc_addr);
2489
2490 /* mark dump completed */
2491 s->TxStatus[0] &= ~0x8;
2492 }
2493
2494 return;
2495 }
2496
2497 DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n",
2498 txRegOffset, val, descriptor);
2499
2500 /* mask only reserved bits */
2501 val &= ~0xff00c000; /* these bits are reset on write */
2502 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
2503
2504 s->TxStatus[descriptor] = val;
2505
2506 /* attempt to start transmission */
2507 rtl8139_transmit(s);
2508 }
2509
2510 static uint32_t rtl8139_TxStatus_TxAddr_read(RTL8139State *s, uint32_t regs[],
2511 uint32_t base, uint8_t addr,
2512 int size)
2513 {
2514 uint32_t reg = (addr - base) / 4;
2515 uint32_t offset = addr & 0x3;
2516 uint32_t ret = 0;
2517
2518 if (addr & (size - 1)) {
2519 DPRINTF("not implemented read for TxStatus/TxAddr "
2520 "addr=0x%x size=0x%x\n", addr, size);
2521 return ret;
2522 }
2523
2524 switch (size) {
2525 case 1: /* fall through */
2526 case 2: /* fall through */
2527 case 4:
2528 ret = (regs[reg] >> offset * 8) & (((uint64_t)1 << (size * 8)) - 1);
2529 DPRINTF("TxStatus/TxAddr[%d] read addr=0x%x size=0x%x val=0x%08x\n",
2530 reg, addr, size, ret);
2531 break;
2532 default:
2533 DPRINTF("unsupported size 0x%x of TxStatus/TxAddr reading\n", size);
2534 break;
2535 }
2536
2537 return ret;
2538 }
2539
2540 static uint16_t rtl8139_TSAD_read(RTL8139State *s)
2541 {
2542 uint16_t ret = 0;
2543
2544 /* Simulate TSAD, it is read only anyway */
2545
2546 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0)
2547 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0)
2548 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0)
2549 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0)
2550
2551 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
2552 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
2553 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
2554 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
2555
2556 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
2557 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
2558 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
2559 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
2560
2561 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
2562 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
2563 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
2564 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
2565
2566
2567 DPRINTF("TSAD read val=0x%04x\n", ret);
2568
2569 return ret;
2570 }
2571
2572 static uint16_t rtl8139_CSCR_read(RTL8139State *s)
2573 {
2574 uint16_t ret = s->CSCR;
2575
2576 DPRINTF("CSCR read val=0x%04x\n", ret);
2577
2578 return ret;
2579 }
2580
2581 static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
2582 {
2583 DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val);
2584
2585 s->TxAddr[txAddrOffset/4] = val;
2586 }
2587
2588 static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
2589 {
2590 uint32_t ret = s->TxAddr[txAddrOffset/4];
2591
2592 DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret);
2593
2594 return ret;
2595 }
2596
2597 static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
2598 {
2599 DPRINTF("RxBufPtr write val=0x%04x\n", val);
2600
2601 /* this value is off by 16 */
2602 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
2603
2604 /* more buffer space may be available so try to receive */
2605 qemu_flush_queued_packets(qemu_get_queue(s->nic));
2606
2607 DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2608 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
2609 }
2610
2611 static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
2612 {
2613 /* this value is off by 16 */
2614 uint32_t ret = s->RxBufPtr - 0x10;
2615
2616 DPRINTF("RxBufPtr read val=0x%04x\n", ret);
2617
2618 return ret;
2619 }
2620
2621 static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
2622 {
2623 /* this value is NOT off by 16 */
2624 uint32_t ret = s->RxBufAddr;
2625
2626 DPRINTF("RxBufAddr read val=0x%04x\n", ret);
2627
2628 return ret;
2629 }
2630
2631 static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
2632 {
2633 DPRINTF("RxBuf write val=0x%08x\n", val);
2634
2635 s->RxBuf = val;
2636
2637 /* may need to reset rxring here */
2638 }
2639
2640 static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
2641 {
2642 uint32_t ret = s->RxBuf;
2643
2644 DPRINTF("RxBuf read val=0x%08x\n", ret);
2645
2646 return ret;
2647 }
2648
2649 static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
2650 {
2651 DPRINTF("IntrMask write(w) val=0x%04x\n", val);
2652
2653 /* mask unwritable bits */
2654 val = SET_MASKED(val, 0x1e00, s->IntrMask);
2655
2656 s->IntrMask = val;
2657
2658 rtl8139_update_irq(s);
2659
2660 }
2661
2662 static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
2663 {
2664 uint32_t ret = s->IntrMask;
2665
2666 DPRINTF("IntrMask read(w) val=0x%04x\n", ret);
2667
2668 return ret;
2669 }
2670
2671 static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
2672 {
2673 DPRINTF("IntrStatus write(w) val=0x%04x\n", val);
2674
2675 #if 0
2676
2677 /* writing to ISR has no effect */
2678
2679 return;
2680
2681 #else
2682 uint16_t newStatus = s->IntrStatus & ~val;
2683
2684 /* mask unwritable bits */
2685 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
2686
2687 /* writing 1 to interrupt status register bit clears it */
2688 s->IntrStatus = 0;
2689 rtl8139_update_irq(s);
2690
2691 s->IntrStatus = newStatus;
2692 rtl8139_set_next_tctr_time(s);
2693 rtl8139_update_irq(s);
2694
2695 #endif
2696 }
2697
2698 static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
2699 {
2700 uint32_t ret = s->IntrStatus;
2701
2702 DPRINTF("IntrStatus read(w) val=0x%04x\n", ret);
2703
2704 #if 0
2705
2706 /* reading ISR clears all interrupts */
2707 s->IntrStatus = 0;
2708
2709 rtl8139_update_irq(s);
2710
2711 #endif
2712
2713 return ret;
2714 }
2715
2716 static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
2717 {
2718 DPRINTF("MultiIntr write(w) val=0x%04x\n", val);
2719
2720 /* mask unwritable bits */
2721 val = SET_MASKED(val, 0xf000, s->MultiIntr);
2722
2723 s->MultiIntr = val;
2724 }
2725
2726 static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
2727 {
2728 uint32_t ret = s->MultiIntr;
2729
2730 DPRINTF("MultiIntr read(w) val=0x%04x\n", ret);
2731
2732 return ret;
2733 }
2734
2735 static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
2736 {
2737 RTL8139State *s = opaque;
2738
2739 switch (addr)
2740 {
2741 case MAC0 ... MAC0+4:
2742 s->phys[addr - MAC0] = val;
2743 break;
2744 case MAC0+5:
2745 s->phys[addr - MAC0] = val;
2746 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->phys);
2747 break;
2748 case MAC0+6 ... MAC0+7:
2749 /* reserved */
2750 break;
2751 case MAR0 ... MAR0+7:
2752 s->mult[addr - MAR0] = val;
2753 break;
2754 case ChipCmd:
2755 rtl8139_ChipCmd_write(s, val);
2756 break;
2757 case Cfg9346:
2758 rtl8139_Cfg9346_write(s, val);
2759 break;
2760 case TxConfig: /* windows driver sometimes writes using byte-lenth call */
2761 rtl8139_TxConfig_writeb(s, val);
2762 break;
2763 case Config0:
2764 rtl8139_Config0_write(s, val);
2765 break;
2766 case Config1:
2767 rtl8139_Config1_write(s, val);
2768 break;
2769 case Config3:
2770 rtl8139_Config3_write(s, val);
2771 break;
2772 case Config4:
2773 rtl8139_Config4_write(s, val);
2774 break;
2775 case Config5:
2776 rtl8139_Config5_write(s, val);
2777 break;
2778 case MediaStatus:
2779 /* ignore */
2780 DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n",
2781 val);
2782 break;
2783
2784 case HltClk:
2785 DPRINTF("HltClk write val=0x%08x\n", val);
2786 if (val == 'R')
2787 {
2788 s->clock_enabled = 1;
2789 }
2790 else if (val == 'H')
2791 {
2792 s->clock_enabled = 0;
2793 }
2794 break;
2795
2796 case TxThresh:
2797 DPRINTF("C+ TxThresh write(b) val=0x%02x\n", val);
2798 s->TxThresh = val;
2799 break;
2800
2801 case TxPoll:
2802 DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val);
2803 if (val & (1 << 7))
2804 {
2805 DPRINTF("C+ TxPoll high priority transmission (not "
2806 "implemented)\n");
2807 //rtl8139_cplus_transmit(s);
2808 }
2809 if (val & (1 << 6))
2810 {
2811 DPRINTF("C+ TxPoll normal priority transmission\n");
2812 rtl8139_cplus_transmit(s);
2813 }
2814
2815 break;
2816
2817 default:
2818 DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr,
2819 val);
2820 break;
2821 }
2822 }
2823
2824 static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
2825 {
2826 RTL8139State *s = opaque;
2827
2828 switch (addr)
2829 {
2830 case IntrMask:
2831 rtl8139_IntrMask_write(s, val);
2832 break;
2833
2834 case IntrStatus:
2835 rtl8139_IntrStatus_write(s, val);
2836 break;
2837
2838 case MultiIntr:
2839 rtl8139_MultiIntr_write(s, val);
2840 break;
2841
2842 case RxBufPtr:
2843 rtl8139_RxBufPtr_write(s, val);
2844 break;
2845
2846 case BasicModeCtrl:
2847 rtl8139_BasicModeCtrl_write(s, val);
2848 break;
2849 case BasicModeStatus:
2850 rtl8139_BasicModeStatus_write(s, val);
2851 break;
2852 case NWayAdvert:
2853 DPRINTF("NWayAdvert write(w) val=0x%04x\n", val);
2854 s->NWayAdvert = val;
2855 break;
2856 case NWayLPAR:
2857 DPRINTF("forbidden NWayLPAR write(w) val=0x%04x\n", val);
2858 break;
2859 case NWayExpansion:
2860 DPRINTF("NWayExpansion write(w) val=0x%04x\n", val);
2861 s->NWayExpansion = val;
2862 break;
2863
2864 case CpCmd:
2865 rtl8139_CpCmd_write(s, val);
2866 break;
2867
2868 case IntrMitigate:
2869 rtl8139_IntrMitigate_write(s, val);
2870 break;
2871
2872 default:
2873 DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n",
2874 addr, val);
2875
2876 rtl8139_io_writeb(opaque, addr, val & 0xff);
2877 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2878 break;
2879 }
2880 }
2881
2882 static void rtl8139_set_next_tctr_time(RTL8139State *s)
2883 {
2884 const uint64_t ns_per_period =
2885 muldiv64(0x100000000LL, get_ticks_per_sec(), PCI_FREQUENCY);
2886
2887 DPRINTF("entered rtl8139_set_next_tctr_time\n");
2888
2889 /* This function is called at least once per period, so it is a good
2890 * place to update the timer base.
2891 *
2892 * After one iteration of this loop the value in the Timer register does
2893 * not change, but the device model is counting up by 2^32 ticks (approx.
2894 * 130 seconds).
2895 */
2896 while (s->TCTR_base + ns_per_period <= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) {
2897 s->TCTR_base += ns_per_period;
2898 }
2899
2900 if (!s->TimerInt) {
2901 timer_del(s->timer);
2902 } else {
2903 uint64_t delta = muldiv64(s->TimerInt, get_ticks_per_sec(), PCI_FREQUENCY);
2904 if (s->TCTR_base + delta <= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) {
2905 delta += ns_per_period;
2906 }
2907 timer_mod(s->timer, s->TCTR_base + delta);
2908 }
2909 }
2910
2911 static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
2912 {
2913 RTL8139State *s = opaque;
2914
2915 switch (addr)
2916 {
2917 case RxMissed:
2918 DPRINTF("RxMissed clearing on write\n");
2919 s->RxMissed = 0;
2920 break;
2921
2922 case TxConfig:
2923 rtl8139_TxConfig_write(s, val);
2924 break;
2925
2926 case RxConfig:
2927 rtl8139_RxConfig_write(s, val);
2928 break;
2929
2930 case TxStatus0 ... TxStatus0+4*4-1:
2931 rtl8139_TxStatus_write(s, addr-TxStatus0, val);
2932 break;
2933
2934 case TxAddr0 ... TxAddr0+4*4-1:
2935 rtl8139_TxAddr_write(s, addr-TxAddr0, val);
2936 break;
2937
2938 case RxBuf:
2939 rtl8139_RxBuf_write(s, val);
2940 break;
2941
2942 case RxRingAddrLO:
2943 DPRINTF("C+ RxRing low bits write val=0x%08x\n", val);
2944 s->RxRingAddrLO = val;
2945 break;
2946
2947 case RxRingAddrHI:
2948 DPRINTF("C+ RxRing high bits write val=0x%08x\n", val);
2949 s->RxRingAddrHI = val;
2950 break;
2951
2952 case Timer:
2953 DPRINTF("TCTR Timer reset on write\n");
2954 s->TCTR_base = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
2955 rtl8139_set_next_tctr_time(s);
2956 break;
2957
2958 case FlashReg:
2959 DPRINTF("FlashReg TimerInt write val=0x%08x\n", val);
2960 if (s->TimerInt != val) {
2961 s->TimerInt = val;
2962 rtl8139_set_next_tctr_time(s);
2963 }
2964 break;
2965
2966 default:
2967 DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n",
2968 addr, val);
2969 rtl8139_io_writeb(opaque, addr, val & 0xff);
2970 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2971 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2972 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2973 break;
2974 }
2975 }
2976
2977 static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
2978 {
2979 RTL8139State *s = opaque;
2980 int ret;
2981
2982 switch (addr)
2983 {
2984 case MAC0 ... MAC0+5:
2985 ret = s->phys[addr - MAC0];
2986 break;
2987 case MAC0+6 ... MAC0+7:
2988 ret = 0;
2989 break;
2990 case MAR0 ... MAR0+7:
2991 ret = s->mult[addr - MAR0];
2992 break;
2993 case TxStatus0 ... TxStatus0+4*4-1:
2994 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0,
2995 addr, 1);
2996 break;
2997 case ChipCmd:
2998 ret = rtl8139_ChipCmd_read(s);
2999 break;
3000 case Cfg9346:
3001 ret = rtl8139_Cfg9346_read(s);
3002 break;
3003 case Config0:
3004 ret = rtl8139_Config0_read(s);
3005 break;
3006 case Config1:
3007 ret = rtl8139_Config1_read(s);
3008 break;
3009 case Config3:
3010 ret = rtl8139_Config3_read(s);
3011 break;
3012 case Config4:
3013 ret = rtl8139_Config4_read(s);
3014 break;
3015 case Config5:
3016 ret = rtl8139_Config5_read(s);
3017 break;
3018
3019 case MediaStatus:
3020 /* The LinkDown bit of MediaStatus is inverse with link status */
3021 ret = 0xd0 | (~s->BasicModeStatus & 0x04);
3022 DPRINTF("MediaStatus read 0x%x\n", ret);
3023 break;
3024
3025 case HltClk:
3026 ret = s->clock_enabled;
3027 DPRINTF("HltClk read 0x%x\n", ret);
3028 break;
3029
3030 case PCIRevisionID:
3031 ret = RTL8139_PCI_REVID;
3032 DPRINTF("PCI Revision ID read 0x%x\n", ret);
3033 break;
3034
3035 case TxThresh:
3036 ret = s->TxThresh;
3037 DPRINTF("C+ TxThresh read(b) val=0x%02x\n", ret);
3038 break;
3039
3040 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
3041 ret = s->TxConfig >> 24;
3042 DPRINTF("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret);
3043 break;
3044
3045 default:
3046 DPRINTF("not implemented read(b) addr=0x%x\n", addr);
3047 ret = 0;
3048 break;
3049 }
3050
3051 return ret;
3052 }
3053
3054 static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
3055 {
3056 RTL8139State *s = opaque;
3057 uint32_t ret;
3058
3059 switch (addr)
3060 {
3061 case TxAddr0 ... TxAddr0+4*4-1:
3062 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxAddr, TxAddr0, addr, 2);
3063 break;
3064 case IntrMask:
3065 ret = rtl8139_IntrMask_read(s);
3066 break;
3067
3068 case IntrStatus:
3069 ret = rtl8139_IntrStatus_read(s);
3070 break;
3071
3072 case MultiIntr:
3073 ret = rtl8139_MultiIntr_read(s);
3074 break;
3075
3076 case RxBufPtr:
3077 ret = rtl8139_RxBufPtr_read(s);
3078 break;
3079
3080 case RxBufAddr:
3081 ret = rtl8139_RxBufAddr_read(s);
3082 break;
3083
3084 case BasicModeCtrl:
3085 ret = rtl8139_BasicModeCtrl_read(s);
3086 break;
3087 case BasicModeStatus:
3088 ret = rtl8139_BasicModeStatus_read(s);
3089 break;
3090 case NWayAdvert:
3091 ret = s->NWayAdvert;
3092 DPRINTF("NWayAdvert read(w) val=0x%04x\n", ret);
3093 break;
3094 case NWayLPAR:
3095 ret = s->NWayLPAR;
3096 DPRINTF("NWayLPAR read(w) val=0x%04x\n", ret);
3097 break;
3098 case NWayExpansion:
3099 ret = s->NWayExpansion;
3100 DPRINTF("NWayExpansion read(w) val=0x%04x\n", ret);
3101 break;
3102
3103 case CpCmd:
3104 ret = rtl8139_CpCmd_read(s);
3105 break;
3106
3107 case IntrMitigate:
3108 ret = rtl8139_IntrMitigate_read(s);
3109 break;
3110
3111 case TxSummary:
3112 ret = rtl8139_TSAD_read(s);
3113 break;
3114
3115 case CSCR:
3116 ret = rtl8139_CSCR_read(s);
3117 break;
3118
3119 default:
3120 DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr);
3121
3122 ret = rtl8139_io_readb(opaque, addr);
3123 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3124
3125 DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret);
3126 break;
3127 }
3128
3129 return ret;
3130 }
3131
3132 static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
3133 {
3134 RTL8139State *s = opaque;
3135 uint32_t ret;
3136
3137 switch (addr)
3138 {
3139 case RxMissed:
3140 ret = s->RxMissed;
3141
3142 DPRINTF("RxMissed read val=0x%08x\n", ret);
3143 break;
3144
3145 case TxConfig:
3146 ret = rtl8139_TxConfig_read(s);
3147 break;
3148
3149 case RxConfig:
3150 ret = rtl8139_RxConfig_read(s);
3151 break;
3152
3153 case TxStatus0 ... TxStatus0+4*4-1:
3154 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0,
3155 addr, 4);
3156 break;
3157
3158 case TxAddr0 ... TxAddr0+4*4-1:
3159 ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
3160 break;
3161
3162 case RxBuf:
3163 ret = rtl8139_RxBuf_read(s);
3164 break;
3165
3166 case RxRingAddrLO:
3167 ret = s->RxRingAddrLO;
3168 DPRINTF("C+ RxRing low bits read val=0x%08x\n", ret);
3169 break;
3170
3171 case RxRingAddrHI:
3172 ret = s->RxRingAddrHI;
3173 DPRINTF("C+ RxRing high bits read val=0x%08x\n", ret);
3174 break;
3175
3176 case Timer:
3177 ret = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->TCTR_base,
3178 PCI_FREQUENCY, get_ticks_per_sec());
3179 DPRINTF("TCTR Timer read val=0x%08x\n", ret);
3180 break;
3181
3182 case FlashReg:
3183 ret = s->TimerInt;
3184 DPRINTF("FlashReg TimerInt read val=0x%08x\n", ret);
3185 break;
3186
3187 default:
3188 DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr);
3189
3190 ret = rtl8139_io_readb(opaque, addr);
3191 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3192 ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
3193 ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
3194
3195 DPRINTF("read(l) addr=0x%x val=%08x\n", addr, ret);
3196 break;
3197 }
3198
3199 return ret;
3200 }
3201
3202 /* */
3203
3204 static void rtl8139_mmio_writeb(void *opaque, hwaddr addr, uint32_t val)
3205 {
3206 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3207 }
3208
3209 static void rtl8139_mmio_writew(void *opaque, hwaddr addr, uint32_t val)
3210 {
3211 rtl8139_io_writew(opaque, addr & 0xFF, val);
3212 }
3213
3214 static void rtl8139_mmio_writel(void *opaque, hwaddr addr, uint32_t val)
3215 {
3216 rtl8139_io_writel(opaque, addr & 0xFF, val);
3217 }
3218
3219 static uint32_t rtl8139_mmio_readb(void *opaque, hwaddr addr)
3220 {
3221 return rtl8139_io_readb(opaque, addr & 0xFF);
3222 }
3223
3224 static uint32_t rtl8139_mmio_readw(void *opaque, hwaddr addr)
3225 {
3226 uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
3227 return val;
3228 }
3229
3230 static uint32_t rtl8139_mmio_readl(void *opaque, hwaddr addr)
3231 {
3232 uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
3233 return val;
3234 }
3235
3236 static int rtl8139_post_load(void *opaque, int version_id)
3237 {
3238 RTL8139State* s = opaque;
3239 rtl8139_set_next_tctr_time(s);
3240 if (version_id < 4) {
3241 s->cplus_enabled = s->CpCmd != 0;
3242 }
3243
3244 /* nc.link_down can't be migrated, so infer link_down according
3245 * to link status bit in BasicModeStatus */
3246 qemu_get_queue(s->nic)->link_down = (s->BasicModeStatus & 0x04) == 0;
3247
3248 return 0;
3249 }
3250
3251 static bool rtl8139_hotplug_ready_needed(void *opaque)
3252 {
3253 return qdev_machine_modified();
3254 }
3255
3256 static const VMStateDescription vmstate_rtl8139_hotplug_ready ={
3257 .name = "rtl8139/hotplug_ready",
3258 .version_id = 1,
3259 .minimum_version_id = 1,
3260 .needed = rtl8139_hotplug_ready_needed,
3261 .fields = (VMStateField[]) {
3262 VMSTATE_END_OF_LIST()
3263 }
3264 };
3265
3266 static void rtl8139_pre_save(void *opaque)
3267 {
3268 RTL8139State* s = opaque;
3269 int64_t current_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
3270
3271 /* for migration to older versions */
3272 s->TCTR = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
3273 get_ticks_per_sec());
3274 s->rtl8139_mmio_io_addr_dummy = 0;
3275 }
3276
3277 static const VMStateDescription vmstate_rtl8139 = {
3278 .name = "rtl8139",
3279 .version_id = 4,
3280 .minimum_version_id = 3,
3281 .post_load = rtl8139_post_load,
3282 .pre_save = rtl8139_pre_save,
3283 .fields = (VMStateField[]) {
3284 VMSTATE_PCI_DEVICE(parent_obj, RTL8139State),
3285 VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),
3286 VMSTATE_BUFFER(mult, RTL8139State),
3287 VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),
3288 VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4),
3289
3290 VMSTATE_UINT32(RxBuf, RTL8139State),
3291 VMSTATE_UINT32(RxBufferSize, RTL8139State),
3292 VMSTATE_UINT32(RxBufPtr, RTL8139State),
3293 VMSTATE_UINT32(RxBufAddr, RTL8139State),
3294
3295 VMSTATE_UINT16(IntrStatus, RTL8139State),
3296 VMSTATE_UINT16(IntrMask, RTL8139State),
3297
3298 VMSTATE_UINT32(TxConfig, RTL8139State),
3299 VMSTATE_UINT32(RxConfig, RTL8139State),
3300 VMSTATE_UINT32(RxMissed, RTL8139State),
3301 VMSTATE_UINT16(CSCR, RTL8139State),
3302
3303 VMSTATE_UINT8(Cfg9346, RTL8139State),
3304 VMSTATE_UINT8(Config0, RTL8139State),
3305 VMSTATE_UINT8(Config1, RTL8139State),
3306 VMSTATE_UINT8(Config3, RTL8139State),
3307 VMSTATE_UINT8(Config4, RTL8139State),
3308 VMSTATE_UINT8(Config5, RTL8139State),
3309
3310 VMSTATE_UINT8(clock_enabled, RTL8139State),
3311 VMSTATE_UINT8(bChipCmdState, RTL8139State),
3312
3313 VMSTATE_UINT16(MultiIntr, RTL8139State),
3314
3315 VMSTATE_UINT16(BasicModeCtrl, RTL8139State),
3316 VMSTATE_UINT16(BasicModeStatus, RTL8139State),
3317 VMSTATE_UINT16(NWayAdvert, RTL8139State),
3318 VMSTATE_UINT16(NWayLPAR, RTL8139State),
3319 VMSTATE_UINT16(NWayExpansion, RTL8139State),
3320
3321 VMSTATE_UINT16(CpCmd, RTL8139State),
3322 VMSTATE_UINT8(TxThresh, RTL8139State),
3323
3324 VMSTATE_UNUSED(4),
3325 VMSTATE_MACADDR(conf.macaddr, RTL8139State),
3326 VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State),
3327
3328 VMSTATE_UINT32(currTxDesc, RTL8139State),
3329 VMSTATE_UINT32(currCPlusRxDesc, RTL8139State),
3330 VMSTATE_UINT32(currCPlusTxDesc, RTL8139State),
3331 VMSTATE_UINT32(RxRingAddrLO, RTL8139State),
3332 VMSTATE_UINT32(RxRingAddrHI, RTL8139State),
3333
3334 VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE),
3335 VMSTATE_INT32(eeprom.mode, RTL8139State),
3336 VMSTATE_UINT32(eeprom.tick, RTL8139State),
3337 VMSTATE_UINT8(eeprom.address, RTL8139State),
3338 VMSTATE_UINT16(eeprom.input, RTL8139State),
3339 VMSTATE_UINT16(eeprom.output, RTL8139State),
3340
3341 VMSTATE_UINT8(eeprom.eecs, RTL8139State),
3342 VMSTATE_UINT8(eeprom.eesk, RTL8139State),
3343 VMSTATE_UINT8(eeprom.eedi, RTL8139State),
3344 VMSTATE_UINT8(eeprom.eedo, RTL8139State),
3345
3346 VMSTATE_UINT32(TCTR, RTL8139State),
3347 VMSTATE_UINT32(TimerInt, RTL8139State),
3348 VMSTATE_INT64(TCTR_base, RTL8139State),
3349
3350 VMSTATE_STRUCT(tally_counters, RTL8139State, 0,
3351 vmstate_tally_counters, RTL8139TallyCounters),
3352
3353 VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4),
3354 VMSTATE_END_OF_LIST()
3355 },
3356 .subsections = (const VMStateDescription*[]) {
3357 &vmstate_rtl8139_hotplug_ready,
3358 NULL
3359 }
3360 };
3361
3362 /***********************************************************/
3363 /* PCI RTL8139 definitions */
3364
3365 static void rtl8139_ioport_write(void *opaque, hwaddr addr,
3366 uint64_t val, unsigned size)
3367 {
3368 switch (size) {
3369 case 1:
3370 rtl8139_io_writeb(opaque, addr, val);
3371 break;
3372 case 2:
3373 rtl8139_io_writew(opaque, addr, val);
3374 break;
3375 case 4:
3376 rtl8139_io_writel(opaque, addr, val);
3377 break;
3378 }
3379 }
3380
3381 static uint64_t rtl8139_ioport_read(void *opaque, hwaddr addr,
3382 unsigned size)
3383 {
3384 switch (size) {
3385 case 1:
3386 return rtl8139_io_readb(opaque, addr);
3387 case 2:
3388 return rtl8139_io_readw(opaque, addr);
3389 case 4:
3390 return rtl8139_io_readl(opaque, addr);
3391 }
3392
3393 return -1;
3394 }
3395
3396 static const MemoryRegionOps rtl8139_io_ops = {
3397 .read = rtl8139_ioport_read,
3398 .write = rtl8139_ioport_write,
3399 .impl = {
3400 .min_access_size = 1,
3401 .max_access_size = 4,
3402 },
3403 .endianness = DEVICE_LITTLE_ENDIAN,
3404 };
3405
3406 static const MemoryRegionOps rtl8139_mmio_ops = {
3407 .old_mmio = {
3408 .read = {
3409 rtl8139_mmio_readb,
3410 rtl8139_mmio_readw,
3411 rtl8139_mmio_readl,
3412 },
3413 .write = {
3414 rtl8139_mmio_writeb,
3415 rtl8139_mmio_writew,
3416 rtl8139_mmio_writel,
3417 },
3418 },
3419 .endianness = DEVICE_LITTLE_ENDIAN,
3420 };
3421
3422 static void rtl8139_timer(void *opaque)
3423 {
3424 RTL8139State *s = opaque;
3425
3426 if (!s->clock_enabled)
3427 {
3428 DPRINTF(">>> timer: clock is not running\n");
3429 return;
3430 }
3431
3432 s->IntrStatus |= PCSTimeout;
3433 rtl8139_update_irq(s);