hw/arm/bcm2836: Only provide "enabled-cpus" property to multicore SoCs
[qemu.git] / hw / nvram / fw_cfg.c
1 /*
2 * QEMU Firmware configuration device emulation
3 *
4 * Copyright (c) 2008 Gleb Natapov
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu-common.h"
27 #include "sysemu/sysemu.h"
28 #include "sysemu/dma.h"
29 #include "sysemu/reset.h"
30 #include "hw/boards.h"
31 #include "hw/nvram/fw_cfg.h"
32 #include "hw/qdev-properties.h"
33 #include "hw/sysbus.h"
34 #include "migration/qemu-file-types.h"
35 #include "migration/vmstate.h"
36 #include "trace.h"
37 #include "qemu/error-report.h"
38 #include "qemu/option.h"
39 #include "qemu/config-file.h"
40 #include "qemu/cutils.h"
41 #include "qapi/error.h"
42 #include "hw/acpi/aml-build.h"
43
44 #define FW_CFG_FILE_SLOTS_DFLT 0x20
45
46 /* FW_CFG_VERSION bits */
47 #define FW_CFG_VERSION 0x01
48 #define FW_CFG_VERSION_DMA 0x02
49
50 /* FW_CFG_DMA_CONTROL bits */
51 #define FW_CFG_DMA_CTL_ERROR 0x01
52 #define FW_CFG_DMA_CTL_READ 0x02
53 #define FW_CFG_DMA_CTL_SKIP 0x04
54 #define FW_CFG_DMA_CTL_SELECT 0x08
55 #define FW_CFG_DMA_CTL_WRITE 0x10
56
57 #define FW_CFG_DMA_SIGNATURE 0x51454d5520434647ULL /* "QEMU CFG" */
58
59 struct FWCfgEntry {
60 uint32_t len;
61 bool allow_write;
62 uint8_t *data;
63 void *callback_opaque;
64 FWCfgCallback select_cb;
65 FWCfgWriteCallback write_cb;
66 };
67
68 /**
69 * key_name:
70 *
71 * @key: The uint16 selector key.
72 *
73 * Returns: The stringified name if the selector refers to a well-known
74 * numerically defined item, or NULL on key lookup failure.
75 */
76 static const char *key_name(uint16_t key)
77 {
78 static const char *fw_cfg_wellknown_keys[FW_CFG_FILE_FIRST] = {
79 [FW_CFG_SIGNATURE] = "signature",
80 [FW_CFG_ID] = "id",
81 [FW_CFG_UUID] = "uuid",
82 [FW_CFG_RAM_SIZE] = "ram_size",
83 [FW_CFG_NOGRAPHIC] = "nographic",
84 [FW_CFG_NB_CPUS] = "nb_cpus",
85 [FW_CFG_MACHINE_ID] = "machine_id",
86 [FW_CFG_KERNEL_ADDR] = "kernel_addr",
87 [FW_CFG_KERNEL_SIZE] = "kernel_size",
88 [FW_CFG_KERNEL_CMDLINE] = "kernel_cmdline",
89 [FW_CFG_INITRD_ADDR] = "initrd_addr",
90 [FW_CFG_INITRD_SIZE] = "initdr_size",
91 [FW_CFG_BOOT_DEVICE] = "boot_device",
92 [FW_CFG_NUMA] = "numa",
93 [FW_CFG_BOOT_MENU] = "boot_menu",
94 [FW_CFG_MAX_CPUS] = "max_cpus",
95 [FW_CFG_KERNEL_ENTRY] = "kernel_entry",
96 [FW_CFG_KERNEL_DATA] = "kernel_data",
97 [FW_CFG_INITRD_DATA] = "initrd_data",
98 [FW_CFG_CMDLINE_ADDR] = "cmdline_addr",
99 [FW_CFG_CMDLINE_SIZE] = "cmdline_size",
100 [FW_CFG_CMDLINE_DATA] = "cmdline_data",
101 [FW_CFG_SETUP_ADDR] = "setup_addr",
102 [FW_CFG_SETUP_SIZE] = "setup_size",
103 [FW_CFG_SETUP_DATA] = "setup_data",
104 [FW_CFG_FILE_DIR] = "file_dir",
105 };
106
107 if (key & FW_CFG_ARCH_LOCAL) {
108 return fw_cfg_arch_key_name(key);
109 }
110 if (key < FW_CFG_FILE_FIRST) {
111 return fw_cfg_wellknown_keys[key];
112 }
113
114 return NULL;
115 }
116
117 static inline const char *trace_key_name(uint16_t key)
118 {
119 const char *name = key_name(key);
120
121 return name ? name : "unknown";
122 }
123
124 #define JPG_FILE 0
125 #define BMP_FILE 1
126
127 static char *read_splashfile(char *filename, gsize *file_sizep,
128 int *file_typep)
129 {
130 GError *err = NULL;
131 gchar *content;
132 int file_type;
133 unsigned int filehead;
134 int bmp_bpp;
135
136 if (!g_file_get_contents(filename, &content, file_sizep, &err)) {
137 error_report("failed to read splash file '%s': %s",
138 filename, err->message);
139 g_error_free(err);
140 return NULL;
141 }
142
143 /* check file size */
144 if (*file_sizep < 30) {
145 goto error;
146 }
147
148 /* check magic ID */
149 filehead = lduw_le_p(content);
150 if (filehead == 0xd8ff) {
151 file_type = JPG_FILE;
152 } else if (filehead == 0x4d42) {
153 file_type = BMP_FILE;
154 } else {
155 goto error;
156 }
157
158 /* check BMP bpp */
159 if (file_type == BMP_FILE) {
160 bmp_bpp = lduw_le_p(&content[28]);
161 if (bmp_bpp != 24) {
162 goto error;
163 }
164 }
165
166 /* return values */
167 *file_typep = file_type;
168
169 return content;
170
171 error:
172 error_report("splash file '%s' format not recognized; must be JPEG "
173 "or 24 bit BMP", filename);
174 g_free(content);
175 return NULL;
176 }
177
178 static void fw_cfg_bootsplash(FWCfgState *s)
179 {
180 const char *boot_splash_filename = NULL;
181 const char *boot_splash_time = NULL;
182 char *filename, *file_data;
183 gsize file_size;
184 int file_type;
185
186 /* get user configuration */
187 QemuOptsList *plist = qemu_find_opts("boot-opts");
188 QemuOpts *opts = QTAILQ_FIRST(&plist->head);
189 boot_splash_filename = qemu_opt_get(opts, "splash");
190 boot_splash_time = qemu_opt_get(opts, "splash-time");
191
192 /* insert splash time if user configurated */
193 if (boot_splash_time) {
194 int64_t bst_val = qemu_opt_get_number(opts, "splash-time", -1);
195 uint16_t bst_le16;
196
197 /* validate the input */
198 if (bst_val < 0 || bst_val > 0xffff) {
199 error_report("splash-time is invalid,"
200 "it should be a value between 0 and 65535");
201 exit(1);
202 }
203 /* use little endian format */
204 bst_le16 = cpu_to_le16(bst_val);
205 fw_cfg_add_file(s, "etc/boot-menu-wait",
206 g_memdup(&bst_le16, sizeof bst_le16), sizeof bst_le16);
207 }
208
209 /* insert splash file if user configurated */
210 if (boot_splash_filename) {
211 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, boot_splash_filename);
212 if (filename == NULL) {
213 error_report("failed to find file '%s'", boot_splash_filename);
214 return;
215 }
216
217 /* loading file data */
218 file_data = read_splashfile(filename, &file_size, &file_type);
219 if (file_data == NULL) {
220 g_free(filename);
221 return;
222 }
223 g_free(boot_splash_filedata);
224 boot_splash_filedata = (uint8_t *)file_data;
225
226 /* insert data */
227 if (file_type == JPG_FILE) {
228 fw_cfg_add_file(s, "bootsplash.jpg",
229 boot_splash_filedata, file_size);
230 } else {
231 fw_cfg_add_file(s, "bootsplash.bmp",
232 boot_splash_filedata, file_size);
233 }
234 g_free(filename);
235 }
236 }
237
238 static void fw_cfg_reboot(FWCfgState *s)
239 {
240 const char *reboot_timeout = NULL;
241 uint64_t rt_val = -1;
242 uint32_t rt_le32;
243
244 /* get user configuration */
245 QemuOptsList *plist = qemu_find_opts("boot-opts");
246 QemuOpts *opts = QTAILQ_FIRST(&plist->head);
247 reboot_timeout = qemu_opt_get(opts, "reboot-timeout");
248
249 if (reboot_timeout) {
250 rt_val = qemu_opt_get_number(opts, "reboot-timeout", -1);
251
252 /* validate the input */
253 if (rt_val > 0xffff && rt_val != (uint64_t)-1) {
254 error_report("reboot timeout is invalid,"
255 "it should be a value between -1 and 65535");
256 exit(1);
257 }
258 }
259
260 rt_le32 = cpu_to_le32(rt_val);
261 fw_cfg_add_file(s, "etc/boot-fail-wait", g_memdup(&rt_le32, 4), 4);
262 }
263
264 static void fw_cfg_write(FWCfgState *s, uint8_t value)
265 {
266 /* nothing, write support removed in QEMU v2.4+ */
267 }
268
269 static inline uint16_t fw_cfg_file_slots(const FWCfgState *s)
270 {
271 return s->file_slots;
272 }
273
274 /* Note: this function returns an exclusive limit. */
275 static inline uint32_t fw_cfg_max_entry(const FWCfgState *s)
276 {
277 return FW_CFG_FILE_FIRST + fw_cfg_file_slots(s);
278 }
279
280 static int fw_cfg_select(FWCfgState *s, uint16_t key)
281 {
282 int arch, ret;
283 FWCfgEntry *e;
284
285 s->cur_offset = 0;
286 if ((key & FW_CFG_ENTRY_MASK) >= fw_cfg_max_entry(s)) {
287 s->cur_entry = FW_CFG_INVALID;
288 ret = 0;
289 } else {
290 s->cur_entry = key;
291 ret = 1;
292 /* entry successfully selected, now run callback if present */
293 arch = !!(key & FW_CFG_ARCH_LOCAL);
294 e = &s->entries[arch][key & FW_CFG_ENTRY_MASK];
295 if (e->select_cb) {
296 e->select_cb(e->callback_opaque);
297 }
298 }
299
300 trace_fw_cfg_select(s, key, trace_key_name(key), ret);
301 return ret;
302 }
303
304 static uint64_t fw_cfg_data_read(void *opaque, hwaddr addr, unsigned size)
305 {
306 FWCfgState *s = opaque;
307 int arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL);
308 FWCfgEntry *e = (s->cur_entry == FW_CFG_INVALID) ? NULL :
309 &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK];
310 uint64_t value = 0;
311
312 assert(size > 0 && size <= sizeof(value));
313 if (s->cur_entry != FW_CFG_INVALID && e->data && s->cur_offset < e->len) {
314 /* The least significant 'size' bytes of the return value are
315 * expected to contain a string preserving portion of the item
316 * data, padded with zeros on the right in case we run out early.
317 * In technical terms, we're composing the host-endian representation
318 * of the big endian interpretation of the fw_cfg string.
319 */
320 do {
321 value = (value << 8) | e->data[s->cur_offset++];
322 } while (--size && s->cur_offset < e->len);
323 /* If size is still not zero, we *did* run out early, so continue
324 * left-shifting, to add the appropriate number of padding zeros
325 * on the right.
326 */
327 value <<= 8 * size;
328 }
329
330 trace_fw_cfg_read(s, value);
331 return value;
332 }
333
334 static void fw_cfg_data_mem_write(void *opaque, hwaddr addr,
335 uint64_t value, unsigned size)
336 {
337 FWCfgState *s = opaque;
338 unsigned i = size;
339
340 do {
341 fw_cfg_write(s, value >> (8 * --i));
342 } while (i);
343 }
344
345 static void fw_cfg_dma_transfer(FWCfgState *s)
346 {
347 dma_addr_t len;
348 FWCfgDmaAccess dma;
349 int arch;
350 FWCfgEntry *e;
351 int read = 0, write = 0;
352 dma_addr_t dma_addr;
353
354 /* Reset the address before the next access */
355 dma_addr = s->dma_addr;
356 s->dma_addr = 0;
357
358 if (dma_memory_read(s->dma_as, dma_addr, &dma, sizeof(dma))) {
359 stl_be_dma(s->dma_as, dma_addr + offsetof(FWCfgDmaAccess, control),
360 FW_CFG_DMA_CTL_ERROR);
361 return;
362 }
363
364 dma.address = be64_to_cpu(dma.address);
365 dma.length = be32_to_cpu(dma.length);
366 dma.control = be32_to_cpu(dma.control);
367
368 if (dma.control & FW_CFG_DMA_CTL_SELECT) {
369 fw_cfg_select(s, dma.control >> 16);
370 }
371
372 arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL);
373 e = (s->cur_entry == FW_CFG_INVALID) ? NULL :
374 &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK];
375
376 if (dma.control & FW_CFG_DMA_CTL_READ) {
377 read = 1;
378 write = 0;
379 } else if (dma.control & FW_CFG_DMA_CTL_WRITE) {
380 read = 0;
381 write = 1;
382 } else if (dma.control & FW_CFG_DMA_CTL_SKIP) {
383 read = 0;
384 write = 0;
385 } else {
386 dma.length = 0;
387 }
388
389 dma.control = 0;
390
391 while (dma.length > 0 && !(dma.control & FW_CFG_DMA_CTL_ERROR)) {
392 if (s->cur_entry == FW_CFG_INVALID || !e->data ||
393 s->cur_offset >= e->len) {
394 len = dma.length;
395
396 /* If the access is not a read access, it will be a skip access,
397 * tested before.
398 */
399 if (read) {
400 if (dma_memory_set(s->dma_as, dma.address, 0, len)) {
401 dma.control |= FW_CFG_DMA_CTL_ERROR;
402 }
403 }
404 if (write) {
405 dma.control |= FW_CFG_DMA_CTL_ERROR;
406 }
407 } else {
408 if (dma.length <= (e->len - s->cur_offset)) {
409 len = dma.length;
410 } else {
411 len = (e->len - s->cur_offset);
412 }
413
414 /* If the access is not a read access, it will be a skip access,
415 * tested before.
416 */
417 if (read) {
418 if (dma_memory_write(s->dma_as, dma.address,
419 &e->data[s->cur_offset], len)) {
420 dma.control |= FW_CFG_DMA_CTL_ERROR;
421 }
422 }
423 if (write) {
424 if (!e->allow_write ||
425 len != dma.length ||
426 dma_memory_read(s->dma_as, dma.address,
427 &e->data[s->cur_offset], len)) {
428 dma.control |= FW_CFG_DMA_CTL_ERROR;
429 } else if (e->write_cb) {
430 e->write_cb(e->callback_opaque, s->cur_offset, len);
431 }
432 }
433
434 s->cur_offset += len;
435 }
436
437 dma.address += len;
438 dma.length -= len;
439
440 }
441
442 stl_be_dma(s->dma_as, dma_addr + offsetof(FWCfgDmaAccess, control),
443 dma.control);
444
445 trace_fw_cfg_read(s, 0);
446 }
447
448 static uint64_t fw_cfg_dma_mem_read(void *opaque, hwaddr addr,
449 unsigned size)
450 {
451 /* Return a signature value (and handle various read sizes) */
452 return extract64(FW_CFG_DMA_SIGNATURE, (8 - addr - size) * 8, size * 8);
453 }
454
455 static void fw_cfg_dma_mem_write(void *opaque, hwaddr addr,
456 uint64_t value, unsigned size)
457 {
458 FWCfgState *s = opaque;
459
460 if (size == 4) {
461 if (addr == 0) {
462 /* FWCfgDmaAccess high address */
463 s->dma_addr = value << 32;
464 } else if (addr == 4) {
465 /* FWCfgDmaAccess low address */
466 s->dma_addr |= value;
467 fw_cfg_dma_transfer(s);
468 }
469 } else if (size == 8 && addr == 0) {
470 s->dma_addr = value;
471 fw_cfg_dma_transfer(s);
472 }
473 }
474
475 static bool fw_cfg_dma_mem_valid(void *opaque, hwaddr addr,
476 unsigned size, bool is_write,
477 MemTxAttrs attrs)
478 {
479 return !is_write || ((size == 4 && (addr == 0 || addr == 4)) ||
480 (size == 8 && addr == 0));
481 }
482
483 static bool fw_cfg_data_mem_valid(void *opaque, hwaddr addr,
484 unsigned size, bool is_write,
485 MemTxAttrs attrs)
486 {
487 return addr == 0;
488 }
489
490 static uint64_t fw_cfg_ctl_mem_read(void *opaque, hwaddr addr, unsigned size)
491 {
492 return 0;
493 }
494
495 static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr,
496 uint64_t value, unsigned size)
497 {
498 fw_cfg_select(opaque, (uint16_t)value);
499 }
500
501 static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr,
502 unsigned size, bool is_write,
503 MemTxAttrs attrs)
504 {
505 return is_write && size == 2;
506 }
507
508 static void fw_cfg_comb_write(void *opaque, hwaddr addr,
509 uint64_t value, unsigned size)
510 {
511 switch (size) {
512 case 1:
513 fw_cfg_write(opaque, (uint8_t)value);
514 break;
515 case 2:
516 fw_cfg_select(opaque, (uint16_t)value);
517 break;
518 }
519 }
520
521 static bool fw_cfg_comb_valid(void *opaque, hwaddr addr,
522 unsigned size, bool is_write,
523 MemTxAttrs attrs)
524 {
525 return (size == 1) || (is_write && size == 2);
526 }
527
528 static const MemoryRegionOps fw_cfg_ctl_mem_ops = {
529 .read = fw_cfg_ctl_mem_read,
530 .write = fw_cfg_ctl_mem_write,
531 .endianness = DEVICE_BIG_ENDIAN,
532 .valid.accepts = fw_cfg_ctl_mem_valid,
533 };
534
535 static const MemoryRegionOps fw_cfg_data_mem_ops = {
536 .read = fw_cfg_data_read,
537 .write = fw_cfg_data_mem_write,
538 .endianness = DEVICE_BIG_ENDIAN,
539 .valid = {
540 .min_access_size = 1,
541 .max_access_size = 1,
542 .accepts = fw_cfg_data_mem_valid,
543 },
544 };
545
546 static const MemoryRegionOps fw_cfg_comb_mem_ops = {
547 .read = fw_cfg_data_read,
548 .write = fw_cfg_comb_write,
549 .endianness = DEVICE_LITTLE_ENDIAN,
550 .valid.accepts = fw_cfg_comb_valid,
551 };
552
553 static const MemoryRegionOps fw_cfg_dma_mem_ops = {
554 .read = fw_cfg_dma_mem_read,
555 .write = fw_cfg_dma_mem_write,
556 .endianness = DEVICE_BIG_ENDIAN,
557 .valid.accepts = fw_cfg_dma_mem_valid,
558 .valid.max_access_size = 8,
559 .impl.max_access_size = 8,
560 };
561
562 static void fw_cfg_reset(DeviceState *d)
563 {
564 FWCfgState *s = FW_CFG(d);
565
566 /* we never register a read callback for FW_CFG_SIGNATURE */
567 fw_cfg_select(s, FW_CFG_SIGNATURE);
568 }
569
570 /* Save restore 32 bit int as uint16_t
571 This is a Big hack, but it is how the old state did it.
572 Or we broke compatibility in the state, or we can't use struct tm
573 */
574
575 static int get_uint32_as_uint16(QEMUFile *f, void *pv, size_t size,
576 const VMStateField *field)
577 {
578 uint32_t *v = pv;
579 *v = qemu_get_be16(f);
580 return 0;
581 }
582
583 static int put_unused(QEMUFile *f, void *pv, size_t size,
584 const VMStateField *field, QJSON *vmdesc)
585 {
586 fprintf(stderr, "uint32_as_uint16 is only used for backward compatibility.\n");
587 fprintf(stderr, "This functions shouldn't be called.\n");
588
589 return 0;
590 }
591
592 static const VMStateInfo vmstate_hack_uint32_as_uint16 = {
593 .name = "int32_as_uint16",
594 .get = get_uint32_as_uint16,
595 .put = put_unused,
596 };
597
598 #define VMSTATE_UINT16_HACK(_f, _s, _t) \
599 VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint32_as_uint16, uint32_t)
600
601
602 static bool is_version_1(void *opaque, int version_id)
603 {
604 return version_id == 1;
605 }
606
607 bool fw_cfg_dma_enabled(void *opaque)
608 {
609 FWCfgState *s = opaque;
610
611 return s->dma_enabled;
612 }
613
614 static bool fw_cfg_acpi_mr_restore(void *opaque)
615 {
616 FWCfgState *s = opaque;
617 bool mr_aligned;
618
619 mr_aligned = QEMU_IS_ALIGNED(s->table_mr_size, qemu_real_host_page_size) &&
620 QEMU_IS_ALIGNED(s->linker_mr_size, qemu_real_host_page_size) &&
621 QEMU_IS_ALIGNED(s->rsdp_mr_size, qemu_real_host_page_size);
622 return s->acpi_mr_restore && !mr_aligned;
623 }
624
625 static void fw_cfg_update_mr(FWCfgState *s, uint16_t key, size_t size)
626 {
627 MemoryRegion *mr;
628 ram_addr_t offset;
629 int arch = !!(key & FW_CFG_ARCH_LOCAL);
630 void *ptr;
631
632 key &= FW_CFG_ENTRY_MASK;
633 assert(key < fw_cfg_max_entry(s));
634
635 ptr = s->entries[arch][key].data;
636 mr = memory_region_from_host(ptr, &offset);
637
638 memory_region_ram_resize(mr, size, &error_abort);
639 }
640
641 static int fw_cfg_acpi_mr_restore_post_load(void *opaque, int version_id)
642 {
643 FWCfgState *s = opaque;
644 int i, index;
645
646 assert(s->files);
647
648 index = be32_to_cpu(s->files->count);
649
650 for (i = 0; i < index; i++) {
651 if (!strcmp(s->files->f[i].name, ACPI_BUILD_TABLE_FILE)) {
652 fw_cfg_update_mr(s, FW_CFG_FILE_FIRST + i, s->table_mr_size);
653 } else if (!strcmp(s->files->f[i].name, ACPI_BUILD_LOADER_FILE)) {
654 fw_cfg_update_mr(s, FW_CFG_FILE_FIRST + i, s->linker_mr_size);
655 } else if (!strcmp(s->files->f[i].name, ACPI_BUILD_RSDP_FILE)) {
656 fw_cfg_update_mr(s, FW_CFG_FILE_FIRST + i, s->rsdp_mr_size);
657 }
658 }
659
660 return 0;
661 }
662
663 static const VMStateDescription vmstate_fw_cfg_dma = {
664 .name = "fw_cfg/dma",
665 .needed = fw_cfg_dma_enabled,
666 .fields = (VMStateField[]) {
667 VMSTATE_UINT64(dma_addr, FWCfgState),
668 VMSTATE_END_OF_LIST()
669 },
670 };
671
672 static const VMStateDescription vmstate_fw_cfg_acpi_mr = {
673 .name = "fw_cfg/acpi_mr",
674 .version_id = 1,
675 .minimum_version_id = 1,
676 .needed = fw_cfg_acpi_mr_restore,
677 .post_load = fw_cfg_acpi_mr_restore_post_load,
678 .fields = (VMStateField[]) {
679 VMSTATE_UINT64(table_mr_size, FWCfgState),
680 VMSTATE_UINT64(linker_mr_size, FWCfgState),
681 VMSTATE_UINT64(rsdp_mr_size, FWCfgState),
682 VMSTATE_END_OF_LIST()
683 },
684 };
685
686 static const VMStateDescription vmstate_fw_cfg = {
687 .name = "fw_cfg",
688 .version_id = 2,
689 .minimum_version_id = 1,
690 .fields = (VMStateField[]) {
691 VMSTATE_UINT16(cur_entry, FWCfgState),
692 VMSTATE_UINT16_HACK(cur_offset, FWCfgState, is_version_1),
693 VMSTATE_UINT32_V(cur_offset, FWCfgState, 2),
694 VMSTATE_END_OF_LIST()
695 },
696 .subsections = (const VMStateDescription*[]) {
697 &vmstate_fw_cfg_dma,
698 &vmstate_fw_cfg_acpi_mr,
699 NULL,
700 }
701 };
702
703 static void fw_cfg_add_bytes_callback(FWCfgState *s, uint16_t key,
704 FWCfgCallback select_cb,
705 FWCfgWriteCallback write_cb,
706 void *callback_opaque,
707 void *data, size_t len,
708 bool read_only)
709 {
710 int arch = !!(key & FW_CFG_ARCH_LOCAL);
711
712 key &= FW_CFG_ENTRY_MASK;
713
714 assert(key < fw_cfg_max_entry(s) && len < UINT32_MAX);
715 assert(s->entries[arch][key].data == NULL); /* avoid key conflict */
716
717 s->entries[arch][key].data = data;
718 s->entries[arch][key].len = (uint32_t)len;
719 s->entries[arch][key].select_cb = select_cb;
720 s->entries[arch][key].write_cb = write_cb;
721 s->entries[arch][key].callback_opaque = callback_opaque;
722 s->entries[arch][key].allow_write = !read_only;
723 }
724
725 static void *fw_cfg_modify_bytes_read(FWCfgState *s, uint16_t key,
726 void *data, size_t len)
727 {
728 void *ptr;
729 int arch = !!(key & FW_CFG_ARCH_LOCAL);
730
731 key &= FW_CFG_ENTRY_MASK;
732
733 assert(key < fw_cfg_max_entry(s) && len < UINT32_MAX);
734
735 /* return the old data to the function caller, avoid memory leak */
736 ptr = s->entries[arch][key].data;
737 s->entries[arch][key].data = data;
738 s->entries[arch][key].len = len;
739 s->entries[arch][key].callback_opaque = NULL;
740 s->entries[arch][key].allow_write = false;
741
742 return ptr;
743 }
744
745 void fw_cfg_add_bytes(FWCfgState *s, uint16_t key, void *data, size_t len)
746 {
747 trace_fw_cfg_add_bytes(key, trace_key_name(key), len);
748 fw_cfg_add_bytes_callback(s, key, NULL, NULL, NULL, data, len, true);
749 }
750
751 void fw_cfg_add_string(FWCfgState *s, uint16_t key, const char *value)
752 {
753 size_t sz = strlen(value) + 1;
754
755 trace_fw_cfg_add_string(key, trace_key_name(key), value);
756 fw_cfg_add_bytes(s, key, g_memdup(value, sz), sz);
757 }
758
759 void fw_cfg_modify_string(FWCfgState *s, uint16_t key, const char *value)
760 {
761 size_t sz = strlen(value) + 1;
762 char *old;
763
764 old = fw_cfg_modify_bytes_read(s, key, g_memdup(value, sz), sz);
765 g_free(old);
766 }
767
768 void fw_cfg_add_i16(FWCfgState *s, uint16_t key, uint16_t value)
769 {
770 uint16_t *copy;
771
772 copy = g_malloc(sizeof(value));
773 *copy = cpu_to_le16(value);
774 trace_fw_cfg_add_i16(key, trace_key_name(key), value);
775 fw_cfg_add_bytes(s, key, copy, sizeof(value));
776 }
777
778 void fw_cfg_modify_i16(FWCfgState *s, uint16_t key, uint16_t value)
779 {
780 uint16_t *copy, *old;
781
782 copy = g_malloc(sizeof(value));
783 *copy = cpu_to_le16(value);
784 old = fw_cfg_modify_bytes_read(s, key, copy, sizeof(value));
785 g_free(old);
786 }
787
788 void fw_cfg_add_i32(FWCfgState *s, uint16_t key, uint32_t value)
789 {
790 uint32_t *copy;
791
792 copy = g_malloc(sizeof(value));
793 *copy = cpu_to_le32(value);
794 trace_fw_cfg_add_i32(key, trace_key_name(key), value);
795 fw_cfg_add_bytes(s, key, copy, sizeof(value));
796 }
797
798 void fw_cfg_modify_i32(FWCfgState *s, uint16_t key, uint32_t value)
799 {
800 uint32_t *copy, *old;
801
802 copy = g_malloc(sizeof(value));
803 *copy = cpu_to_le32(value);
804 old = fw_cfg_modify_bytes_read(s, key, copy, sizeof(value));
805 g_free(old);
806 }
807
808 void fw_cfg_add_i64(FWCfgState *s, uint16_t key, uint64_t value)
809 {
810 uint64_t *copy;
811
812 copy = g_malloc(sizeof(value));
813 *copy = cpu_to_le64(value);
814 trace_fw_cfg_add_i64(key, trace_key_name(key), value);
815 fw_cfg_add_bytes(s, key, copy, sizeof(value));
816 }
817
818 void fw_cfg_modify_i64(FWCfgState *s, uint16_t key, uint64_t value)
819 {
820 uint64_t *copy, *old;
821
822 copy = g_malloc(sizeof(value));
823 *copy = cpu_to_le64(value);
824 old = fw_cfg_modify_bytes_read(s, key, copy, sizeof(value));
825 g_free(old);
826 }
827
828 void fw_cfg_set_order_override(FWCfgState *s, int order)
829 {
830 assert(s->fw_cfg_order_override == 0);
831 s->fw_cfg_order_override = order;
832 }
833
834 void fw_cfg_reset_order_override(FWCfgState *s)
835 {
836 assert(s->fw_cfg_order_override != 0);
837 s->fw_cfg_order_override = 0;
838 }
839
840 /*
841 * This is the legacy order list. For legacy systems, files are in
842 * the fw_cfg in the order defined below, by the "order" value. Note
843 * that some entries (VGA ROMs, NIC option ROMS, etc.) go into a
844 * specific area, but there may be more than one and they occur in the
845 * order that the user specifies them on the command line. Those are
846 * handled in a special manner, using the order override above.
847 *
848 * For non-legacy, the files are sorted by filename to avoid this kind
849 * of complexity in the future.
850 *
851 * This is only for x86, other arches don't implement versioning so
852 * they won't set legacy mode.
853 */
854 static struct {
855 const char *name;
856 int order;
857 } fw_cfg_order[] = {
858 { "etc/boot-menu-wait", 10 },
859 { "bootsplash.jpg", 11 },
860 { "bootsplash.bmp", 12 },
861 { "etc/boot-fail-wait", 15 },
862 { "etc/smbios/smbios-tables", 20 },
863 { "etc/smbios/smbios-anchor", 30 },
864 { "etc/e820", 40 },
865 { "etc/reserved-memory-end", 50 },
866 { "genroms/kvmvapic.bin", 55 },
867 { "genroms/linuxboot.bin", 60 },
868 { }, /* VGA ROMs from pc_vga_init come here, 70. */
869 { }, /* NIC option ROMs from pc_nic_init come here, 80. */
870 { "etc/system-states", 90 },
871 { }, /* User ROMs come here, 100. */
872 { }, /* Device FW comes here, 110. */
873 { "etc/extra-pci-roots", 120 },
874 { "etc/acpi/tables", 130 },
875 { "etc/table-loader", 140 },
876 { "etc/tpm/log", 150 },
877 { "etc/acpi/rsdp", 160 },
878 { "bootorder", 170 },
879
880 #define FW_CFG_ORDER_OVERRIDE_LAST 200
881 };
882
883 /*
884 * Any sub-page size update to these table MRs will be lost during migration,
885 * as we use aligned size in ram_load_precopy() -> qemu_ram_resize() path.
886 * In order to avoid the inconsistency in sizes save them seperately and
887 * migrate over in vmstate post_load().
888 */
889 static void fw_cfg_acpi_mr_save(FWCfgState *s, const char *filename, size_t len)
890 {
891 if (!strcmp(filename, ACPI_BUILD_TABLE_FILE)) {
892 s->table_mr_size = len;
893 } else if (!strcmp(filename, ACPI_BUILD_LOADER_FILE)) {
894 s->linker_mr_size = len;
895 } else if (!strcmp(filename, ACPI_BUILD_RSDP_FILE)) {
896 s->rsdp_mr_size = len;
897 }
898 }
899
900 static int get_fw_cfg_order(FWCfgState *s, const char *name)
901 {
902 int i;
903
904 if (s->fw_cfg_order_override > 0) {
905 return s->fw_cfg_order_override;
906 }
907
908 for (i = 0; i < ARRAY_SIZE(fw_cfg_order); i++) {
909 if (fw_cfg_order[i].name == NULL) {
910 continue;
911 }
912
913 if (strcmp(name, fw_cfg_order[i].name) == 0) {
914 return fw_cfg_order[i].order;
915 }
916 }
917
918 /* Stick unknown stuff at the end. */
919 warn_report("Unknown firmware file in legacy mode: %s", name);
920 return FW_CFG_ORDER_OVERRIDE_LAST;
921 }
922
923 void fw_cfg_add_file_callback(FWCfgState *s, const char *filename,
924 FWCfgCallback select_cb,
925 FWCfgWriteCallback write_cb,
926 void *callback_opaque,
927 void *data, size_t len, bool read_only)
928 {
929 int i, index, count;
930 size_t dsize;
931 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
932 int order = 0;
933
934 if (!s->files) {
935 dsize = sizeof(uint32_t) + sizeof(FWCfgFile) * fw_cfg_file_slots(s);
936 s->files = g_malloc0(dsize);
937 fw_cfg_add_bytes(s, FW_CFG_FILE_DIR, s->files, dsize);
938 }
939
940 count = be32_to_cpu(s->files->count);
941 assert(count < fw_cfg_file_slots(s));
942
943 /* Find the insertion point. */
944 if (mc->legacy_fw_cfg_order) {
945 /*
946 * Sort by order. For files with the same order, we keep them
947 * in the sequence in which they were added.
948 */
949 order = get_fw_cfg_order(s, filename);
950 for (index = count;
951 index > 0 && order < s->entry_order[index - 1];
952 index--);
953 } else {
954 /* Sort by file name. */
955 for (index = count;
956 index > 0 && strcmp(filename, s->files->f[index - 1].name) < 0;
957 index--);
958 }
959
960 /*
961 * Move all the entries from the index point and after down one
962 * to create a slot for the new entry. Because calculations are
963 * being done with the index, make it so that "i" is the current
964 * index and "i - 1" is the one being copied from, thus the
965 * unusual start and end in the for statement.
966 */
967 for (i = count; i > index; i--) {
968 s->files->f[i] = s->files->f[i - 1];
969 s->files->f[i].select = cpu_to_be16(FW_CFG_FILE_FIRST + i);
970 s->entries[0][FW_CFG_FILE_FIRST + i] =
971 s->entries[0][FW_CFG_FILE_FIRST + i - 1];
972 s->entry_order[i] = s->entry_order[i - 1];
973 }
974
975 memset(&s->files->f[index], 0, sizeof(FWCfgFile));
976 memset(&s->entries[0][FW_CFG_FILE_FIRST + index], 0, sizeof(FWCfgEntry));
977
978 pstrcpy(s->files->f[index].name, sizeof(s->files->f[index].name), filename);
979 for (i = 0; i <= count; i++) {
980 if (i != index &&
981 strcmp(s->files->f[index].name, s->files->f[i].name) == 0) {
982 error_report("duplicate fw_cfg file name: %s",
983 s->files->f[index].name);
984 exit(1);
985 }
986 }
987
988 fw_cfg_add_bytes_callback(s, FW_CFG_FILE_FIRST + index,
989 select_cb, write_cb,
990 callback_opaque, data, len,
991 read_only);
992
993 s->files->f[index].size = cpu_to_be32(len);
994 s->files->f[index].select = cpu_to_be16(FW_CFG_FILE_FIRST + index);
995 s->entry_order[index] = order;
996 trace_fw_cfg_add_file(s, index, s->files->f[index].name, len);
997
998 s->files->count = cpu_to_be32(count+1);
999 fw_cfg_acpi_mr_save(s, filename, len);
1000 }
1001
1002 void fw_cfg_add_file(FWCfgState *s, const char *filename,
1003 void *data, size_t len)
1004 {
1005 fw_cfg_add_file_callback(s, filename, NULL, NULL, NULL, data, len, true);
1006 }
1007
1008 void *fw_cfg_modify_file(FWCfgState *s, const char *filename,
1009 void *data, size_t len)
1010 {
1011 int i, index;
1012 void *ptr = NULL;
1013
1014 assert(s->files);
1015
1016 index = be32_to_cpu(s->files->count);
1017
1018 for (i = 0; i < index; i++) {
1019 if (strcmp(filename, s->files->f[i].name) == 0) {
1020 ptr = fw_cfg_modify_bytes_read(s, FW_CFG_FILE_FIRST + i,
1021 data, len);
1022 s->files->f[i].size = cpu_to_be32(len);
1023 fw_cfg_acpi_mr_save(s, filename, len);
1024 return ptr;
1025 }
1026 }
1027
1028 assert(index < fw_cfg_file_slots(s));
1029
1030 /* add new one */
1031 fw_cfg_add_file_callback(s, filename, NULL, NULL, NULL, data, len, true);
1032 return NULL;
1033 }
1034
1035 bool fw_cfg_add_from_generator(FWCfgState *s, const char *filename,
1036 const char *gen_id, Error **errp)
1037 {
1038 FWCfgDataGeneratorClass *klass;
1039 GByteArray *array;
1040 Object *obj;
1041 gsize size;
1042
1043 obj = object_resolve_path_component(object_get_objects_root(), gen_id);
1044 if (!obj) {
1045 error_setg(errp, "Cannot find object ID '%s'", gen_id);
1046 return false;
1047 }
1048 if (!object_dynamic_cast(obj, TYPE_FW_CFG_DATA_GENERATOR_INTERFACE)) {
1049 error_setg(errp, "Object ID '%s' is not a '%s' subclass",
1050 gen_id, TYPE_FW_CFG_DATA_GENERATOR_INTERFACE);
1051 return false;
1052 }
1053 klass = FW_CFG_DATA_GENERATOR_GET_CLASS(obj);
1054 array = klass->get_data(obj, errp);
1055 if (!array) {
1056 return false;
1057 }
1058 size = array->len;
1059 fw_cfg_add_file(s, filename, g_byte_array_free(array, FALSE), size);
1060
1061 return true;
1062 }
1063
1064 static void fw_cfg_machine_reset(void *opaque)
1065 {
1066 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
1067 FWCfgState *s = opaque;
1068 void *ptr;
1069 size_t len;
1070 char *buf;
1071
1072 buf = get_boot_devices_list(&len);
1073 ptr = fw_cfg_modify_file(s, "bootorder", (uint8_t *)buf, len);
1074 g_free(ptr);
1075
1076 if (!mc->legacy_fw_cfg_order) {
1077 buf = get_boot_devices_lchs_list(&len);
1078 ptr = fw_cfg_modify_file(s, "bios-geometry", (uint8_t *)buf, len);
1079 g_free(ptr);
1080 }
1081 }
1082
1083 static void fw_cfg_machine_ready(struct Notifier *n, void *data)
1084 {
1085 FWCfgState *s = container_of(n, FWCfgState, machine_ready);
1086 qemu_register_reset(fw_cfg_machine_reset, s);
1087 }
1088
1089 static Property fw_cfg_properties[] = {
1090 DEFINE_PROP_BOOL("acpi-mr-restore", FWCfgState, acpi_mr_restore, true),
1091 DEFINE_PROP_END_OF_LIST(),
1092 };
1093
1094 static void fw_cfg_common_realize(DeviceState *dev, Error **errp)
1095 {
1096 FWCfgState *s = FW_CFG(dev);
1097 MachineState *machine = MACHINE(qdev_get_machine());
1098 uint32_t version = FW_CFG_VERSION;
1099
1100 if (!fw_cfg_find()) {
1101 error_setg(errp, "at most one %s device is permitted", TYPE_FW_CFG);
1102 return;
1103 }
1104
1105 fw_cfg_add_bytes(s, FW_CFG_SIGNATURE, (char *)"QEMU", 4);
1106 fw_cfg_add_bytes(s, FW_CFG_UUID, &qemu_uuid, 16);
1107 fw_cfg_add_i16(s, FW_CFG_NOGRAPHIC, (uint16_t)!machine->enable_graphics);
1108 fw_cfg_add_i16(s, FW_CFG_BOOT_MENU, (uint16_t)boot_menu);
1109 fw_cfg_bootsplash(s);
1110 fw_cfg_reboot(s);
1111
1112 if (s->dma_enabled) {
1113 version |= FW_CFG_VERSION_DMA;
1114 }
1115
1116 fw_cfg_add_i32(s, FW_CFG_ID, version);
1117
1118 s->machine_ready.notify = fw_cfg_machine_ready;
1119 qemu_add_machine_init_done_notifier(&s->machine_ready);
1120 }
1121
1122 FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, uint32_t dma_iobase,
1123 AddressSpace *dma_as)
1124 {
1125 DeviceState *dev;
1126 SysBusDevice *sbd;
1127 FWCfgIoState *ios;
1128 FWCfgState *s;
1129 bool dma_requested = dma_iobase && dma_as;
1130
1131 dev = qdev_new(TYPE_FW_CFG_IO);
1132 if (!dma_requested) {
1133 qdev_prop_set_bit(dev, "dma_enabled", false);
1134 }
1135
1136 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
1137 OBJECT(dev));
1138
1139 sbd = SYS_BUS_DEVICE(dev);
1140 sysbus_realize_and_unref(sbd, &error_fatal);
1141 ios = FW_CFG_IO(dev);
1142 sysbus_add_io(sbd, iobase, &ios->comb_iomem);
1143
1144 s = FW_CFG(dev);
1145
1146 if (s->dma_enabled) {
1147 /* 64 bits for the address field */
1148 s->dma_as = dma_as;
1149 s->dma_addr = 0;
1150 sysbus_add_io(sbd, dma_iobase, &s->dma_iomem);
1151 }
1152
1153 return s;
1154 }
1155
1156 FWCfgState *fw_cfg_init_io(uint32_t iobase)
1157 {
1158 return fw_cfg_init_io_dma(iobase, 0, NULL);
1159 }
1160
1161 FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr,
1162 hwaddr data_addr, uint32_t data_width,
1163 hwaddr dma_addr, AddressSpace *dma_as)
1164 {
1165 DeviceState *dev;
1166 SysBusDevice *sbd;
1167 FWCfgState *s;
1168 bool dma_requested = dma_addr && dma_as;
1169
1170 dev = qdev_new(TYPE_FW_CFG_MEM);
1171 qdev_prop_set_uint32(dev, "data_width", data_width);
1172 if (!dma_requested) {
1173 qdev_prop_set_bit(dev, "dma_enabled", false);
1174 }
1175
1176 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
1177 OBJECT(dev));
1178
1179 sbd = SYS_BUS_DEVICE(dev);
1180 sysbus_realize_and_unref(sbd, &error_fatal);
1181 sysbus_mmio_map(sbd, 0, ctl_addr);
1182 sysbus_mmio_map(sbd, 1, data_addr);
1183
1184 s = FW_CFG(dev);
1185
1186 if (s->dma_enabled) {
1187 s->dma_as = dma_as;
1188 s->dma_addr = 0;
1189 sysbus_mmio_map(sbd, 2, dma_addr);
1190 }
1191
1192 return s;
1193 }
1194
1195 FWCfgState *fw_cfg_init_mem(hwaddr ctl_addr, hwaddr data_addr)
1196 {
1197 return fw_cfg_init_mem_wide(ctl_addr, data_addr,
1198 fw_cfg_data_mem_ops.valid.max_access_size,
1199 0, NULL);
1200 }
1201
1202
1203 FWCfgState *fw_cfg_find(void)
1204 {
1205 /* Returns NULL unless there is exactly one fw_cfg device */
1206 return FW_CFG(object_resolve_path_type("", TYPE_FW_CFG, NULL));
1207 }
1208
1209
1210 static void fw_cfg_class_init(ObjectClass *klass, void *data)
1211 {
1212 DeviceClass *dc = DEVICE_CLASS(klass);
1213
1214 dc->reset = fw_cfg_reset;
1215 dc->vmsd = &vmstate_fw_cfg;
1216
1217 device_class_set_props(dc, fw_cfg_properties);
1218 }
1219
1220 static const TypeInfo fw_cfg_info = {
1221 .name = TYPE_FW_CFG,
1222 .parent = TYPE_SYS_BUS_DEVICE,
1223 .abstract = true,
1224 .instance_size = sizeof(FWCfgState),
1225 .class_init = fw_cfg_class_init,
1226 };
1227
1228 static void fw_cfg_file_slots_allocate(FWCfgState *s, Error **errp)
1229 {
1230 uint16_t file_slots_max;
1231
1232 if (fw_cfg_file_slots(s) < FW_CFG_FILE_SLOTS_MIN) {
1233 error_setg(errp, "\"file_slots\" must be at least 0x%x",
1234 FW_CFG_FILE_SLOTS_MIN);
1235 return;
1236 }
1237
1238 /* (UINT16_MAX & FW_CFG_ENTRY_MASK) is the highest inclusive selector value
1239 * that we permit. The actual (exclusive) value coming from the
1240 * configuration is (FW_CFG_FILE_FIRST + fw_cfg_file_slots(s)). */
1241 file_slots_max = (UINT16_MAX & FW_CFG_ENTRY_MASK) - FW_CFG_FILE_FIRST + 1;
1242 if (fw_cfg_file_slots(s) > file_slots_max) {
1243 error_setg(errp, "\"file_slots\" must not exceed 0x%" PRIx16,
1244 file_slots_max);
1245 return;
1246 }
1247
1248 s->entries[0] = g_new0(FWCfgEntry, fw_cfg_max_entry(s));
1249 s->entries[1] = g_new0(FWCfgEntry, fw_cfg_max_entry(s));
1250 s->entry_order = g_new0(int, fw_cfg_max_entry(s));
1251 }
1252
1253 static Property fw_cfg_io_properties[] = {
1254 DEFINE_PROP_BOOL("dma_enabled", FWCfgIoState, parent_obj.dma_enabled,
1255 true),
1256 DEFINE_PROP_UINT16("x-file-slots", FWCfgIoState, parent_obj.file_slots,
1257 FW_CFG_FILE_SLOTS_DFLT),
1258 DEFINE_PROP_END_OF_LIST(),
1259 };
1260
1261 static void fw_cfg_io_realize(DeviceState *dev, Error **errp)
1262 {
1263 ERRP_GUARD();
1264 FWCfgIoState *s = FW_CFG_IO(dev);
1265
1266 fw_cfg_file_slots_allocate(FW_CFG(s), errp);
1267 if (*errp) {
1268 return;
1269 }
1270
1271 /* when using port i/o, the 8-bit data register ALWAYS overlaps
1272 * with half of the 16-bit control register. Hence, the total size
1273 * of the i/o region used is FW_CFG_CTL_SIZE */
1274 memory_region_init_io(&s->comb_iomem, OBJECT(s), &fw_cfg_comb_mem_ops,
1275 FW_CFG(s), "fwcfg", FW_CFG_CTL_SIZE);
1276
1277 if (FW_CFG(s)->dma_enabled) {
1278 memory_region_init_io(&FW_CFG(s)->dma_iomem, OBJECT(s),
1279 &fw_cfg_dma_mem_ops, FW_CFG(s), "fwcfg.dma",
1280 sizeof(dma_addr_t));
1281 }
1282
1283 fw_cfg_common_realize(dev, errp);
1284 }
1285
1286 static void fw_cfg_io_class_init(ObjectClass *klass, void *data)
1287 {
1288 DeviceClass *dc = DEVICE_CLASS(klass);
1289
1290 dc->realize = fw_cfg_io_realize;
1291 device_class_set_props(dc, fw_cfg_io_properties);
1292 }
1293
1294 static const TypeInfo fw_cfg_io_info = {
1295 .name = TYPE_FW_CFG_IO,
1296 .parent = TYPE_FW_CFG,
1297 .instance_size = sizeof(FWCfgIoState),
1298 .class_init = fw_cfg_io_class_init,
1299 };
1300
1301
1302 static Property fw_cfg_mem_properties[] = {
1303 DEFINE_PROP_UINT32("data_width", FWCfgMemState, data_width, -1),
1304 DEFINE_PROP_BOOL("dma_enabled", FWCfgMemState, parent_obj.dma_enabled,
1305 true),
1306 DEFINE_PROP_UINT16("x-file-slots", FWCfgMemState, parent_obj.file_slots,
1307 FW_CFG_FILE_SLOTS_DFLT),
1308 DEFINE_PROP_END_OF_LIST(),
1309 };
1310
1311 static void fw_cfg_mem_realize(DeviceState *dev, Error **errp)
1312 {
1313 ERRP_GUARD();
1314 FWCfgMemState *s = FW_CFG_MEM(dev);
1315 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1316 const MemoryRegionOps *data_ops = &fw_cfg_data_mem_ops;
1317
1318 fw_cfg_file_slots_allocate(FW_CFG(s), errp);
1319 if (*errp) {
1320 return;
1321 }
1322
1323 memory_region_init_io(&s->ctl_iomem, OBJECT(s), &fw_cfg_ctl_mem_ops,
1324 FW_CFG(s), "fwcfg.ctl", FW_CFG_CTL_SIZE);
1325 sysbus_init_mmio(sbd, &s->ctl_iomem);
1326
1327 if (s->data_width > data_ops->valid.max_access_size) {
1328 s->wide_data_ops = *data_ops;
1329
1330 s->wide_data_ops.valid.max_access_size = s->data_width;
1331 s->wide_data_ops.impl.max_access_size = s->data_width;
1332 data_ops = &s->wide_data_ops;
1333 }
1334 memory_region_init_io(&s->data_iomem, OBJECT(s), data_ops, FW_CFG(s),
1335 "fwcfg.data", data_ops->valid.max_access_size);
1336 sysbus_init_mmio(sbd, &s->data_iomem);
1337
1338 if (FW_CFG(s)->dma_enabled) {
1339 memory_region_init_io(&FW_CFG(s)->dma_iomem, OBJECT(s),
1340 &fw_cfg_dma_mem_ops, FW_CFG(s), "fwcfg.dma",
1341 sizeof(dma_addr_t));
1342 sysbus_init_mmio(sbd, &FW_CFG(s)->dma_iomem);
1343 }
1344
1345 fw_cfg_common_realize(dev, errp);
1346 }
1347
1348 static void fw_cfg_mem_class_init(ObjectClass *klass, void *data)
1349 {
1350 DeviceClass *dc = DEVICE_CLASS(klass);
1351
1352 dc->realize = fw_cfg_mem_realize;
1353 device_class_set_props(dc, fw_cfg_mem_properties);
1354 }
1355
1356 static const TypeInfo fw_cfg_mem_info = {
1357 .name = TYPE_FW_CFG_MEM,
1358 .parent = TYPE_FW_CFG,
1359 .instance_size = sizeof(FWCfgMemState),
1360 .class_init = fw_cfg_mem_class_init,
1361 };
1362
1363 static void fw_cfg_register_types(void)
1364 {
1365 type_register_static(&fw_cfg_info);
1366 type_register_static(&fw_cfg_io_info);
1367 type_register_static(&fw_cfg_mem_info);
1368 }
1369
1370 type_init(fw_cfg_register_types)