sm501: Add missing arbitration control register
[qemu.git] / hw / nvram / fw_cfg.c
1 /*
2 * QEMU Firmware configuration device emulation
3 *
4 * Copyright (c) 2008 Gleb Natapov
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "qemu/osdep.h"
25 #include "hw/hw.h"
26 #include "sysemu/sysemu.h"
27 #include "sysemu/dma.h"
28 #include "hw/boards.h"
29 #include "hw/isa/isa.h"
30 #include "hw/nvram/fw_cfg.h"
31 #include "hw/sysbus.h"
32 #include "trace.h"
33 #include "qemu/error-report.h"
34 #include "qemu/config-file.h"
35 #include "qemu/cutils.h"
36 #include "qapi/error.h"
37
38 #define FW_CFG_FILE_SLOTS_DFLT 0x20
39
40 #define FW_CFG_NAME "fw_cfg"
41 #define FW_CFG_PATH "/machine/" FW_CFG_NAME
42
43 #define TYPE_FW_CFG "fw_cfg"
44 #define TYPE_FW_CFG_IO "fw_cfg_io"
45 #define TYPE_FW_CFG_MEM "fw_cfg_mem"
46
47 #define FW_CFG(obj) OBJECT_CHECK(FWCfgState, (obj), TYPE_FW_CFG)
48 #define FW_CFG_IO(obj) OBJECT_CHECK(FWCfgIoState, (obj), TYPE_FW_CFG_IO)
49 #define FW_CFG_MEM(obj) OBJECT_CHECK(FWCfgMemState, (obj), TYPE_FW_CFG_MEM)
50
51 /* FW_CFG_VERSION bits */
52 #define FW_CFG_VERSION 0x01
53 #define FW_CFG_VERSION_DMA 0x02
54
55 /* FW_CFG_DMA_CONTROL bits */
56 #define FW_CFG_DMA_CTL_ERROR 0x01
57 #define FW_CFG_DMA_CTL_READ 0x02
58 #define FW_CFG_DMA_CTL_SKIP 0x04
59 #define FW_CFG_DMA_CTL_SELECT 0x08
60 #define FW_CFG_DMA_CTL_WRITE 0x10
61
62 #define FW_CFG_DMA_SIGNATURE 0x51454d5520434647ULL /* "QEMU CFG" */
63
64 typedef struct FWCfgEntry {
65 uint32_t len;
66 bool allow_write;
67 uint8_t *data;
68 void *callback_opaque;
69 FWCfgReadCallback read_callback;
70 } FWCfgEntry;
71
72 struct FWCfgState {
73 /*< private >*/
74 SysBusDevice parent_obj;
75 /*< public >*/
76
77 uint16_t file_slots;
78 FWCfgEntry *entries[2];
79 int *entry_order;
80 FWCfgFiles *files;
81 uint16_t cur_entry;
82 uint32_t cur_offset;
83 Notifier machine_ready;
84
85 int fw_cfg_order_override;
86
87 bool dma_enabled;
88 dma_addr_t dma_addr;
89 AddressSpace *dma_as;
90 MemoryRegion dma_iomem;
91 };
92
93 struct FWCfgIoState {
94 /*< private >*/
95 FWCfgState parent_obj;
96 /*< public >*/
97
98 MemoryRegion comb_iomem;
99 uint32_t iobase, dma_iobase;
100 };
101
102 struct FWCfgMemState {
103 /*< private >*/
104 FWCfgState parent_obj;
105 /*< public >*/
106
107 MemoryRegion ctl_iomem, data_iomem;
108 uint32_t data_width;
109 MemoryRegionOps wide_data_ops;
110 };
111
112 #define JPG_FILE 0
113 #define BMP_FILE 1
114
115 static char *read_splashfile(char *filename, gsize *file_sizep,
116 int *file_typep)
117 {
118 GError *err = NULL;
119 gboolean res;
120 gchar *content;
121 int file_type;
122 unsigned int filehead;
123 int bmp_bpp;
124
125 res = g_file_get_contents(filename, &content, file_sizep, &err);
126 if (res == FALSE) {
127 error_report("failed to read splash file '%s'", filename);
128 g_error_free(err);
129 return NULL;
130 }
131
132 /* check file size */
133 if (*file_sizep < 30) {
134 goto error;
135 }
136
137 /* check magic ID */
138 filehead = ((content[0] & 0xff) + (content[1] << 8)) & 0xffff;
139 if (filehead == 0xd8ff) {
140 file_type = JPG_FILE;
141 } else if (filehead == 0x4d42) {
142 file_type = BMP_FILE;
143 } else {
144 goto error;
145 }
146
147 /* check BMP bpp */
148 if (file_type == BMP_FILE) {
149 bmp_bpp = (content[28] + (content[29] << 8)) & 0xffff;
150 if (bmp_bpp != 24) {
151 goto error;
152 }
153 }
154
155 /* return values */
156 *file_typep = file_type;
157
158 return content;
159
160 error:
161 error_report("splash file '%s' format not recognized; must be JPEG "
162 "or 24 bit BMP", filename);
163 g_free(content);
164 return NULL;
165 }
166
167 static void fw_cfg_bootsplash(FWCfgState *s)
168 {
169 int boot_splash_time = -1;
170 const char *boot_splash_filename = NULL;
171 char *p;
172 char *filename, *file_data;
173 gsize file_size;
174 int file_type;
175 const char *temp;
176
177 /* get user configuration */
178 QemuOptsList *plist = qemu_find_opts("boot-opts");
179 QemuOpts *opts = QTAILQ_FIRST(&plist->head);
180 if (opts != NULL) {
181 temp = qemu_opt_get(opts, "splash");
182 if (temp != NULL) {
183 boot_splash_filename = temp;
184 }
185 temp = qemu_opt_get(opts, "splash-time");
186 if (temp != NULL) {
187 p = (char *)temp;
188 boot_splash_time = strtol(p, &p, 10);
189 }
190 }
191
192 /* insert splash time if user configurated */
193 if (boot_splash_time >= 0) {
194 /* validate the input */
195 if (boot_splash_time > 0xffff) {
196 error_report("splash time is big than 65535, force it to 65535.");
197 boot_splash_time = 0xffff;
198 }
199 /* use little endian format */
200 qemu_extra_params_fw[0] = (uint8_t)(boot_splash_time & 0xff);
201 qemu_extra_params_fw[1] = (uint8_t)((boot_splash_time >> 8) & 0xff);
202 fw_cfg_add_file(s, "etc/boot-menu-wait", qemu_extra_params_fw, 2);
203 }
204
205 /* insert splash file if user configurated */
206 if (boot_splash_filename != NULL) {
207 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, boot_splash_filename);
208 if (filename == NULL) {
209 error_report("failed to find file '%s'.", boot_splash_filename);
210 return;
211 }
212
213 /* loading file data */
214 file_data = read_splashfile(filename, &file_size, &file_type);
215 if (file_data == NULL) {
216 g_free(filename);
217 return;
218 }
219 g_free(boot_splash_filedata);
220 boot_splash_filedata = (uint8_t *)file_data;
221 boot_splash_filedata_size = file_size;
222
223 /* insert data */
224 if (file_type == JPG_FILE) {
225 fw_cfg_add_file(s, "bootsplash.jpg",
226 boot_splash_filedata, boot_splash_filedata_size);
227 } else {
228 fw_cfg_add_file(s, "bootsplash.bmp",
229 boot_splash_filedata, boot_splash_filedata_size);
230 }
231 g_free(filename);
232 }
233 }
234
235 static void fw_cfg_reboot(FWCfgState *s)
236 {
237 int reboot_timeout = -1;
238 char *p;
239 const char *temp;
240
241 /* get user configuration */
242 QemuOptsList *plist = qemu_find_opts("boot-opts");
243 QemuOpts *opts = QTAILQ_FIRST(&plist->head);
244 if (opts != NULL) {
245 temp = qemu_opt_get(opts, "reboot-timeout");
246 if (temp != NULL) {
247 p = (char *)temp;
248 reboot_timeout = strtol(p, &p, 10);
249 }
250 }
251 /* validate the input */
252 if (reboot_timeout > 0xffff) {
253 error_report("reboot timeout is larger than 65535, force it to 65535.");
254 reboot_timeout = 0xffff;
255 }
256 fw_cfg_add_file(s, "etc/boot-fail-wait", g_memdup(&reboot_timeout, 4), 4);
257 }
258
259 static void fw_cfg_write(FWCfgState *s, uint8_t value)
260 {
261 /* nothing, write support removed in QEMU v2.4+ */
262 }
263
264 static inline uint16_t fw_cfg_file_slots(const FWCfgState *s)
265 {
266 return s->file_slots;
267 }
268
269 /* Note: this function returns an exclusive limit. */
270 static inline uint32_t fw_cfg_max_entry(const FWCfgState *s)
271 {
272 return FW_CFG_FILE_FIRST + fw_cfg_file_slots(s);
273 }
274
275 static int fw_cfg_select(FWCfgState *s, uint16_t key)
276 {
277 int arch, ret;
278 FWCfgEntry *e;
279
280 s->cur_offset = 0;
281 if ((key & FW_CFG_ENTRY_MASK) >= fw_cfg_max_entry(s)) {
282 s->cur_entry = FW_CFG_INVALID;
283 ret = 0;
284 } else {
285 s->cur_entry = key;
286 ret = 1;
287 /* entry successfully selected, now run callback if present */
288 arch = !!(key & FW_CFG_ARCH_LOCAL);
289 e = &s->entries[arch][key & FW_CFG_ENTRY_MASK];
290 if (e->read_callback) {
291 e->read_callback(e->callback_opaque);
292 }
293 }
294
295 trace_fw_cfg_select(s, key, ret);
296 return ret;
297 }
298
299 static uint64_t fw_cfg_data_read(void *opaque, hwaddr addr, unsigned size)
300 {
301 FWCfgState *s = opaque;
302 int arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL);
303 FWCfgEntry *e = (s->cur_entry == FW_CFG_INVALID) ? NULL :
304 &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK];
305 uint64_t value = 0;
306
307 assert(size > 0 && size <= sizeof(value));
308 if (s->cur_entry != FW_CFG_INVALID && e->data && s->cur_offset < e->len) {
309 /* The least significant 'size' bytes of the return value are
310 * expected to contain a string preserving portion of the item
311 * data, padded with zeros on the right in case we run out early.
312 * In technical terms, we're composing the host-endian representation
313 * of the big endian interpretation of the fw_cfg string.
314 */
315 do {
316 value = (value << 8) | e->data[s->cur_offset++];
317 } while (--size && s->cur_offset < e->len);
318 /* If size is still not zero, we *did* run out early, so continue
319 * left-shifting, to add the appropriate number of padding zeros
320 * on the right.
321 */
322 value <<= 8 * size;
323 }
324
325 trace_fw_cfg_read(s, value);
326 return value;
327 }
328
329 static void fw_cfg_data_mem_write(void *opaque, hwaddr addr,
330 uint64_t value, unsigned size)
331 {
332 FWCfgState *s = opaque;
333 unsigned i = size;
334
335 do {
336 fw_cfg_write(s, value >> (8 * --i));
337 } while (i);
338 }
339
340 static void fw_cfg_dma_transfer(FWCfgState *s)
341 {
342 dma_addr_t len;
343 FWCfgDmaAccess dma;
344 int arch;
345 FWCfgEntry *e;
346 int read = 0, write = 0;
347 dma_addr_t dma_addr;
348
349 /* Reset the address before the next access */
350 dma_addr = s->dma_addr;
351 s->dma_addr = 0;
352
353 if (dma_memory_read(s->dma_as, dma_addr, &dma, sizeof(dma))) {
354 stl_be_dma(s->dma_as, dma_addr + offsetof(FWCfgDmaAccess, control),
355 FW_CFG_DMA_CTL_ERROR);
356 return;
357 }
358
359 dma.address = be64_to_cpu(dma.address);
360 dma.length = be32_to_cpu(dma.length);
361 dma.control = be32_to_cpu(dma.control);
362
363 if (dma.control & FW_CFG_DMA_CTL_SELECT) {
364 fw_cfg_select(s, dma.control >> 16);
365 }
366
367 arch = !!(s->cur_entry & FW_CFG_ARCH_LOCAL);
368 e = (s->cur_entry == FW_CFG_INVALID) ? NULL :
369 &s->entries[arch][s->cur_entry & FW_CFG_ENTRY_MASK];
370
371 if (dma.control & FW_CFG_DMA_CTL_READ) {
372 read = 1;
373 write = 0;
374 } else if (dma.control & FW_CFG_DMA_CTL_WRITE) {
375 read = 0;
376 write = 1;
377 } else if (dma.control & FW_CFG_DMA_CTL_SKIP) {
378 read = 0;
379 write = 0;
380 } else {
381 dma.length = 0;
382 }
383
384 dma.control = 0;
385
386 while (dma.length > 0 && !(dma.control & FW_CFG_DMA_CTL_ERROR)) {
387 if (s->cur_entry == FW_CFG_INVALID || !e->data ||
388 s->cur_offset >= e->len) {
389 len = dma.length;
390
391 /* If the access is not a read access, it will be a skip access,
392 * tested before.
393 */
394 if (read) {
395 if (dma_memory_set(s->dma_as, dma.address, 0, len)) {
396 dma.control |= FW_CFG_DMA_CTL_ERROR;
397 }
398 }
399 if (write) {
400 dma.control |= FW_CFG_DMA_CTL_ERROR;
401 }
402 } else {
403 if (dma.length <= (e->len - s->cur_offset)) {
404 len = dma.length;
405 } else {
406 len = (e->len - s->cur_offset);
407 }
408
409 /* If the access is not a read access, it will be a skip access,
410 * tested before.
411 */
412 if (read) {
413 if (dma_memory_write(s->dma_as, dma.address,
414 &e->data[s->cur_offset], len)) {
415 dma.control |= FW_CFG_DMA_CTL_ERROR;
416 }
417 }
418 if (write) {
419 if (!e->allow_write ||
420 len != dma.length ||
421 dma_memory_read(s->dma_as, dma.address,
422 &e->data[s->cur_offset], len)) {
423 dma.control |= FW_CFG_DMA_CTL_ERROR;
424 }
425 }
426
427 s->cur_offset += len;
428 }
429
430 dma.address += len;
431 dma.length -= len;
432
433 }
434
435 stl_be_dma(s->dma_as, dma_addr + offsetof(FWCfgDmaAccess, control),
436 dma.control);
437
438 trace_fw_cfg_read(s, 0);
439 }
440
441 static uint64_t fw_cfg_dma_mem_read(void *opaque, hwaddr addr,
442 unsigned size)
443 {
444 /* Return a signature value (and handle various read sizes) */
445 return extract64(FW_CFG_DMA_SIGNATURE, (8 - addr - size) * 8, size * 8);
446 }
447
448 static void fw_cfg_dma_mem_write(void *opaque, hwaddr addr,
449 uint64_t value, unsigned size)
450 {
451 FWCfgState *s = opaque;
452
453 if (size == 4) {
454 if (addr == 0) {
455 /* FWCfgDmaAccess high address */
456 s->dma_addr = value << 32;
457 } else if (addr == 4) {
458 /* FWCfgDmaAccess low address */
459 s->dma_addr |= value;
460 fw_cfg_dma_transfer(s);
461 }
462 } else if (size == 8 && addr == 0) {
463 s->dma_addr = value;
464 fw_cfg_dma_transfer(s);
465 }
466 }
467
468 static bool fw_cfg_dma_mem_valid(void *opaque, hwaddr addr,
469 unsigned size, bool is_write)
470 {
471 return !is_write || ((size == 4 && (addr == 0 || addr == 4)) ||
472 (size == 8 && addr == 0));
473 }
474
475 static bool fw_cfg_data_mem_valid(void *opaque, hwaddr addr,
476 unsigned size, bool is_write)
477 {
478 return addr == 0;
479 }
480
481 static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr,
482 uint64_t value, unsigned size)
483 {
484 fw_cfg_select(opaque, (uint16_t)value);
485 }
486
487 static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr,
488 unsigned size, bool is_write)
489 {
490 return is_write && size == 2;
491 }
492
493 static void fw_cfg_comb_write(void *opaque, hwaddr addr,
494 uint64_t value, unsigned size)
495 {
496 switch (size) {
497 case 1:
498 fw_cfg_write(opaque, (uint8_t)value);
499 break;
500 case 2:
501 fw_cfg_select(opaque, (uint16_t)value);
502 break;
503 }
504 }
505
506 static bool fw_cfg_comb_valid(void *opaque, hwaddr addr,
507 unsigned size, bool is_write)
508 {
509 return (size == 1) || (is_write && size == 2);
510 }
511
512 static const MemoryRegionOps fw_cfg_ctl_mem_ops = {
513 .write = fw_cfg_ctl_mem_write,
514 .endianness = DEVICE_BIG_ENDIAN,
515 .valid.accepts = fw_cfg_ctl_mem_valid,
516 };
517
518 static const MemoryRegionOps fw_cfg_data_mem_ops = {
519 .read = fw_cfg_data_read,
520 .write = fw_cfg_data_mem_write,
521 .endianness = DEVICE_BIG_ENDIAN,
522 .valid = {
523 .min_access_size = 1,
524 .max_access_size = 1,
525 .accepts = fw_cfg_data_mem_valid,
526 },
527 };
528
529 static const MemoryRegionOps fw_cfg_comb_mem_ops = {
530 .read = fw_cfg_data_read,
531 .write = fw_cfg_comb_write,
532 .endianness = DEVICE_LITTLE_ENDIAN,
533 .valid.accepts = fw_cfg_comb_valid,
534 };
535
536 static const MemoryRegionOps fw_cfg_dma_mem_ops = {
537 .read = fw_cfg_dma_mem_read,
538 .write = fw_cfg_dma_mem_write,
539 .endianness = DEVICE_BIG_ENDIAN,
540 .valid.accepts = fw_cfg_dma_mem_valid,
541 .valid.max_access_size = 8,
542 .impl.max_access_size = 8,
543 };
544
545 static void fw_cfg_reset(DeviceState *d)
546 {
547 FWCfgState *s = FW_CFG(d);
548
549 /* we never register a read callback for FW_CFG_SIGNATURE */
550 fw_cfg_select(s, FW_CFG_SIGNATURE);
551 }
552
553 /* Save restore 32 bit int as uint16_t
554 This is a Big hack, but it is how the old state did it.
555 Or we broke compatibility in the state, or we can't use struct tm
556 */
557
558 static int get_uint32_as_uint16(QEMUFile *f, void *pv, size_t size,
559 VMStateField *field)
560 {
561 uint32_t *v = pv;
562 *v = qemu_get_be16(f);
563 return 0;
564 }
565
566 static int put_unused(QEMUFile *f, void *pv, size_t size, VMStateField *field,
567 QJSON *vmdesc)
568 {
569 fprintf(stderr, "uint32_as_uint16 is only used for backward compatibility.\n");
570 fprintf(stderr, "This functions shouldn't be called.\n");
571
572 return 0;
573 }
574
575 static const VMStateInfo vmstate_hack_uint32_as_uint16 = {
576 .name = "int32_as_uint16",
577 .get = get_uint32_as_uint16,
578 .put = put_unused,
579 };
580
581 #define VMSTATE_UINT16_HACK(_f, _s, _t) \
582 VMSTATE_SINGLE_TEST(_f, _s, _t, 0, vmstate_hack_uint32_as_uint16, uint32_t)
583
584
585 static bool is_version_1(void *opaque, int version_id)
586 {
587 return version_id == 1;
588 }
589
590 bool fw_cfg_dma_enabled(void *opaque)
591 {
592 FWCfgState *s = opaque;
593
594 return s->dma_enabled;
595 }
596
597 static const VMStateDescription vmstate_fw_cfg_dma = {
598 .name = "fw_cfg/dma",
599 .needed = fw_cfg_dma_enabled,
600 .fields = (VMStateField[]) {
601 VMSTATE_UINT64(dma_addr, FWCfgState),
602 VMSTATE_END_OF_LIST()
603 },
604 };
605
606 static const VMStateDescription vmstate_fw_cfg = {
607 .name = "fw_cfg",
608 .version_id = 2,
609 .minimum_version_id = 1,
610 .fields = (VMStateField[]) {
611 VMSTATE_UINT16(cur_entry, FWCfgState),
612 VMSTATE_UINT16_HACK(cur_offset, FWCfgState, is_version_1),
613 VMSTATE_UINT32_V(cur_offset, FWCfgState, 2),
614 VMSTATE_END_OF_LIST()
615 },
616 .subsections = (const VMStateDescription*[]) {
617 &vmstate_fw_cfg_dma,
618 NULL,
619 }
620 };
621
622 static void fw_cfg_add_bytes_read_callback(FWCfgState *s, uint16_t key,
623 FWCfgReadCallback callback,
624 void *callback_opaque,
625 void *data, size_t len,
626 bool read_only)
627 {
628 int arch = !!(key & FW_CFG_ARCH_LOCAL);
629
630 key &= FW_CFG_ENTRY_MASK;
631
632 assert(key < fw_cfg_max_entry(s) && len < UINT32_MAX);
633 assert(s->entries[arch][key].data == NULL); /* avoid key conflict */
634
635 s->entries[arch][key].data = data;
636 s->entries[arch][key].len = (uint32_t)len;
637 s->entries[arch][key].read_callback = callback;
638 s->entries[arch][key].callback_opaque = callback_opaque;
639 s->entries[arch][key].allow_write = !read_only;
640 }
641
642 static void *fw_cfg_modify_bytes_read(FWCfgState *s, uint16_t key,
643 void *data, size_t len)
644 {
645 void *ptr;
646 int arch = !!(key & FW_CFG_ARCH_LOCAL);
647
648 key &= FW_CFG_ENTRY_MASK;
649
650 assert(key < fw_cfg_max_entry(s) && len < UINT32_MAX);
651
652 /* return the old data to the function caller, avoid memory leak */
653 ptr = s->entries[arch][key].data;
654 s->entries[arch][key].data = data;
655 s->entries[arch][key].len = len;
656 s->entries[arch][key].callback_opaque = NULL;
657 s->entries[arch][key].allow_write = false;
658
659 return ptr;
660 }
661
662 void fw_cfg_add_bytes(FWCfgState *s, uint16_t key, void *data, size_t len)
663 {
664 fw_cfg_add_bytes_read_callback(s, key, NULL, NULL, data, len, true);
665 }
666
667 void fw_cfg_add_string(FWCfgState *s, uint16_t key, const char *value)
668 {
669 size_t sz = strlen(value) + 1;
670
671 fw_cfg_add_bytes(s, key, g_memdup(value, sz), sz);
672 }
673
674 void fw_cfg_add_i16(FWCfgState *s, uint16_t key, uint16_t value)
675 {
676 uint16_t *copy;
677
678 copy = g_malloc(sizeof(value));
679 *copy = cpu_to_le16(value);
680 fw_cfg_add_bytes(s, key, copy, sizeof(value));
681 }
682
683 void fw_cfg_modify_i16(FWCfgState *s, uint16_t key, uint16_t value)
684 {
685 uint16_t *copy, *old;
686
687 copy = g_malloc(sizeof(value));
688 *copy = cpu_to_le16(value);
689 old = fw_cfg_modify_bytes_read(s, key, copy, sizeof(value));
690 g_free(old);
691 }
692
693 void fw_cfg_add_i32(FWCfgState *s, uint16_t key, uint32_t value)
694 {
695 uint32_t *copy;
696
697 copy = g_malloc(sizeof(value));
698 *copy = cpu_to_le32(value);
699 fw_cfg_add_bytes(s, key, copy, sizeof(value));
700 }
701
702 void fw_cfg_add_i64(FWCfgState *s, uint16_t key, uint64_t value)
703 {
704 uint64_t *copy;
705
706 copy = g_malloc(sizeof(value));
707 *copy = cpu_to_le64(value);
708 fw_cfg_add_bytes(s, key, copy, sizeof(value));
709 }
710
711 void fw_cfg_set_order_override(FWCfgState *s, int order)
712 {
713 assert(s->fw_cfg_order_override == 0);
714 s->fw_cfg_order_override = order;
715 }
716
717 void fw_cfg_reset_order_override(FWCfgState *s)
718 {
719 assert(s->fw_cfg_order_override != 0);
720 s->fw_cfg_order_override = 0;
721 }
722
723 /*
724 * This is the legacy order list. For legacy systems, files are in
725 * the fw_cfg in the order defined below, by the "order" value. Note
726 * that some entries (VGA ROMs, NIC option ROMS, etc.) go into a
727 * specific area, but there may be more than one and they occur in the
728 * order that the user specifies them on the command line. Those are
729 * handled in a special manner, using the order override above.
730 *
731 * For non-legacy, the files are sorted by filename to avoid this kind
732 * of complexity in the future.
733 *
734 * This is only for x86, other arches don't implement versioning so
735 * they won't set legacy mode.
736 */
737 static struct {
738 const char *name;
739 int order;
740 } fw_cfg_order[] = {
741 { "etc/boot-menu-wait", 10 },
742 { "bootsplash.jpg", 11 },
743 { "bootsplash.bmp", 12 },
744 { "etc/boot-fail-wait", 15 },
745 { "etc/smbios/smbios-tables", 20 },
746 { "etc/smbios/smbios-anchor", 30 },
747 { "etc/e820", 40 },
748 { "etc/reserved-memory-end", 50 },
749 { "genroms/kvmvapic.bin", 55 },
750 { "genroms/linuxboot.bin", 60 },
751 { }, /* VGA ROMs from pc_vga_init come here, 70. */
752 { }, /* NIC option ROMs from pc_nic_init come here, 80. */
753 { "etc/system-states", 90 },
754 { }, /* User ROMs come here, 100. */
755 { }, /* Device FW comes here, 110. */
756 { "etc/extra-pci-roots", 120 },
757 { "etc/acpi/tables", 130 },
758 { "etc/table-loader", 140 },
759 { "etc/tpm/log", 150 },
760 { "etc/acpi/rsdp", 160 },
761 { "bootorder", 170 },
762
763 #define FW_CFG_ORDER_OVERRIDE_LAST 200
764 };
765
766 static int get_fw_cfg_order(FWCfgState *s, const char *name)
767 {
768 int i;
769
770 if (s->fw_cfg_order_override > 0) {
771 return s->fw_cfg_order_override;
772 }
773
774 for (i = 0; i < ARRAY_SIZE(fw_cfg_order); i++) {
775 if (fw_cfg_order[i].name == NULL) {
776 continue;
777 }
778
779 if (strcmp(name, fw_cfg_order[i].name) == 0) {
780 return fw_cfg_order[i].order;
781 }
782 }
783
784 /* Stick unknown stuff at the end. */
785 error_report("warning: Unknown firmware file in legacy mode: %s", name);
786 return FW_CFG_ORDER_OVERRIDE_LAST;
787 }
788
789 void fw_cfg_add_file_callback(FWCfgState *s, const char *filename,
790 FWCfgReadCallback callback, void *callback_opaque,
791 void *data, size_t len, bool read_only)
792 {
793 int i, index, count;
794 size_t dsize;
795 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
796 int order = 0;
797
798 if (!s->files) {
799 dsize = sizeof(uint32_t) + sizeof(FWCfgFile) * fw_cfg_file_slots(s);
800 s->files = g_malloc0(dsize);
801 fw_cfg_add_bytes(s, FW_CFG_FILE_DIR, s->files, dsize);
802 }
803
804 count = be32_to_cpu(s->files->count);
805 assert(count < fw_cfg_file_slots(s));
806
807 /* Find the insertion point. */
808 if (mc->legacy_fw_cfg_order) {
809 /*
810 * Sort by order. For files with the same order, we keep them
811 * in the sequence in which they were added.
812 */
813 order = get_fw_cfg_order(s, filename);
814 for (index = count;
815 index > 0 && order < s->entry_order[index - 1];
816 index--);
817 } else {
818 /* Sort by file name. */
819 for (index = count;
820 index > 0 && strcmp(filename, s->files->f[index - 1].name) < 0;
821 index--);
822 }
823
824 /*
825 * Move all the entries from the index point and after down one
826 * to create a slot for the new entry. Because calculations are
827 * being done with the index, make it so that "i" is the current
828 * index and "i - 1" is the one being copied from, thus the
829 * unusual start and end in the for statement.
830 */
831 for (i = count + 1; i > index; i--) {
832 s->files->f[i] = s->files->f[i - 1];
833 s->files->f[i].select = cpu_to_be16(FW_CFG_FILE_FIRST + i);
834 s->entries[0][FW_CFG_FILE_FIRST + i] =
835 s->entries[0][FW_CFG_FILE_FIRST + i - 1];
836 s->entry_order[i] = s->entry_order[i - 1];
837 }
838
839 memset(&s->files->f[index], 0, sizeof(FWCfgFile));
840 memset(&s->entries[0][FW_CFG_FILE_FIRST + index], 0, sizeof(FWCfgEntry));
841
842 pstrcpy(s->files->f[index].name, sizeof(s->files->f[index].name), filename);
843 for (i = 0; i <= count; i++) {
844 if (i != index &&
845 strcmp(s->files->f[index].name, s->files->f[i].name) == 0) {
846 error_report("duplicate fw_cfg file name: %s",
847 s->files->f[index].name);
848 exit(1);
849 }
850 }
851
852 fw_cfg_add_bytes_read_callback(s, FW_CFG_FILE_FIRST + index,
853 callback, callback_opaque, data, len,
854 read_only);
855
856 s->files->f[index].size = cpu_to_be32(len);
857 s->files->f[index].select = cpu_to_be16(FW_CFG_FILE_FIRST + index);
858 s->entry_order[index] = order;
859 trace_fw_cfg_add_file(s, index, s->files->f[index].name, len);
860
861 s->files->count = cpu_to_be32(count+1);
862 }
863
864 void fw_cfg_add_file(FWCfgState *s, const char *filename,
865 void *data, size_t len)
866 {
867 fw_cfg_add_file_callback(s, filename, NULL, NULL, data, len, true);
868 }
869
870 void *fw_cfg_modify_file(FWCfgState *s, const char *filename,
871 void *data, size_t len)
872 {
873 int i, index;
874 void *ptr = NULL;
875
876 assert(s->files);
877
878 index = be32_to_cpu(s->files->count);
879 assert(index < fw_cfg_file_slots(s));
880
881 for (i = 0; i < index; i++) {
882 if (strcmp(filename, s->files->f[i].name) == 0) {
883 ptr = fw_cfg_modify_bytes_read(s, FW_CFG_FILE_FIRST + i,
884 data, len);
885 s->files->f[i].size = cpu_to_be32(len);
886 return ptr;
887 }
888 }
889 /* add new one */
890 fw_cfg_add_file_callback(s, filename, NULL, NULL, data, len, true);
891 return NULL;
892 }
893
894 static void fw_cfg_machine_reset(void *opaque)
895 {
896 void *ptr;
897 size_t len;
898 FWCfgState *s = opaque;
899 char *bootindex = get_boot_devices_list(&len, false);
900
901 ptr = fw_cfg_modify_file(s, "bootorder", (uint8_t *)bootindex, len);
902 g_free(ptr);
903 }
904
905 static void fw_cfg_machine_ready(struct Notifier *n, void *data)
906 {
907 FWCfgState *s = container_of(n, FWCfgState, machine_ready);
908 qemu_register_reset(fw_cfg_machine_reset, s);
909 }
910
911
912
913 static void fw_cfg_init1(DeviceState *dev)
914 {
915 FWCfgState *s = FW_CFG(dev);
916 MachineState *machine = MACHINE(qdev_get_machine());
917
918 assert(!object_resolve_path(FW_CFG_PATH, NULL));
919
920 object_property_add_child(OBJECT(machine), FW_CFG_NAME, OBJECT(s), NULL);
921
922 qdev_init_nofail(dev);
923
924 fw_cfg_add_bytes(s, FW_CFG_SIGNATURE, (char *)"QEMU", 4);
925 fw_cfg_add_bytes(s, FW_CFG_UUID, &qemu_uuid, 16);
926 fw_cfg_add_i16(s, FW_CFG_NOGRAPHIC, (uint16_t)!machine->enable_graphics);
927 fw_cfg_add_i16(s, FW_CFG_BOOT_MENU, (uint16_t)boot_menu);
928 fw_cfg_bootsplash(s);
929 fw_cfg_reboot(s);
930
931 s->machine_ready.notify = fw_cfg_machine_ready;
932 qemu_add_machine_init_done_notifier(&s->machine_ready);
933 }
934
935 FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, uint32_t dma_iobase,
936 AddressSpace *dma_as)
937 {
938 DeviceState *dev;
939 FWCfgState *s;
940 uint32_t version = FW_CFG_VERSION;
941 bool dma_requested = dma_iobase && dma_as;
942
943 dev = qdev_create(NULL, TYPE_FW_CFG_IO);
944 qdev_prop_set_uint32(dev, "iobase", iobase);
945 qdev_prop_set_uint32(dev, "dma_iobase", dma_iobase);
946 if (!dma_requested) {
947 qdev_prop_set_bit(dev, "dma_enabled", false);
948 }
949
950 fw_cfg_init1(dev);
951 s = FW_CFG(dev);
952
953 if (s->dma_enabled) {
954 /* 64 bits for the address field */
955 s->dma_as = dma_as;
956 s->dma_addr = 0;
957
958 version |= FW_CFG_VERSION_DMA;
959 }
960
961 fw_cfg_add_i32(s, FW_CFG_ID, version);
962
963 return s;
964 }
965
966 FWCfgState *fw_cfg_init_io(uint32_t iobase)
967 {
968 return fw_cfg_init_io_dma(iobase, 0, NULL);
969 }
970
971 FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr,
972 hwaddr data_addr, uint32_t data_width,
973 hwaddr dma_addr, AddressSpace *dma_as)
974 {
975 DeviceState *dev;
976 SysBusDevice *sbd;
977 FWCfgState *s;
978 uint32_t version = FW_CFG_VERSION;
979 bool dma_requested = dma_addr && dma_as;
980
981 dev = qdev_create(NULL, TYPE_FW_CFG_MEM);
982 qdev_prop_set_uint32(dev, "data_width", data_width);
983 if (!dma_requested) {
984 qdev_prop_set_bit(dev, "dma_enabled", false);
985 }
986
987 fw_cfg_init1(dev);
988
989 sbd = SYS_BUS_DEVICE(dev);
990 sysbus_mmio_map(sbd, 0, ctl_addr);
991 sysbus_mmio_map(sbd, 1, data_addr);
992
993 s = FW_CFG(dev);
994
995 if (s->dma_enabled) {
996 s->dma_as = dma_as;
997 s->dma_addr = 0;
998 sysbus_mmio_map(sbd, 2, dma_addr);
999 version |= FW_CFG_VERSION_DMA;
1000 }
1001
1002 fw_cfg_add_i32(s, FW_CFG_ID, version);
1003
1004 return s;
1005 }
1006
1007 FWCfgState *fw_cfg_init_mem(hwaddr ctl_addr, hwaddr data_addr)
1008 {
1009 return fw_cfg_init_mem_wide(ctl_addr, data_addr,
1010 fw_cfg_data_mem_ops.valid.max_access_size,
1011 0, NULL);
1012 }
1013
1014
1015 FWCfgState *fw_cfg_find(void)
1016 {
1017 return FW_CFG(object_resolve_path(FW_CFG_PATH, NULL));
1018 }
1019
1020 static void fw_cfg_class_init(ObjectClass *klass, void *data)
1021 {
1022 DeviceClass *dc = DEVICE_CLASS(klass);
1023
1024 dc->reset = fw_cfg_reset;
1025 dc->vmsd = &vmstate_fw_cfg;
1026 }
1027
1028 static const TypeInfo fw_cfg_info = {
1029 .name = TYPE_FW_CFG,
1030 .parent = TYPE_SYS_BUS_DEVICE,
1031 .abstract = true,
1032 .instance_size = sizeof(FWCfgState),
1033 .class_init = fw_cfg_class_init,
1034 };
1035
1036 static void fw_cfg_file_slots_allocate(FWCfgState *s, Error **errp)
1037 {
1038 uint16_t file_slots_max;
1039
1040 if (fw_cfg_file_slots(s) < FW_CFG_FILE_SLOTS_MIN) {
1041 error_setg(errp, "\"file_slots\" must be at least 0x%x",
1042 FW_CFG_FILE_SLOTS_MIN);
1043 return;
1044 }
1045
1046 /* (UINT16_MAX & FW_CFG_ENTRY_MASK) is the highest inclusive selector value
1047 * that we permit. The actual (exclusive) value coming from the
1048 * configuration is (FW_CFG_FILE_FIRST + fw_cfg_file_slots(s)). */
1049 file_slots_max = (UINT16_MAX & FW_CFG_ENTRY_MASK) - FW_CFG_FILE_FIRST + 1;
1050 if (fw_cfg_file_slots(s) > file_slots_max) {
1051 error_setg(errp, "\"file_slots\" must not exceed 0x%" PRIx16,
1052 file_slots_max);
1053 return;
1054 }
1055
1056 s->entries[0] = g_new0(FWCfgEntry, fw_cfg_max_entry(s));
1057 s->entries[1] = g_new0(FWCfgEntry, fw_cfg_max_entry(s));
1058 s->entry_order = g_new0(int, fw_cfg_max_entry(s));
1059 }
1060
1061 static Property fw_cfg_io_properties[] = {
1062 DEFINE_PROP_UINT32("iobase", FWCfgIoState, iobase, -1),
1063 DEFINE_PROP_UINT32("dma_iobase", FWCfgIoState, dma_iobase, -1),
1064 DEFINE_PROP_BOOL("dma_enabled", FWCfgIoState, parent_obj.dma_enabled,
1065 true),
1066 DEFINE_PROP_UINT16("x-file-slots", FWCfgIoState, parent_obj.file_slots,
1067 FW_CFG_FILE_SLOTS_DFLT),
1068 DEFINE_PROP_END_OF_LIST(),
1069 };
1070
1071 static void fw_cfg_io_realize(DeviceState *dev, Error **errp)
1072 {
1073 FWCfgIoState *s = FW_CFG_IO(dev);
1074 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1075 Error *local_err = NULL;
1076
1077 fw_cfg_file_slots_allocate(FW_CFG(s), &local_err);
1078 if (local_err) {
1079 error_propagate(errp, local_err);
1080 return;
1081 }
1082
1083 /* when using port i/o, the 8-bit data register ALWAYS overlaps
1084 * with half of the 16-bit control register. Hence, the total size
1085 * of the i/o region used is FW_CFG_CTL_SIZE */
1086 memory_region_init_io(&s->comb_iomem, OBJECT(s), &fw_cfg_comb_mem_ops,
1087 FW_CFG(s), "fwcfg", FW_CFG_CTL_SIZE);
1088 sysbus_add_io(sbd, s->iobase, &s->comb_iomem);
1089
1090 if (FW_CFG(s)->dma_enabled) {
1091 memory_region_init_io(&FW_CFG(s)->dma_iomem, OBJECT(s),
1092 &fw_cfg_dma_mem_ops, FW_CFG(s), "fwcfg.dma",
1093 sizeof(dma_addr_t));
1094 sysbus_add_io(sbd, s->dma_iobase, &FW_CFG(s)->dma_iomem);
1095 }
1096 }
1097
1098 static void fw_cfg_io_class_init(ObjectClass *klass, void *data)
1099 {
1100 DeviceClass *dc = DEVICE_CLASS(klass);
1101
1102 dc->realize = fw_cfg_io_realize;
1103 dc->props = fw_cfg_io_properties;
1104 }
1105
1106 static const TypeInfo fw_cfg_io_info = {
1107 .name = TYPE_FW_CFG_IO,
1108 .parent = TYPE_FW_CFG,
1109 .instance_size = sizeof(FWCfgIoState),
1110 .class_init = fw_cfg_io_class_init,
1111 };
1112
1113
1114 static Property fw_cfg_mem_properties[] = {
1115 DEFINE_PROP_UINT32("data_width", FWCfgMemState, data_width, -1),
1116 DEFINE_PROP_BOOL("dma_enabled", FWCfgMemState, parent_obj.dma_enabled,
1117 true),
1118 DEFINE_PROP_UINT16("x-file-slots", FWCfgMemState, parent_obj.file_slots,
1119 FW_CFG_FILE_SLOTS_DFLT),
1120 DEFINE_PROP_END_OF_LIST(),
1121 };
1122
1123 static void fw_cfg_mem_realize(DeviceState *dev, Error **errp)
1124 {
1125 FWCfgMemState *s = FW_CFG_MEM(dev);
1126 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1127 const MemoryRegionOps *data_ops = &fw_cfg_data_mem_ops;
1128 Error *local_err = NULL;
1129
1130 fw_cfg_file_slots_allocate(FW_CFG(s), &local_err);
1131 if (local_err) {
1132 error_propagate(errp, local_err);
1133 return;
1134 }
1135
1136 memory_region_init_io(&s->ctl_iomem, OBJECT(s), &fw_cfg_ctl_mem_ops,
1137 FW_CFG(s), "fwcfg.ctl", FW_CFG_CTL_SIZE);
1138 sysbus_init_mmio(sbd, &s->ctl_iomem);
1139
1140 if (s->data_width > data_ops->valid.max_access_size) {
1141 /* memberwise copy because the "old_mmio" member is const */
1142 s->wide_data_ops.read = data_ops->read;
1143 s->wide_data_ops.write = data_ops->write;
1144 s->wide_data_ops.endianness = data_ops->endianness;
1145 s->wide_data_ops.valid = data_ops->valid;
1146 s->wide_data_ops.impl = data_ops->impl;
1147
1148 s->wide_data_ops.valid.max_access_size = s->data_width;
1149 s->wide_data_ops.impl.max_access_size = s->data_width;
1150 data_ops = &s->wide_data_ops;
1151 }
1152 memory_region_init_io(&s->data_iomem, OBJECT(s), data_ops, FW_CFG(s),
1153 "fwcfg.data", data_ops->valid.max_access_size);
1154 sysbus_init_mmio(sbd, &s->data_iomem);
1155
1156 if (FW_CFG(s)->dma_enabled) {
1157 memory_region_init_io(&FW_CFG(s)->dma_iomem, OBJECT(s),
1158 &fw_cfg_dma_mem_ops, FW_CFG(s), "fwcfg.dma",
1159 sizeof(dma_addr_t));
1160 sysbus_init_mmio(sbd, &FW_CFG(s)->dma_iomem);
1161 }
1162 }
1163
1164 static void fw_cfg_mem_class_init(ObjectClass *klass, void *data)
1165 {
1166 DeviceClass *dc = DEVICE_CLASS(klass);
1167
1168 dc->realize = fw_cfg_mem_realize;
1169 dc->props = fw_cfg_mem_properties;
1170 }
1171
1172 static const TypeInfo fw_cfg_mem_info = {
1173 .name = TYPE_FW_CFG_MEM,
1174 .parent = TYPE_FW_CFG,
1175 .instance_size = sizeof(FWCfgMemState),
1176 .class_init = fw_cfg_mem_class_init,
1177 };
1178
1179
1180 static void fw_cfg_register_types(void)
1181 {
1182 type_register_static(&fw_cfg_info);
1183 type_register_static(&fw_cfg_io_info);
1184 type_register_static(&fw_cfg_mem_info);
1185 }
1186
1187 type_init(fw_cfg_register_types)