sm501: Add missing arbitration control register
[qemu.git] / hw / nvram / mac_nvram.c
1 /*
2 * PowerMac NVRAM emulation
3 *
4 * Copyright (c) 2005-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 #include "qemu/osdep.h"
26 #include "hw/hw.h"
27 #include "hw/nvram/chrp_nvram.h"
28 #include "hw/ppc/mac.h"
29 #include "qemu/cutils.h"
30 #include <zlib.h>
31
32 /* debug NVR */
33 //#define DEBUG_NVR
34
35 #ifdef DEBUG_NVR
36 #define NVR_DPRINTF(fmt, ...) \
37 do { printf("NVR: " fmt , ## __VA_ARGS__); } while (0)
38 #else
39 #define NVR_DPRINTF(fmt, ...)
40 #endif
41
42 #define DEF_SYSTEM_SIZE 0xc10
43
44 /* macio style NVRAM device */
45 static void macio_nvram_writeb(void *opaque, hwaddr addr,
46 uint64_t value, unsigned size)
47 {
48 MacIONVRAMState *s = opaque;
49
50 addr = (addr >> s->it_shift) & (s->size - 1);
51 s->data[addr] = value;
52 NVR_DPRINTF("writeb addr %04" HWADDR_PRIx " val %" PRIx64 "\n",
53 addr, value);
54 }
55
56 static uint64_t macio_nvram_readb(void *opaque, hwaddr addr,
57 unsigned size)
58 {
59 MacIONVRAMState *s = opaque;
60 uint32_t value;
61
62 addr = (addr >> s->it_shift) & (s->size - 1);
63 value = s->data[addr];
64 NVR_DPRINTF("readb addr %04" HWADDR_PRIx " val %" PRIx32 "\n",
65 addr, value);
66
67 return value;
68 }
69
70 static const MemoryRegionOps macio_nvram_ops = {
71 .read = macio_nvram_readb,
72 .write = macio_nvram_writeb,
73 .valid.min_access_size = 1,
74 .valid.max_access_size = 4,
75 .impl.min_access_size = 1,
76 .impl.max_access_size = 1,
77 .endianness = DEVICE_BIG_ENDIAN,
78 };
79
80 static const VMStateDescription vmstate_macio_nvram = {
81 .name = "macio_nvram",
82 .version_id = 1,
83 .minimum_version_id = 1,
84 .fields = (VMStateField[]) {
85 VMSTATE_VBUFFER_UINT32(data, MacIONVRAMState, 0, NULL, size),
86 VMSTATE_END_OF_LIST()
87 }
88 };
89
90
91 static void macio_nvram_reset(DeviceState *dev)
92 {
93 }
94
95 static void macio_nvram_realizefn(DeviceState *dev, Error **errp)
96 {
97 SysBusDevice *d = SYS_BUS_DEVICE(dev);
98 MacIONVRAMState *s = MACIO_NVRAM(dev);
99
100 s->data = g_malloc0(s->size);
101
102 memory_region_init_io(&s->mem, OBJECT(s), &macio_nvram_ops, s,
103 "macio-nvram", s->size << s->it_shift);
104 sysbus_init_mmio(d, &s->mem);
105 }
106
107 static void macio_nvram_unrealizefn(DeviceState *dev, Error **errp)
108 {
109 MacIONVRAMState *s = MACIO_NVRAM(dev);
110
111 g_free(s->data);
112 }
113
114 static Property macio_nvram_properties[] = {
115 DEFINE_PROP_UINT32("size", MacIONVRAMState, size, 0),
116 DEFINE_PROP_UINT32("it_shift", MacIONVRAMState, it_shift, 0),
117 DEFINE_PROP_END_OF_LIST()
118 };
119
120 static void macio_nvram_class_init(ObjectClass *oc, void *data)
121 {
122 DeviceClass *dc = DEVICE_CLASS(oc);
123
124 dc->realize = macio_nvram_realizefn;
125 dc->unrealize = macio_nvram_unrealizefn;
126 dc->reset = macio_nvram_reset;
127 dc->vmsd = &vmstate_macio_nvram;
128 dc->props = macio_nvram_properties;
129 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
130 }
131
132 static const TypeInfo macio_nvram_type_info = {
133 .name = TYPE_MACIO_NVRAM,
134 .parent = TYPE_SYS_BUS_DEVICE,
135 .instance_size = sizeof(MacIONVRAMState),
136 .class_init = macio_nvram_class_init,
137 };
138
139 static void macio_nvram_register_types(void)
140 {
141 type_register_static(&macio_nvram_type_info);
142 }
143
144 /* Set up a system OpenBIOS NVRAM partition */
145 static void pmac_format_nvram_partition_of(MacIONVRAMState *nvr, int off,
146 int len)
147 {
148 int sysp_end;
149
150 /* OpenBIOS nvram variables partition */
151 sysp_end = chrp_nvram_create_system_partition(&nvr->data[off],
152 DEF_SYSTEM_SIZE) + off;
153
154 /* Free space partition */
155 chrp_nvram_create_free_partition(&nvr->data[sysp_end], len - sysp_end);
156 }
157
158 #define OSX_NVRAM_SIGNATURE (0x5A)
159
160 /* Set up a Mac OS X NVRAM partition */
161 static void pmac_format_nvram_partition_osx(MacIONVRAMState *nvr, int off,
162 int len)
163 {
164 uint32_t start = off;
165 ChrpNvramPartHdr *part_header;
166 unsigned char *data = &nvr->data[start];
167
168 /* empty partition */
169 part_header = (ChrpNvramPartHdr *)data;
170 part_header->signature = OSX_NVRAM_SIGNATURE;
171 pstrcpy(part_header->name, sizeof(part_header->name), "wwwwwwwwwwww");
172
173 chrp_nvram_finish_partition(part_header, len);
174
175 /* Generation */
176 stl_be_p(&data[20], 2);
177
178 /* Adler32 checksum */
179 stl_be_p(&data[16], adler32(0, &data[20], len - 20));
180 }
181
182 /* Set up NVRAM with OF and OSX partitions */
183 void pmac_format_nvram_partition(MacIONVRAMState *nvr, int len)
184 {
185 /*
186 * Mac OS X expects side "B" of the flash at the second half of NVRAM,
187 * so we use half of the chip for OF and the other half for a free OSX
188 * partition.
189 */
190 pmac_format_nvram_partition_of(nvr, 0, len / 2);
191 pmac_format_nvram_partition_osx(nvr, len / 2, len / 2);
192 }
193 type_init(macio_nvram_register_types)