x86: move cpu hotplug from pc to x86
[qemu.git] / hw / nvram / spapr_nvram.c
1 /*
2 * QEMU sPAPR NVRAM emulation
3 *
4 * Copyright (C) 2012 David Gibson, IBM Corporation.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/module.h"
27 #include "qemu/units.h"
28 #include "qapi/error.h"
29 #include "cpu.h"
30 #include <libfdt.h>
31
32 #include "sysemu/block-backend.h"
33 #include "sysemu/device_tree.h"
34 #include "sysemu/sysemu.h"
35 #include "sysemu/runstate.h"
36 #include "hw/sysbus.h"
37 #include "migration/vmstate.h"
38 #include "hw/nvram/chrp_nvram.h"
39 #include "hw/ppc/spapr.h"
40 #include "hw/ppc/spapr_vio.h"
41 #include "hw/qdev-properties.h"
42 #include "qom/object.h"
43
44 struct SpaprNvram {
45 SpaprVioDevice sdev;
46 uint32_t size;
47 uint8_t *buf;
48 BlockBackend *blk;
49 VMChangeStateEntry *vmstate;
50 };
51 typedef struct SpaprNvram SpaprNvram;
52
53 #define TYPE_VIO_SPAPR_NVRAM "spapr-nvram"
54 DECLARE_INSTANCE_CHECKER(SpaprNvram, VIO_SPAPR_NVRAM,
55 TYPE_VIO_SPAPR_NVRAM)
56
57 #define MIN_NVRAM_SIZE (8 * KiB)
58 #define DEFAULT_NVRAM_SIZE (64 * KiB)
59 #define MAX_NVRAM_SIZE (1 * MiB)
60
61 static void rtas_nvram_fetch(PowerPCCPU *cpu, SpaprMachineState *spapr,
62 uint32_t token, uint32_t nargs,
63 target_ulong args,
64 uint32_t nret, target_ulong rets)
65 {
66 SpaprNvram *nvram = spapr->nvram;
67 hwaddr offset, buffer, len;
68 void *membuf;
69
70 if ((nargs != 3) || (nret != 2)) {
71 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
72 return;
73 }
74
75 if (!nvram) {
76 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
77 rtas_st(rets, 1, 0);
78 return;
79 }
80
81 offset = rtas_ld(args, 0);
82 buffer = rtas_ld(args, 1);
83 len = rtas_ld(args, 2);
84
85 if (((offset + len) < offset)
86 || ((offset + len) > nvram->size)) {
87 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
88 rtas_st(rets, 1, 0);
89 return;
90 }
91
92 assert(nvram->buf);
93
94 membuf = cpu_physical_memory_map(buffer, &len, true);
95 memcpy(membuf, nvram->buf + offset, len);
96 cpu_physical_memory_unmap(membuf, len, 1, len);
97
98 rtas_st(rets, 0, RTAS_OUT_SUCCESS);
99 rtas_st(rets, 1, len);
100 }
101
102 static void rtas_nvram_store(PowerPCCPU *cpu, SpaprMachineState *spapr,
103 uint32_t token, uint32_t nargs,
104 target_ulong args,
105 uint32_t nret, target_ulong rets)
106 {
107 SpaprNvram *nvram = spapr->nvram;
108 hwaddr offset, buffer, len;
109 int alen;
110 void *membuf;
111
112 if ((nargs != 3) || (nret != 2)) {
113 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
114 return;
115 }
116
117 if (!nvram) {
118 rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
119 return;
120 }
121
122 offset = rtas_ld(args, 0);
123 buffer = rtas_ld(args, 1);
124 len = rtas_ld(args, 2);
125
126 if (((offset + len) < offset)
127 || ((offset + len) > nvram->size)) {
128 rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
129 return;
130 }
131
132 membuf = cpu_physical_memory_map(buffer, &len, false);
133
134 alen = len;
135 if (nvram->blk) {
136 alen = blk_pwrite(nvram->blk, offset, membuf, len, 0);
137 }
138
139 assert(nvram->buf);
140 memcpy(nvram->buf + offset, membuf, len);
141
142 cpu_physical_memory_unmap(membuf, len, 0, len);
143
144 rtas_st(rets, 0, (alen < len) ? RTAS_OUT_HW_ERROR : RTAS_OUT_SUCCESS);
145 rtas_st(rets, 1, (alen < 0) ? 0 : alen);
146 }
147
148 static void spapr_nvram_realize(SpaprVioDevice *dev, Error **errp)
149 {
150 SpaprNvram *nvram = VIO_SPAPR_NVRAM(dev);
151 int ret;
152
153 if (nvram->blk) {
154 int64_t len = blk_getlength(nvram->blk);
155
156 if (len < 0) {
157 error_setg_errno(errp, -len,
158 "could not get length of backing image");
159 return;
160 }
161
162 nvram->size = len;
163
164 ret = blk_set_perm(nvram->blk,
165 BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE,
166 BLK_PERM_ALL, errp);
167 if (ret < 0) {
168 return;
169 }
170 } else {
171 nvram->size = DEFAULT_NVRAM_SIZE;
172 }
173
174 nvram->buf = g_malloc0(nvram->size);
175
176 if ((nvram->size < MIN_NVRAM_SIZE) || (nvram->size > MAX_NVRAM_SIZE)) {
177 error_setg(errp,
178 "spapr-nvram must be between %" PRId64
179 " and %" PRId64 " bytes in size",
180 MIN_NVRAM_SIZE, MAX_NVRAM_SIZE);
181 return;
182 }
183
184 if (nvram->blk) {
185 int alen = blk_pread(nvram->blk, 0, nvram->buf, nvram->size);
186
187 if (alen != nvram->size) {
188 error_setg(errp, "can't read spapr-nvram contents");
189 return;
190 }
191 } else if (nb_prom_envs > 0) {
192 /* Create a system partition to pass the -prom-env variables */
193 chrp_nvram_create_system_partition(nvram->buf, MIN_NVRAM_SIZE / 4,
194 nvram->size);
195 chrp_nvram_create_free_partition(&nvram->buf[MIN_NVRAM_SIZE / 4],
196 nvram->size - MIN_NVRAM_SIZE / 4);
197 }
198
199 spapr_rtas_register(RTAS_NVRAM_FETCH, "nvram-fetch", rtas_nvram_fetch);
200 spapr_rtas_register(RTAS_NVRAM_STORE, "nvram-store", rtas_nvram_store);
201 }
202
203 static int spapr_nvram_devnode(SpaprVioDevice *dev, void *fdt, int node_off)
204 {
205 SpaprNvram *nvram = VIO_SPAPR_NVRAM(dev);
206
207 return fdt_setprop_cell(fdt, node_off, "#bytes", nvram->size);
208 }
209
210 static int spapr_nvram_pre_load(void *opaque)
211 {
212 SpaprNvram *nvram = VIO_SPAPR_NVRAM(opaque);
213
214 g_free(nvram->buf);
215 nvram->buf = NULL;
216 nvram->size = 0;
217
218 return 0;
219 }
220
221 static void postload_update_cb(void *opaque, int running, RunState state)
222 {
223 SpaprNvram *nvram = opaque;
224
225 /* This is called after bdrv_invalidate_cache_all. */
226
227 qemu_del_vm_change_state_handler(nvram->vmstate);
228 nvram->vmstate = NULL;
229
230 blk_pwrite(nvram->blk, 0, nvram->buf, nvram->size, 0);
231 }
232
233 static int spapr_nvram_post_load(void *opaque, int version_id)
234 {
235 SpaprNvram *nvram = VIO_SPAPR_NVRAM(opaque);
236
237 if (nvram->blk) {
238 nvram->vmstate = qemu_add_vm_change_state_handler(postload_update_cb,
239 nvram);
240 }
241
242 return 0;
243 }
244
245 static const VMStateDescription vmstate_spapr_nvram = {
246 .name = "spapr_nvram",
247 .version_id = 1,
248 .minimum_version_id = 1,
249 .pre_load = spapr_nvram_pre_load,
250 .post_load = spapr_nvram_post_load,
251 .fields = (VMStateField[]) {
252 VMSTATE_UINT32(size, SpaprNvram),
253 VMSTATE_VBUFFER_ALLOC_UINT32(buf, SpaprNvram, 1, NULL, size),
254 VMSTATE_END_OF_LIST()
255 },
256 };
257
258 static Property spapr_nvram_properties[] = {
259 DEFINE_SPAPR_PROPERTIES(SpaprNvram, sdev),
260 DEFINE_PROP_DRIVE("drive", SpaprNvram, blk),
261 DEFINE_PROP_END_OF_LIST(),
262 };
263
264 static void spapr_nvram_class_init(ObjectClass *klass, void *data)
265 {
266 DeviceClass *dc = DEVICE_CLASS(klass);
267 SpaprVioDeviceClass *k = VIO_SPAPR_DEVICE_CLASS(klass);
268
269 k->realize = spapr_nvram_realize;
270 k->devnode = spapr_nvram_devnode;
271 k->dt_name = "nvram";
272 k->dt_type = "nvram";
273 k->dt_compatible = "qemu,spapr-nvram";
274 set_bit(DEVICE_CATEGORY_MISC, dc->categories);
275 device_class_set_props(dc, spapr_nvram_properties);
276 dc->vmsd = &vmstate_spapr_nvram;
277 /* Reason: Internal device only, uses spapr_rtas_register() in realize() */
278 dc->user_creatable = false;
279 }
280
281 static const TypeInfo spapr_nvram_type_info = {
282 .name = TYPE_VIO_SPAPR_NVRAM,
283 .parent = TYPE_VIO_SPAPR_DEVICE,
284 .instance_size = sizeof(SpaprNvram),
285 .class_init = spapr_nvram_class_init,
286 };
287
288 static void spapr_nvram_register_types(void)
289 {
290 type_register_static(&spapr_nvram_type_info);
291 }
292
293 type_init(spapr_nvram_register_types)