PPC: e500: msync is 440 only, e500 has real sync
[qemu.git] / hw / omap_spi.c
1 /*
2 * TI OMAP processor's Multichannel SPI emulation.
3 *
4 * Copyright (C) 2007-2009 Nokia Corporation
5 *
6 * Original code for OMAP2 by Andrzej Zaborowski <andrew@openedhand.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 or
11 * (at your option) any later version of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 */
22 #include "hw.h"
23 #include "omap.h"
24
25 /* Multichannel SPI */
26 struct omap_mcspi_s {
27 MemoryRegion iomem;
28 qemu_irq irq;
29 int chnum;
30
31 uint32_t sysconfig;
32 uint32_t systest;
33 uint32_t irqst;
34 uint32_t irqen;
35 uint32_t wken;
36 uint32_t control;
37
38 struct omap_mcspi_ch_s {
39 qemu_irq txdrq;
40 qemu_irq rxdrq;
41 uint32_t (*txrx)(void *opaque, uint32_t, int);
42 void *opaque;
43
44 uint32_t tx;
45 uint32_t rx;
46
47 uint32_t config;
48 uint32_t status;
49 uint32_t control;
50 } ch[4];
51 };
52
53 static inline void omap_mcspi_interrupt_update(struct omap_mcspi_s *s)
54 {
55 qemu_set_irq(s->irq, s->irqst & s->irqen);
56 }
57
58 static inline void omap_mcspi_dmarequest_update(struct omap_mcspi_ch_s *ch)
59 {
60 qemu_set_irq(ch->txdrq,
61 (ch->control & 1) && /* EN */
62 (ch->config & (1 << 14)) && /* DMAW */
63 (ch->status & (1 << 1)) && /* TXS */
64 ((ch->config >> 12) & 3) != 1); /* TRM */
65 qemu_set_irq(ch->rxdrq,
66 (ch->control & 1) && /* EN */
67 (ch->config & (1 << 15)) && /* DMAW */
68 (ch->status & (1 << 0)) && /* RXS */
69 ((ch->config >> 12) & 3) != 2); /* TRM */
70 }
71
72 static void omap_mcspi_transfer_run(struct omap_mcspi_s *s, int chnum)
73 {
74 struct omap_mcspi_ch_s *ch = s->ch + chnum;
75
76 if (!(ch->control & 1)) /* EN */
77 return;
78 if ((ch->status & (1 << 0)) && /* RXS */
79 ((ch->config >> 12) & 3) != 2 && /* TRM */
80 !(ch->config & (1 << 19))) /* TURBO */
81 goto intr_update;
82 if ((ch->status & (1 << 1)) && /* TXS */
83 ((ch->config >> 12) & 3) != 1) /* TRM */
84 goto intr_update;
85
86 if (!(s->control & 1) || /* SINGLE */
87 (ch->config & (1 << 20))) { /* FORCE */
88 if (ch->txrx)
89 ch->rx = ch->txrx(ch->opaque, ch->tx, /* WL */
90 1 + (0x1f & (ch->config >> 7)));
91 }
92
93 ch->tx = 0;
94 ch->status |= 1 << 2; /* EOT */
95 ch->status |= 1 << 1; /* TXS */
96 if (((ch->config >> 12) & 3) != 2) /* TRM */
97 ch->status |= 1 << 0; /* RXS */
98
99 intr_update:
100 if ((ch->status & (1 << 0)) && /* RXS */
101 ((ch->config >> 12) & 3) != 2 && /* TRM */
102 !(ch->config & (1 << 19))) /* TURBO */
103 s->irqst |= 1 << (2 + 4 * chnum); /* RX_FULL */
104 if ((ch->status & (1 << 1)) && /* TXS */
105 ((ch->config >> 12) & 3) != 1) /* TRM */
106 s->irqst |= 1 << (0 + 4 * chnum); /* TX_EMPTY */
107 omap_mcspi_interrupt_update(s);
108 omap_mcspi_dmarequest_update(ch);
109 }
110
111 void omap_mcspi_reset(struct omap_mcspi_s *s)
112 {
113 int ch;
114
115 s->sysconfig = 0;
116 s->systest = 0;
117 s->irqst = 0;
118 s->irqen = 0;
119 s->wken = 0;
120 s->control = 4;
121
122 for (ch = 0; ch < 4; ch ++) {
123 s->ch[ch].config = 0x060000;
124 s->ch[ch].status = 2; /* TXS */
125 s->ch[ch].control = 0;
126
127 omap_mcspi_dmarequest_update(s->ch + ch);
128 }
129
130 omap_mcspi_interrupt_update(s);
131 }
132
133 static uint64_t omap_mcspi_read(void *opaque, target_phys_addr_t addr,
134 unsigned size)
135 {
136 struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
137 int ch = 0;
138 uint32_t ret;
139
140 if (size != 4) {
141 return omap_badwidth_read32(opaque, addr);
142 }
143
144 switch (addr) {
145 case 0x00: /* MCSPI_REVISION */
146 return 0x91;
147
148 case 0x10: /* MCSPI_SYSCONFIG */
149 return s->sysconfig;
150
151 case 0x14: /* MCSPI_SYSSTATUS */
152 return 1; /* RESETDONE */
153
154 case 0x18: /* MCSPI_IRQSTATUS */
155 return s->irqst;
156
157 case 0x1c: /* MCSPI_IRQENABLE */
158 return s->irqen;
159
160 case 0x20: /* MCSPI_WAKEUPENABLE */
161 return s->wken;
162
163 case 0x24: /* MCSPI_SYST */
164 return s->systest;
165
166 case 0x28: /* MCSPI_MODULCTRL */
167 return s->control;
168
169 case 0x68: ch ++;
170 case 0x54: ch ++;
171 case 0x40: ch ++;
172 case 0x2c: /* MCSPI_CHCONF */
173 return s->ch[ch].config;
174
175 case 0x6c: ch ++;
176 case 0x58: ch ++;
177 case 0x44: ch ++;
178 case 0x30: /* MCSPI_CHSTAT */
179 return s->ch[ch].status;
180
181 case 0x70: ch ++;
182 case 0x5c: ch ++;
183 case 0x48: ch ++;
184 case 0x34: /* MCSPI_CHCTRL */
185 return s->ch[ch].control;
186
187 case 0x74: ch ++;
188 case 0x60: ch ++;
189 case 0x4c: ch ++;
190 case 0x38: /* MCSPI_TX */
191 return s->ch[ch].tx;
192
193 case 0x78: ch ++;
194 case 0x64: ch ++;
195 case 0x50: ch ++;
196 case 0x3c: /* MCSPI_RX */
197 s->ch[ch].status &= ~(1 << 0); /* RXS */
198 ret = s->ch[ch].rx;
199 omap_mcspi_transfer_run(s, ch);
200 return ret;
201 }
202
203 OMAP_BAD_REG(addr);
204 return 0;
205 }
206
207 static void omap_mcspi_write(void *opaque, target_phys_addr_t addr,
208 uint64_t value, unsigned size)
209 {
210 struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
211 int ch = 0;
212
213 if (size != 4) {
214 return omap_badwidth_write32(opaque, addr, value);
215 }
216
217 switch (addr) {
218 case 0x00: /* MCSPI_REVISION */
219 case 0x14: /* MCSPI_SYSSTATUS */
220 case 0x30: /* MCSPI_CHSTAT0 */
221 case 0x3c: /* MCSPI_RX0 */
222 case 0x44: /* MCSPI_CHSTAT1 */
223 case 0x50: /* MCSPI_RX1 */
224 case 0x58: /* MCSPI_CHSTAT2 */
225 case 0x64: /* MCSPI_RX2 */
226 case 0x6c: /* MCSPI_CHSTAT3 */
227 case 0x78: /* MCSPI_RX3 */
228 OMAP_RO_REG(addr);
229 return;
230
231 case 0x10: /* MCSPI_SYSCONFIG */
232 if (value & (1 << 1)) /* SOFTRESET */
233 omap_mcspi_reset(s);
234 s->sysconfig = value & 0x31d;
235 break;
236
237 case 0x18: /* MCSPI_IRQSTATUS */
238 if (!((s->control & (1 << 3)) && (s->systest & (1 << 11)))) {
239 s->irqst &= ~value;
240 omap_mcspi_interrupt_update(s);
241 }
242 break;
243
244 case 0x1c: /* MCSPI_IRQENABLE */
245 s->irqen = value & 0x1777f;
246 omap_mcspi_interrupt_update(s);
247 break;
248
249 case 0x20: /* MCSPI_WAKEUPENABLE */
250 s->wken = value & 1;
251 break;
252
253 case 0x24: /* MCSPI_SYST */
254 if (s->control & (1 << 3)) /* SYSTEM_TEST */
255 if (value & (1 << 11)) { /* SSB */
256 s->irqst |= 0x1777f;
257 omap_mcspi_interrupt_update(s);
258 }
259 s->systest = value & 0xfff;
260 break;
261
262 case 0x28: /* MCSPI_MODULCTRL */
263 if (value & (1 << 3)) /* SYSTEM_TEST */
264 if (s->systest & (1 << 11)) { /* SSB */
265 s->irqst |= 0x1777f;
266 omap_mcspi_interrupt_update(s);
267 }
268 s->control = value & 0xf;
269 break;
270
271 case 0x68: ch ++;
272 case 0x54: ch ++;
273 case 0x40: ch ++;
274 case 0x2c: /* MCSPI_CHCONF */
275 if ((value ^ s->ch[ch].config) & (3 << 14)) /* DMAR | DMAW */
276 omap_mcspi_dmarequest_update(s->ch + ch);
277 if (((value >> 12) & 3) == 3) /* TRM */
278 fprintf(stderr, "%s: invalid TRM value (3)\n", __FUNCTION__);
279 if (((value >> 7) & 0x1f) < 3) /* WL */
280 fprintf(stderr, "%s: invalid WL value (%" PRIx64 ")\n",
281 __FUNCTION__, (value >> 7) & 0x1f);
282 s->ch[ch].config = value & 0x7fffff;
283 break;
284
285 case 0x70: ch ++;
286 case 0x5c: ch ++;
287 case 0x48: ch ++;
288 case 0x34: /* MCSPI_CHCTRL */
289 if (value & ~s->ch[ch].control & 1) { /* EN */
290 s->ch[ch].control |= 1;
291 omap_mcspi_transfer_run(s, ch);
292 } else
293 s->ch[ch].control = value & 1;
294 break;
295
296 case 0x74: ch ++;
297 case 0x60: ch ++;
298 case 0x4c: ch ++;
299 case 0x38: /* MCSPI_TX */
300 s->ch[ch].tx = value;
301 s->ch[ch].status &= ~(1 << 1); /* TXS */
302 omap_mcspi_transfer_run(s, ch);
303 break;
304
305 default:
306 OMAP_BAD_REG(addr);
307 return;
308 }
309 }
310
311 static const MemoryRegionOps omap_mcspi_ops = {
312 .read = omap_mcspi_read,
313 .write = omap_mcspi_write,
314 .endianness = DEVICE_NATIVE_ENDIAN,
315 };
316
317 struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
318 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
319 {
320 struct omap_mcspi_s *s = (struct omap_mcspi_s *)
321 g_malloc0(sizeof(struct omap_mcspi_s));
322 struct omap_mcspi_ch_s *ch = s->ch;
323
324 s->irq = irq;
325 s->chnum = chnum;
326 while (chnum --) {
327 ch->txdrq = *drq ++;
328 ch->rxdrq = *drq ++;
329 ch ++;
330 }
331 omap_mcspi_reset(s);
332
333 memory_region_init_io(&s->iomem, &omap_mcspi_ops, s, "omap.mcspi",
334 omap_l4_region_size(ta, 0));
335 omap_l4_attach(ta, 0, &s->iomem);
336
337 return s;
338 }
339
340 void omap_mcspi_attach(struct omap_mcspi_s *s,
341 uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque,
342 int chipselect)
343 {
344 if (chipselect < 0 || chipselect >= s->chnum)
345 hw_error("%s: Bad chipselect %i\n", __FUNCTION__, chipselect);
346
347 s->ch[chipselect].txrx = txrx;
348 s->ch[chipselect].opaque = opaque;
349 }