meson: convert hw/9pfs, cleanup
[qemu.git] / hw / openrisc / openrisc_sim.c
1 /*
2 * OpenRISC simulator for use as an IIS.
3 *
4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
5 * Feng Gao <gf91597@gmail.com>
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "qemu/error-report.h"
23 #include "qapi/error.h"
24 #include "cpu.h"
25 #include "hw/irq.h"
26 #include "hw/boards.h"
27 #include "elf.h"
28 #include "hw/char/serial.h"
29 #include "net/net.h"
30 #include "hw/loader.h"
31 #include "hw/qdev-properties.h"
32 #include "exec/address-spaces.h"
33 #include "sysemu/sysemu.h"
34 #include "hw/sysbus.h"
35 #include "sysemu/qtest.h"
36 #include "sysemu/reset.h"
37
38 #define KERNEL_LOAD_ADDR 0x100
39
40 static struct openrisc_boot_info {
41 uint32_t bootstrap_pc;
42 } boot_info;
43
44 static void main_cpu_reset(void *opaque)
45 {
46 OpenRISCCPU *cpu = opaque;
47 CPUState *cs = CPU(cpu);
48
49 cpu_reset(CPU(cpu));
50
51 cpu_set_pc(cs, boot_info.bootstrap_pc);
52 }
53
54 static void openrisc_sim_net_init(hwaddr base, hwaddr descriptors,
55 int num_cpus, qemu_irq **cpu_irqs,
56 int irq_pin, NICInfo *nd)
57 {
58 DeviceState *dev;
59 SysBusDevice *s;
60 int i;
61
62 dev = qdev_new("open_eth");
63 qdev_set_nic_properties(dev, nd);
64
65 s = SYS_BUS_DEVICE(dev);
66 sysbus_realize_and_unref(s, &error_fatal);
67 for (i = 0; i < num_cpus; i++) {
68 sysbus_connect_irq(s, 0, cpu_irqs[i][irq_pin]);
69 }
70 sysbus_mmio_map(s, 0, base);
71 sysbus_mmio_map(s, 1, descriptors);
72 }
73
74 static void openrisc_sim_ompic_init(hwaddr base, int num_cpus,
75 qemu_irq **cpu_irqs, int irq_pin)
76 {
77 DeviceState *dev;
78 SysBusDevice *s;
79 int i;
80
81 dev = qdev_new("or1k-ompic");
82 qdev_prop_set_uint32(dev, "num-cpus", num_cpus);
83
84 s = SYS_BUS_DEVICE(dev);
85 sysbus_realize_and_unref(s, &error_fatal);
86 for (i = 0; i < num_cpus; i++) {
87 sysbus_connect_irq(s, i, cpu_irqs[i][irq_pin]);
88 }
89 sysbus_mmio_map(s, 0, base);
90 }
91
92 static void openrisc_load_kernel(ram_addr_t ram_size,
93 const char *kernel_filename)
94 {
95 long kernel_size;
96 uint64_t elf_entry;
97 hwaddr entry;
98
99 if (kernel_filename && !qtest_enabled()) {
100 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
101 &elf_entry, NULL, NULL, NULL, 1, EM_OPENRISC,
102 1, 0);
103 entry = elf_entry;
104 if (kernel_size < 0) {
105 kernel_size = load_uimage(kernel_filename,
106 &entry, NULL, NULL, NULL, NULL);
107 }
108 if (kernel_size < 0) {
109 kernel_size = load_image_targphys(kernel_filename,
110 KERNEL_LOAD_ADDR,
111 ram_size - KERNEL_LOAD_ADDR);
112 }
113
114 if (entry <= 0) {
115 entry = KERNEL_LOAD_ADDR;
116 }
117
118 if (kernel_size < 0) {
119 error_report("couldn't load the kernel '%s'", kernel_filename);
120 exit(1);
121 }
122 boot_info.bootstrap_pc = entry;
123 }
124 }
125
126 static void openrisc_sim_init(MachineState *machine)
127 {
128 ram_addr_t ram_size = machine->ram_size;
129 const char *kernel_filename = machine->kernel_filename;
130 OpenRISCCPU *cpu = NULL;
131 MemoryRegion *ram;
132 qemu_irq *cpu_irqs[2];
133 qemu_irq serial_irq;
134 int n;
135 unsigned int smp_cpus = machine->smp.cpus;
136
137 assert(smp_cpus >= 1 && smp_cpus <= 2);
138 for (n = 0; n < smp_cpus; n++) {
139 cpu = OPENRISC_CPU(cpu_create(machine->cpu_type));
140 if (cpu == NULL) {
141 fprintf(stderr, "Unable to find CPU definition!\n");
142 exit(1);
143 }
144 cpu_openrisc_pic_init(cpu);
145 cpu_irqs[n] = (qemu_irq *) cpu->env.irq;
146
147 cpu_openrisc_clock_init(cpu);
148
149 qemu_register_reset(main_cpu_reset, cpu);
150 }
151
152 ram = g_malloc(sizeof(*ram));
153 memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_fatal);
154 memory_region_add_subregion(get_system_memory(), 0, ram);
155
156 if (nd_table[0].used) {
157 openrisc_sim_net_init(0x92000000, 0x92000400, smp_cpus,
158 cpu_irqs, 4, nd_table);
159 }
160
161 if (smp_cpus > 1) {
162 openrisc_sim_ompic_init(0x98000000, smp_cpus, cpu_irqs, 1);
163
164 serial_irq = qemu_irq_split(cpu_irqs[0][2], cpu_irqs[1][2]);
165 } else {
166 serial_irq = cpu_irqs[0][2];
167 }
168
169 serial_mm_init(get_system_memory(), 0x90000000, 0, serial_irq,
170 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
171
172 openrisc_load_kernel(ram_size, kernel_filename);
173 }
174
175 static void openrisc_sim_machine_init(MachineClass *mc)
176 {
177 mc->desc = "or1k simulation";
178 mc->init = openrisc_sim_init;
179 mc->max_cpus = 2;
180 mc->is_default = true;
181 mc->default_cpu_type = OPENRISC_CPU_TYPE_NAME("or1200");
182 }
183
184 DEFINE_MACHINE("or1k-sim", openrisc_sim_machine_init)