qdev: don't access name through info
[qemu.git] / hw / pc.c
1 /*
2 * QEMU PC System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "pc.h"
26 #include "apic.h"
27 #include "fdc.h"
28 #include "ide.h"
29 #include "pci.h"
30 #include "vmware_vga.h"
31 #include "monitor.h"
32 #include "fw_cfg.h"
33 #include "hpet_emul.h"
34 #include "smbios.h"
35 #include "loader.h"
36 #include "elf.h"
37 #include "multiboot.h"
38 #include "mc146818rtc.h"
39 #include "msi.h"
40 #include "sysbus.h"
41 #include "sysemu.h"
42 #include "kvm.h"
43 #include "blockdev.h"
44 #include "ui/qemu-spice.h"
45 #include "memory.h"
46 #include "exec-memory.h"
47
48 /* output Bochs bios info messages */
49 //#define DEBUG_BIOS
50
51 /* debug PC/ISA interrupts */
52 //#define DEBUG_IRQ
53
54 #ifdef DEBUG_IRQ
55 #define DPRINTF(fmt, ...) \
56 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
57 #else
58 #define DPRINTF(fmt, ...)
59 #endif
60
61 #define BIOS_FILENAME "bios.bin"
62
63 #define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
64
65 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables. */
66 #define ACPI_DATA_SIZE 0x10000
67 #define BIOS_CFG_IOPORT 0x510
68 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
69 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
70 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
71 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
72 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
73
74 #define MSI_ADDR_BASE 0xfee00000
75
76 #define E820_NR_ENTRIES 16
77
78 struct e820_entry {
79 uint64_t address;
80 uint64_t length;
81 uint32_t type;
82 } QEMU_PACKED __attribute((__aligned__(4)));
83
84 struct e820_table {
85 uint32_t count;
86 struct e820_entry entry[E820_NR_ENTRIES];
87 } QEMU_PACKED __attribute((__aligned__(4)));
88
89 static struct e820_table e820_table;
90 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
91
92 void gsi_handler(void *opaque, int n, int level)
93 {
94 GSIState *s = opaque;
95
96 DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
97 if (n < ISA_NUM_IRQS) {
98 qemu_set_irq(s->i8259_irq[n], level);
99 }
100 qemu_set_irq(s->ioapic_irq[n], level);
101 }
102
103 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
104 {
105 }
106
107 /* MSDOS compatibility mode FPU exception support */
108 static qemu_irq ferr_irq;
109
110 void pc_register_ferr_irq(qemu_irq irq)
111 {
112 ferr_irq = irq;
113 }
114
115 /* XXX: add IGNNE support */
116 void cpu_set_ferr(CPUX86State *s)
117 {
118 qemu_irq_raise(ferr_irq);
119 }
120
121 static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
122 {
123 qemu_irq_lower(ferr_irq);
124 }
125
126 /* TSC handling */
127 uint64_t cpu_get_tsc(CPUX86State *env)
128 {
129 return cpu_get_ticks();
130 }
131
132 /* SMM support */
133
134 static cpu_set_smm_t smm_set;
135 static void *smm_arg;
136
137 void cpu_smm_register(cpu_set_smm_t callback, void *arg)
138 {
139 assert(smm_set == NULL);
140 assert(smm_arg == NULL);
141 smm_set = callback;
142 smm_arg = arg;
143 }
144
145 void cpu_smm_update(CPUState *env)
146 {
147 if (smm_set && smm_arg && env == first_cpu)
148 smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
149 }
150
151
152 /* IRQ handling */
153 int cpu_get_pic_interrupt(CPUState *env)
154 {
155 int intno;
156
157 intno = apic_get_interrupt(env->apic_state);
158 if (intno >= 0) {
159 return intno;
160 }
161 /* read the irq from the PIC */
162 if (!apic_accept_pic_intr(env->apic_state)) {
163 return -1;
164 }
165
166 intno = pic_read_irq(isa_pic);
167 return intno;
168 }
169
170 static void pic_irq_request(void *opaque, int irq, int level)
171 {
172 CPUState *env = first_cpu;
173
174 DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
175 if (env->apic_state) {
176 while (env) {
177 if (apic_accept_pic_intr(env->apic_state)) {
178 apic_deliver_pic_intr(env->apic_state, level);
179 }
180 env = env->next_cpu;
181 }
182 } else {
183 if (level)
184 cpu_interrupt(env, CPU_INTERRUPT_HARD);
185 else
186 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
187 }
188 }
189
190 /* PC cmos mappings */
191
192 #define REG_EQUIPMENT_BYTE 0x14
193
194 static int cmos_get_fd_drive_type(FDriveType fd0)
195 {
196 int val;
197
198 switch (fd0) {
199 case FDRIVE_DRV_144:
200 /* 1.44 Mb 3"5 drive */
201 val = 4;
202 break;
203 case FDRIVE_DRV_288:
204 /* 2.88 Mb 3"5 drive */
205 val = 5;
206 break;
207 case FDRIVE_DRV_120:
208 /* 1.2 Mb 5"5 drive */
209 val = 2;
210 break;
211 case FDRIVE_DRV_NONE:
212 default:
213 val = 0;
214 break;
215 }
216 return val;
217 }
218
219 static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd,
220 ISADevice *s)
221 {
222 int cylinders, heads, sectors;
223 bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
224 rtc_set_memory(s, type_ofs, 47);
225 rtc_set_memory(s, info_ofs, cylinders);
226 rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
227 rtc_set_memory(s, info_ofs + 2, heads);
228 rtc_set_memory(s, info_ofs + 3, 0xff);
229 rtc_set_memory(s, info_ofs + 4, 0xff);
230 rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
231 rtc_set_memory(s, info_ofs + 6, cylinders);
232 rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
233 rtc_set_memory(s, info_ofs + 8, sectors);
234 }
235
236 /* convert boot_device letter to something recognizable by the bios */
237 static int boot_device2nibble(char boot_device)
238 {
239 switch(boot_device) {
240 case 'a':
241 case 'b':
242 return 0x01; /* floppy boot */
243 case 'c':
244 return 0x02; /* hard drive boot */
245 case 'd':
246 return 0x03; /* CD-ROM boot */
247 case 'n':
248 return 0x04; /* Network boot */
249 }
250 return 0;
251 }
252
253 static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk)
254 {
255 #define PC_MAX_BOOT_DEVICES 3
256 int nbds, bds[3] = { 0, };
257 int i;
258
259 nbds = strlen(boot_device);
260 if (nbds > PC_MAX_BOOT_DEVICES) {
261 error_report("Too many boot devices for PC");
262 return(1);
263 }
264 for (i = 0; i < nbds; i++) {
265 bds[i] = boot_device2nibble(boot_device[i]);
266 if (bds[i] == 0) {
267 error_report("Invalid boot device for PC: '%c'",
268 boot_device[i]);
269 return(1);
270 }
271 }
272 rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
273 rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
274 return(0);
275 }
276
277 static int pc_boot_set(void *opaque, const char *boot_device)
278 {
279 return set_boot_dev(opaque, boot_device, 0);
280 }
281
282 typedef struct pc_cmos_init_late_arg {
283 ISADevice *rtc_state;
284 BusState *idebus0, *idebus1;
285 } pc_cmos_init_late_arg;
286
287 static void pc_cmos_init_late(void *opaque)
288 {
289 pc_cmos_init_late_arg *arg = opaque;
290 ISADevice *s = arg->rtc_state;
291 int val;
292 BlockDriverState *hd_table[4];
293 int i;
294
295 ide_get_bs(hd_table, arg->idebus0);
296 ide_get_bs(hd_table + 2, arg->idebus1);
297
298 rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
299 if (hd_table[0])
300 cmos_init_hd(0x19, 0x1b, hd_table[0], s);
301 if (hd_table[1])
302 cmos_init_hd(0x1a, 0x24, hd_table[1], s);
303
304 val = 0;
305 for (i = 0; i < 4; i++) {
306 if (hd_table[i]) {
307 int cylinders, heads, sectors, translation;
308 /* NOTE: bdrv_get_geometry_hint() returns the physical
309 geometry. It is always such that: 1 <= sects <= 63, 1
310 <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
311 geometry can be different if a translation is done. */
312 translation = bdrv_get_translation_hint(hd_table[i]);
313 if (translation == BIOS_ATA_TRANSLATION_AUTO) {
314 bdrv_get_geometry_hint(hd_table[i], &cylinders, &heads, &sectors);
315 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
316 /* No translation. */
317 translation = 0;
318 } else {
319 /* LBA translation. */
320 translation = 1;
321 }
322 } else {
323 translation--;
324 }
325 val |= translation << (i * 2);
326 }
327 }
328 rtc_set_memory(s, 0x39, val);
329
330 qemu_unregister_reset(pc_cmos_init_late, opaque);
331 }
332
333 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
334 const char *boot_device,
335 ISADevice *floppy, BusState *idebus0, BusState *idebus1,
336 ISADevice *s)
337 {
338 int val, nb, nb_heads, max_track, last_sect, i;
339 FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE };
340 BlockDriverState *fd[MAX_FD];
341 static pc_cmos_init_late_arg arg;
342
343 /* various important CMOS locations needed by PC/Bochs bios */
344
345 /* memory size */
346 val = 640; /* base memory in K */
347 rtc_set_memory(s, 0x15, val);
348 rtc_set_memory(s, 0x16, val >> 8);
349
350 val = (ram_size / 1024) - 1024;
351 if (val > 65535)
352 val = 65535;
353 rtc_set_memory(s, 0x17, val);
354 rtc_set_memory(s, 0x18, val >> 8);
355 rtc_set_memory(s, 0x30, val);
356 rtc_set_memory(s, 0x31, val >> 8);
357
358 if (above_4g_mem_size) {
359 rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
360 rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
361 rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
362 }
363
364 if (ram_size > (16 * 1024 * 1024))
365 val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
366 else
367 val = 0;
368 if (val > 65535)
369 val = 65535;
370 rtc_set_memory(s, 0x34, val);
371 rtc_set_memory(s, 0x35, val >> 8);
372
373 /* set the number of CPU */
374 rtc_set_memory(s, 0x5f, smp_cpus - 1);
375
376 /* set boot devices, and disable floppy signature check if requested */
377 if (set_boot_dev(s, boot_device, fd_bootchk)) {
378 exit(1);
379 }
380
381 /* floppy type */
382 if (floppy) {
383 fdc_get_bs(fd, floppy);
384 for (i = 0; i < 2; i++) {
385 if (fd[i] && bdrv_is_inserted(fd[i])) {
386 bdrv_get_floppy_geometry_hint(fd[i], &nb_heads, &max_track,
387 &last_sect, FDRIVE_DRV_NONE,
388 &fd_type[i]);
389 }
390 }
391 }
392 val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
393 cmos_get_fd_drive_type(fd_type[1]);
394 rtc_set_memory(s, 0x10, val);
395
396 val = 0;
397 nb = 0;
398 if (fd_type[0] < FDRIVE_DRV_NONE) {
399 nb++;
400 }
401 if (fd_type[1] < FDRIVE_DRV_NONE) {
402 nb++;
403 }
404 switch (nb) {
405 case 0:
406 break;
407 case 1:
408 val |= 0x01; /* 1 drive, ready for boot */
409 break;
410 case 2:
411 val |= 0x41; /* 2 drives, ready for boot */
412 break;
413 }
414 val |= 0x02; /* FPU is there */
415 val |= 0x04; /* PS/2 mouse installed */
416 rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
417
418 /* hard drives */
419 arg.rtc_state = s;
420 arg.idebus0 = idebus0;
421 arg.idebus1 = idebus1;
422 qemu_register_reset(pc_cmos_init_late, &arg);
423 }
424
425 /* port 92 stuff: could be split off */
426 typedef struct Port92State {
427 ISADevice dev;
428 MemoryRegion io;
429 uint8_t outport;
430 qemu_irq *a20_out;
431 } Port92State;
432
433 static void port92_write(void *opaque, uint32_t addr, uint32_t val)
434 {
435 Port92State *s = opaque;
436
437 DPRINTF("port92: write 0x%02x\n", val);
438 s->outport = val;
439 qemu_set_irq(*s->a20_out, (val >> 1) & 1);
440 if (val & 1) {
441 qemu_system_reset_request();
442 }
443 }
444
445 static uint32_t port92_read(void *opaque, uint32_t addr)
446 {
447 Port92State *s = opaque;
448 uint32_t ret;
449
450 ret = s->outport;
451 DPRINTF("port92: read 0x%02x\n", ret);
452 return ret;
453 }
454
455 static void port92_init(ISADevice *dev, qemu_irq *a20_out)
456 {
457 Port92State *s = DO_UPCAST(Port92State, dev, dev);
458
459 s->a20_out = a20_out;
460 }
461
462 static const VMStateDescription vmstate_port92_isa = {
463 .name = "port92",
464 .version_id = 1,
465 .minimum_version_id = 1,
466 .minimum_version_id_old = 1,
467 .fields = (VMStateField []) {
468 VMSTATE_UINT8(outport, Port92State),
469 VMSTATE_END_OF_LIST()
470 }
471 };
472
473 static void port92_reset(DeviceState *d)
474 {
475 Port92State *s = container_of(d, Port92State, dev.qdev);
476
477 s->outport &= ~1;
478 }
479
480 static const MemoryRegionPortio port92_portio[] = {
481 { 0, 1, 1, .read = port92_read, .write = port92_write },
482 PORTIO_END_OF_LIST(),
483 };
484
485 static const MemoryRegionOps port92_ops = {
486 .old_portio = port92_portio
487 };
488
489 static int port92_initfn(ISADevice *dev)
490 {
491 Port92State *s = DO_UPCAST(Port92State, dev, dev);
492
493 memory_region_init_io(&s->io, &port92_ops, s, "port92", 1);
494 isa_register_ioport(dev, &s->io, 0x92);
495
496 s->outport = 0;
497 return 0;
498 }
499
500 static ISADeviceInfo port92_info = {
501 .qdev.name = "port92",
502 .qdev.size = sizeof(Port92State),
503 .qdev.vmsd = &vmstate_port92_isa,
504 .qdev.no_user = 1,
505 .qdev.reset = port92_reset,
506 .init = port92_initfn,
507 };
508
509 static void port92_register(void)
510 {
511 isa_qdev_register(&port92_info);
512 }
513 device_init(port92_register)
514
515 static void handle_a20_line_change(void *opaque, int irq, int level)
516 {
517 CPUState *cpu = opaque;
518
519 /* XXX: send to all CPUs ? */
520 /* XXX: add logic to handle multiple A20 line sources */
521 cpu_x86_set_a20(cpu, level);
522 }
523
524 /***********************************************************/
525 /* Bochs BIOS debug ports */
526
527 static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
528 {
529 static const char shutdown_str[8] = "Shutdown";
530 static int shutdown_index = 0;
531
532 switch(addr) {
533 /* Bochs BIOS messages */
534 case 0x400:
535 case 0x401:
536 /* used to be panic, now unused */
537 break;
538 case 0x402:
539 case 0x403:
540 #ifdef DEBUG_BIOS
541 fprintf(stderr, "%c", val);
542 #endif
543 break;
544 case 0x8900:
545 /* same as Bochs power off */
546 if (val == shutdown_str[shutdown_index]) {
547 shutdown_index++;
548 if (shutdown_index == 8) {
549 shutdown_index = 0;
550 qemu_system_shutdown_request();
551 }
552 } else {
553 shutdown_index = 0;
554 }
555 break;
556
557 /* LGPL'ed VGA BIOS messages */
558 case 0x501:
559 case 0x502:
560 exit((val << 1) | 1);
561 case 0x500:
562 case 0x503:
563 #ifdef DEBUG_BIOS
564 fprintf(stderr, "%c", val);
565 #endif
566 break;
567 }
568 }
569
570 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
571 {
572 int index = le32_to_cpu(e820_table.count);
573 struct e820_entry *entry;
574
575 if (index >= E820_NR_ENTRIES)
576 return -EBUSY;
577 entry = &e820_table.entry[index++];
578
579 entry->address = cpu_to_le64(address);
580 entry->length = cpu_to_le64(length);
581 entry->type = cpu_to_le32(type);
582
583 e820_table.count = cpu_to_le32(index);
584 return index;
585 }
586
587 static void *bochs_bios_init(void)
588 {
589 void *fw_cfg;
590 uint8_t *smbios_table;
591 size_t smbios_len;
592 uint64_t *numa_fw_cfg;
593 int i, j;
594
595 register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
596 register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
597 register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
598 register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
599 register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
600
601 register_ioport_write(0x501, 1, 1, bochs_bios_write, NULL);
602 register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
603 register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
604 register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
605 register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
606
607 fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
608
609 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
610 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
611 fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
612 acpi_tables_len);
613 fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
614
615 smbios_table = smbios_get_table(&smbios_len);
616 if (smbios_table)
617 fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
618 smbios_table, smbios_len);
619 fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table,
620 sizeof(struct e820_table));
621
622 fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, (uint8_t *)&hpet_cfg,
623 sizeof(struct hpet_fw_config));
624 /* allocate memory for the NUMA channel: one (64bit) word for the number
625 * of nodes, one word for each VCPU->node and one word for each node to
626 * hold the amount of memory.
627 */
628 numa_fw_cfg = g_malloc0((1 + max_cpus + nb_numa_nodes) * 8);
629 numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
630 for (i = 0; i < max_cpus; i++) {
631 for (j = 0; j < nb_numa_nodes; j++) {
632 if (node_cpumask[j] & (1 << i)) {
633 numa_fw_cfg[i + 1] = cpu_to_le64(j);
634 break;
635 }
636 }
637 }
638 for (i = 0; i < nb_numa_nodes; i++) {
639 numa_fw_cfg[max_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
640 }
641 fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
642 (1 + max_cpus + nb_numa_nodes) * 8);
643
644 return fw_cfg;
645 }
646
647 static long get_file_size(FILE *f)
648 {
649 long where, size;
650
651 /* XXX: on Unix systems, using fstat() probably makes more sense */
652
653 where = ftell(f);
654 fseek(f, 0, SEEK_END);
655 size = ftell(f);
656 fseek(f, where, SEEK_SET);
657
658 return size;
659 }
660
661 static void load_linux(void *fw_cfg,
662 const char *kernel_filename,
663 const char *initrd_filename,
664 const char *kernel_cmdline,
665 target_phys_addr_t max_ram_size)
666 {
667 uint16_t protocol;
668 int setup_size, kernel_size, initrd_size = 0, cmdline_size;
669 uint32_t initrd_max;
670 uint8_t header[8192], *setup, *kernel, *initrd_data;
671 target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
672 FILE *f;
673 char *vmode;
674
675 /* Align to 16 bytes as a paranoia measure */
676 cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
677
678 /* load the kernel header */
679 f = fopen(kernel_filename, "rb");
680 if (!f || !(kernel_size = get_file_size(f)) ||
681 fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
682 MIN(ARRAY_SIZE(header), kernel_size)) {
683 fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
684 kernel_filename, strerror(errno));
685 exit(1);
686 }
687
688 /* kernel protocol version */
689 #if 0
690 fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
691 #endif
692 if (ldl_p(header+0x202) == 0x53726448)
693 protocol = lduw_p(header+0x206);
694 else {
695 /* This looks like a multiboot kernel. If it is, let's stop
696 treating it like a Linux kernel. */
697 if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
698 kernel_cmdline, kernel_size, header))
699 return;
700 protocol = 0;
701 }
702
703 if (protocol < 0x200 || !(header[0x211] & 0x01)) {
704 /* Low kernel */
705 real_addr = 0x90000;
706 cmdline_addr = 0x9a000 - cmdline_size;
707 prot_addr = 0x10000;
708 } else if (protocol < 0x202) {
709 /* High but ancient kernel */
710 real_addr = 0x90000;
711 cmdline_addr = 0x9a000 - cmdline_size;
712 prot_addr = 0x100000;
713 } else {
714 /* High and recent kernel */
715 real_addr = 0x10000;
716 cmdline_addr = 0x20000;
717 prot_addr = 0x100000;
718 }
719
720 #if 0
721 fprintf(stderr,
722 "qemu: real_addr = 0x" TARGET_FMT_plx "\n"
723 "qemu: cmdline_addr = 0x" TARGET_FMT_plx "\n"
724 "qemu: prot_addr = 0x" TARGET_FMT_plx "\n",
725 real_addr,
726 cmdline_addr,
727 prot_addr);
728 #endif
729
730 /* highest address for loading the initrd */
731 if (protocol >= 0x203)
732 initrd_max = ldl_p(header+0x22c);
733 else
734 initrd_max = 0x37ffffff;
735
736 if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
737 initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
738
739 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
740 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
741 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
742 (uint8_t*)strdup(kernel_cmdline),
743 strlen(kernel_cmdline)+1);
744
745 if (protocol >= 0x202) {
746 stl_p(header+0x228, cmdline_addr);
747 } else {
748 stw_p(header+0x20, 0xA33F);
749 stw_p(header+0x22, cmdline_addr-real_addr);
750 }
751
752 /* handle vga= parameter */
753 vmode = strstr(kernel_cmdline, "vga=");
754 if (vmode) {
755 unsigned int video_mode;
756 /* skip "vga=" */
757 vmode += 4;
758 if (!strncmp(vmode, "normal", 6)) {
759 video_mode = 0xffff;
760 } else if (!strncmp(vmode, "ext", 3)) {
761 video_mode = 0xfffe;
762 } else if (!strncmp(vmode, "ask", 3)) {
763 video_mode = 0xfffd;
764 } else {
765 video_mode = strtol(vmode, NULL, 0);
766 }
767 stw_p(header+0x1fa, video_mode);
768 }
769
770 /* loader type */
771 /* High nybble = B reserved for Qemu; low nybble is revision number.
772 If this code is substantially changed, you may want to consider
773 incrementing the revision. */
774 if (protocol >= 0x200)
775 header[0x210] = 0xB0;
776
777 /* heap */
778 if (protocol >= 0x201) {
779 header[0x211] |= 0x80; /* CAN_USE_HEAP */
780 stw_p(header+0x224, cmdline_addr-real_addr-0x200);
781 }
782
783 /* load initrd */
784 if (initrd_filename) {
785 if (protocol < 0x200) {
786 fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
787 exit(1);
788 }
789
790 initrd_size = get_image_size(initrd_filename);
791 if (initrd_size < 0) {
792 fprintf(stderr, "qemu: error reading initrd %s\n",
793 initrd_filename);
794 exit(1);
795 }
796
797 initrd_addr = (initrd_max-initrd_size) & ~4095;
798
799 initrd_data = g_malloc(initrd_size);
800 load_image(initrd_filename, initrd_data);
801
802 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
803 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
804 fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
805
806 stl_p(header+0x218, initrd_addr);
807 stl_p(header+0x21c, initrd_size);
808 }
809
810 /* load kernel and setup */
811 setup_size = header[0x1f1];
812 if (setup_size == 0)
813 setup_size = 4;
814 setup_size = (setup_size+1)*512;
815 kernel_size -= setup_size;
816
817 setup = g_malloc(setup_size);
818 kernel = g_malloc(kernel_size);
819 fseek(f, 0, SEEK_SET);
820 if (fread(setup, 1, setup_size, f) != setup_size) {
821 fprintf(stderr, "fread() failed\n");
822 exit(1);
823 }
824 if (fread(kernel, 1, kernel_size, f) != kernel_size) {
825 fprintf(stderr, "fread() failed\n");
826 exit(1);
827 }
828 fclose(f);
829 memcpy(setup, header, MIN(sizeof(header), setup_size));
830
831 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
832 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
833 fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
834
835 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
836 fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
837 fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
838
839 option_rom[nb_option_roms].name = "linuxboot.bin";
840 option_rom[nb_option_roms].bootindex = 0;
841 nb_option_roms++;
842 }
843
844 #define NE2000_NB_MAX 6
845
846 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
847 0x280, 0x380 };
848 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
849
850 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
851 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
852
853 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
854 {
855 static int nb_ne2k = 0;
856
857 if (nb_ne2k == NE2000_NB_MAX)
858 return;
859 isa_ne2000_init(bus, ne2000_io[nb_ne2k],
860 ne2000_irq[nb_ne2k], nd);
861 nb_ne2k++;
862 }
863
864 int cpu_is_bsp(CPUState *env)
865 {
866 /* We hard-wire the BSP to the first CPU. */
867 return env->cpu_index == 0;
868 }
869
870 DeviceState *cpu_get_current_apic(void)
871 {
872 if (cpu_single_env) {
873 return cpu_single_env->apic_state;
874 } else {
875 return NULL;
876 }
877 }
878
879 static DeviceState *apic_init(void *env, uint8_t apic_id)
880 {
881 DeviceState *dev;
882 static int apic_mapped;
883
884 if (kvm_enabled() && kvm_irqchip_in_kernel()) {
885 dev = qdev_create(NULL, "kvm-apic");
886 } else {
887 dev = qdev_create(NULL, "apic");
888 }
889 qdev_prop_set_uint8(dev, "id", apic_id);
890 qdev_prop_set_ptr(dev, "cpu_env", env);
891 qdev_init_nofail(dev);
892
893 /* XXX: mapping more APICs at the same memory location */
894 if (apic_mapped == 0) {
895 /* NOTE: the APIC is directly connected to the CPU - it is not
896 on the global memory bus. */
897 /* XXX: what if the base changes? */
898 sysbus_mmio_map(sysbus_from_qdev(dev), 0, MSI_ADDR_BASE);
899 apic_mapped = 1;
900 }
901
902 /* KVM does not support MSI yet. */
903 if (!kvm_enabled() || !kvm_irqchip_in_kernel()) {
904 msi_supported = true;
905 }
906
907 return dev;
908 }
909
910 /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
911 BIOS will read it and start S3 resume at POST Entry */
912 void pc_cmos_set_s3_resume(void *opaque, int irq, int level)
913 {
914 ISADevice *s = opaque;
915
916 if (level) {
917 rtc_set_memory(s, 0xF, 0xFE);
918 }
919 }
920
921 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
922 {
923 CPUState *s = opaque;
924
925 if (level) {
926 cpu_interrupt(s, CPU_INTERRUPT_SMI);
927 }
928 }
929
930 static void pc_cpu_reset(void *opaque)
931 {
932 CPUState *env = opaque;
933
934 cpu_reset(env);
935 env->halted = !cpu_is_bsp(env);
936 }
937
938 static CPUState *pc_new_cpu(const char *cpu_model)
939 {
940 CPUState *env;
941
942 env = cpu_init(cpu_model);
943 if (!env) {
944 fprintf(stderr, "Unable to find x86 CPU definition\n");
945 exit(1);
946 }
947 if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
948 env->apic_state = apic_init(env, env->cpuid_apic_id);
949 }
950 qemu_register_reset(pc_cpu_reset, env);
951 pc_cpu_reset(env);
952 return env;
953 }
954
955 void pc_cpus_init(const char *cpu_model)
956 {
957 int i;
958
959 /* init CPUs */
960 if (cpu_model == NULL) {
961 #ifdef TARGET_X86_64
962 cpu_model = "qemu64";
963 #else
964 cpu_model = "qemu32";
965 #endif
966 }
967
968 for(i = 0; i < smp_cpus; i++) {
969 pc_new_cpu(cpu_model);
970 }
971 }
972
973 void pc_memory_init(MemoryRegion *system_memory,
974 const char *kernel_filename,
975 const char *kernel_cmdline,
976 const char *initrd_filename,
977 ram_addr_t below_4g_mem_size,
978 ram_addr_t above_4g_mem_size,
979 MemoryRegion *rom_memory,
980 MemoryRegion **ram_memory)
981 {
982 char *filename;
983 int ret, linux_boot, i;
984 MemoryRegion *ram, *bios, *isa_bios, *option_rom_mr;
985 MemoryRegion *ram_below_4g, *ram_above_4g;
986 int bios_size, isa_bios_size;
987 void *fw_cfg;
988
989 linux_boot = (kernel_filename != NULL);
990
991 /* Allocate RAM. We allocate it as a single memory region and use
992 * aliases to address portions of it, mostly for backwards compatibility
993 * with older qemus that used qemu_ram_alloc().
994 */
995 ram = g_malloc(sizeof(*ram));
996 memory_region_init_ram(ram, "pc.ram",
997 below_4g_mem_size + above_4g_mem_size);
998 vmstate_register_ram_global(ram);
999 *ram_memory = ram;
1000 ram_below_4g = g_malloc(sizeof(*ram_below_4g));
1001 memory_region_init_alias(ram_below_4g, "ram-below-4g", ram,
1002 0, below_4g_mem_size);
1003 memory_region_add_subregion(system_memory, 0, ram_below_4g);
1004 if (above_4g_mem_size > 0) {
1005 ram_above_4g = g_malloc(sizeof(*ram_above_4g));
1006 memory_region_init_alias(ram_above_4g, "ram-above-4g", ram,
1007 below_4g_mem_size, above_4g_mem_size);
1008 memory_region_add_subregion(system_memory, 0x100000000ULL,
1009 ram_above_4g);
1010 }
1011
1012 /* BIOS load */
1013 if (bios_name == NULL)
1014 bios_name = BIOS_FILENAME;
1015 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1016 if (filename) {
1017 bios_size = get_image_size(filename);
1018 } else {
1019 bios_size = -1;
1020 }
1021 if (bios_size <= 0 ||
1022 (bios_size % 65536) != 0) {
1023 goto bios_error;
1024 }
1025 bios = g_malloc(sizeof(*bios));
1026 memory_region_init_ram(bios, "pc.bios", bios_size);
1027 vmstate_register_ram_global(bios);
1028 memory_region_set_readonly(bios, true);
1029 ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size), -1);
1030 if (ret != 0) {
1031 bios_error:
1032 fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
1033 exit(1);
1034 }
1035 if (filename) {
1036 g_free(filename);
1037 }
1038 /* map the last 128KB of the BIOS in ISA space */
1039 isa_bios_size = bios_size;
1040 if (isa_bios_size > (128 * 1024))
1041 isa_bios_size = 128 * 1024;
1042 isa_bios = g_malloc(sizeof(*isa_bios));
1043 memory_region_init_alias(isa_bios, "isa-bios", bios,
1044 bios_size - isa_bios_size, isa_bios_size);
1045 memory_region_add_subregion_overlap(rom_memory,
1046 0x100000 - isa_bios_size,
1047 isa_bios,
1048 1);
1049 memory_region_set_readonly(isa_bios, true);
1050
1051 option_rom_mr = g_malloc(sizeof(*option_rom_mr));
1052 memory_region_init_ram(option_rom_mr, "pc.rom", PC_ROM_SIZE);
1053 vmstate_register_ram_global(option_rom_mr);
1054 memory_region_add_subregion_overlap(rom_memory,
1055 PC_ROM_MIN_VGA,
1056 option_rom_mr,
1057 1);
1058
1059 /* map all the bios at the top of memory */
1060 memory_region_add_subregion(rom_memory,
1061 (uint32_t)(-bios_size),
1062 bios);
1063
1064 fw_cfg = bochs_bios_init();
1065 rom_set_fw(fw_cfg);
1066
1067 if (linux_boot) {
1068 load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
1069 }
1070
1071 for (i = 0; i < nb_option_roms; i++) {
1072 rom_add_option(option_rom[i].name, option_rom[i].bootindex);
1073 }
1074 }
1075
1076 qemu_irq *pc_allocate_cpu_irq(void)
1077 {
1078 return qemu_allocate_irqs(pic_irq_request, NULL, 1);
1079 }
1080
1081 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
1082 {
1083 DeviceState *dev = NULL;
1084
1085 if (cirrus_vga_enabled) {
1086 if (pci_bus) {
1087 dev = pci_cirrus_vga_init(pci_bus);
1088 } else {
1089 dev = &isa_create_simple(isa_bus, "isa-cirrus-vga")->qdev;
1090 }
1091 } else if (vmsvga_enabled) {
1092 if (pci_bus) {
1093 dev = pci_vmsvga_init(pci_bus);
1094 } else {
1095 fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
1096 }
1097 #ifdef CONFIG_SPICE
1098 } else if (qxl_enabled) {
1099 if (pci_bus) {
1100 dev = &pci_create_simple(pci_bus, -1, "qxl-vga")->qdev;
1101 } else {
1102 fprintf(stderr, "%s: qxl: no PCI bus\n", __FUNCTION__);
1103 }
1104 #endif
1105 } else if (std_vga_enabled) {
1106 if (pci_bus) {
1107 dev = pci_vga_init(pci_bus);
1108 } else {
1109 dev = isa_vga_init(isa_bus);
1110 }
1111 }
1112
1113 return dev;
1114 }
1115
1116 static void cpu_request_exit(void *opaque, int irq, int level)
1117 {
1118 CPUState *env = cpu_single_env;
1119
1120 if (env && level) {
1121 cpu_exit(env);
1122 }
1123 }
1124
1125 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1126 ISADevice **rtc_state,
1127 ISADevice **floppy,
1128 bool no_vmport)
1129 {
1130 int i;
1131 DriveInfo *fd[MAX_FD];
1132 qemu_irq rtc_irq = NULL;
1133 qemu_irq *a20_line;
1134 ISADevice *i8042, *port92, *vmmouse, *pit;
1135 qemu_irq *cpu_exit_irq;
1136
1137 register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
1138
1139 register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
1140
1141 if (!no_hpet) {
1142 DeviceState *hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL);
1143
1144 if (hpet) {
1145 for (i = 0; i < GSI_NUM_PINS; i++) {
1146 sysbus_connect_irq(sysbus_from_qdev(hpet), i, gsi[i]);
1147 }
1148 rtc_irq = qdev_get_gpio_in(hpet, 0);
1149 }
1150 }
1151 *rtc_state = rtc_init(isa_bus, 2000, rtc_irq);
1152
1153 qemu_register_boot_set(pc_boot_set, *rtc_state);
1154
1155 pit = pit_init(isa_bus, 0x40, 0);
1156 pcspk_init(pit);
1157
1158 for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1159 if (serial_hds[i]) {
1160 serial_isa_init(isa_bus, i, serial_hds[i]);
1161 }
1162 }
1163
1164 for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1165 if (parallel_hds[i]) {
1166 parallel_init(isa_bus, i, parallel_hds[i]);
1167 }
1168 }
1169
1170 a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1171 i8042 = isa_create_simple(isa_bus, "i8042");
1172 i8042_setup_a20_line(i8042, &a20_line[0]);
1173 if (!no_vmport) {
1174 vmport_init(isa_bus);
1175 vmmouse = isa_try_create(isa_bus, "vmmouse");
1176 } else {
1177 vmmouse = NULL;
1178 }
1179 if (vmmouse) {
1180 qdev_prop_set_ptr(&vmmouse->qdev, "ps2_mouse", i8042);
1181 qdev_init_nofail(&vmmouse->qdev);
1182 }
1183 port92 = isa_create_simple(isa_bus, "port92");
1184 port92_init(port92, &a20_line[1]);
1185
1186 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
1187 DMA_init(0, cpu_exit_irq);
1188
1189 for(i = 0; i < MAX_FD; i++) {
1190 fd[i] = drive_get(IF_FLOPPY, 0, i);
1191 }
1192 *floppy = fdctrl_init_isa(isa_bus, fd);
1193 }
1194
1195 void pc_pci_device_init(PCIBus *pci_bus)
1196 {
1197 int max_bus;
1198 int bus;
1199
1200 max_bus = drive_get_max_bus(IF_SCSI);
1201 for (bus = 0; bus <= max_bus; bus++) {
1202 pci_create_simple(pci_bus, -1, "lsi53c895a");
1203 }
1204 }