hw/arm/raspi: fix CPRMAN base address
[qemu.git] / hw / pci-bridge / pcie_root_port.c
1 /*
2 * Base class for PCI Express Root Ports
3 *
4 * Copyright (C) 2017 Red Hat Inc
5 *
6 * Authors:
7 * Marcel Apfelbaum <marcel@redhat.com>
8 *
9 * Most of the code was migrated from hw/pci-bridge/ioh3420.
10 *
11 * This work is licensed under the terms of the GNU GPL, version 2 or later.
12 * See the COPYING file in the top-level directory.
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include "qemu/module.h"
18 #include "hw/pci/pcie_port.h"
19 #include "hw/qdev-properties.h"
20
21 static void rp_aer_vector_update(PCIDevice *d)
22 {
23 PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d);
24
25 if (rpc->aer_vector) {
26 pcie_aer_root_set_vector(d, rpc->aer_vector(d));
27 }
28 }
29
30 static void rp_write_config(PCIDevice *d, uint32_t address,
31 uint32_t val, int len)
32 {
33 uint32_t root_cmd =
34 pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND);
35 uint16_t slt_ctl, slt_sta;
36
37 pcie_cap_slot_get(d, &slt_ctl, &slt_sta);
38
39 pci_bridge_write_config(d, address, val, len);
40 rp_aer_vector_update(d);
41 pcie_cap_slot_write_config(d, slt_ctl, slt_sta, address, val, len);
42 pcie_aer_write_config(d, address, val, len);
43 pcie_aer_root_write_config(d, address, val, len, root_cmd);
44 }
45
46 static void rp_reset(DeviceState *qdev)
47 {
48 PCIDevice *d = PCI_DEVICE(qdev);
49
50 rp_aer_vector_update(d);
51 pcie_cap_root_reset(d);
52 pcie_cap_deverr_reset(d);
53 pcie_cap_slot_reset(d);
54 pcie_cap_arifwd_reset(d);
55 pcie_acs_reset(d);
56 pcie_aer_root_reset(d);
57 pci_bridge_reset(qdev);
58 pci_bridge_disable_base_limit(d);
59 }
60
61 static void rp_realize(PCIDevice *d, Error **errp)
62 {
63 PCIEPort *p = PCIE_PORT(d);
64 PCIESlot *s = PCIE_SLOT(d);
65 PCIDeviceClass *dc = PCI_DEVICE_GET_CLASS(d);
66 PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d);
67 int rc;
68
69 pci_config_set_interrupt_pin(d->config, 1);
70 pci_bridge_initfn(d, TYPE_PCIE_BUS);
71 pcie_port_init_reg(d);
72
73 rc = pci_bridge_ssvid_init(d, rpc->ssvid_offset, dc->vendor_id,
74 rpc->ssid, errp);
75 if (rc < 0) {
76 error_append_hint(errp, "Can't init SSV ID, error %d\n", rc);
77 goto err_bridge;
78 }
79
80 if (rpc->interrupts_init) {
81 rc = rpc->interrupts_init(d, errp);
82 if (rc < 0) {
83 goto err_bridge;
84 }
85 }
86
87 rc = pcie_cap_init(d, rpc->exp_offset, PCI_EXP_TYPE_ROOT_PORT,
88 p->port, errp);
89 if (rc < 0) {
90 error_append_hint(errp, "Can't add Root Port capability, "
91 "error %d\n", rc);
92 goto err_int;
93 }
94
95 pcie_cap_arifwd_init(d);
96 pcie_cap_deverr_init(d);
97 pcie_cap_slot_init(d, s);
98 pcie_cap_root_init(d);
99
100 pcie_chassis_create(s->chassis);
101 rc = pcie_chassis_add_slot(s);
102 if (rc < 0) {
103 error_setg(errp, "Can't add chassis slot, error %d", rc);
104 goto err_pcie_cap;
105 }
106
107 rc = pcie_aer_init(d, PCI_ERR_VER, rpc->aer_offset,
108 PCI_ERR_SIZEOF, errp);
109 if (rc < 0) {
110 goto err;
111 }
112 pcie_aer_root_init(d);
113 rp_aer_vector_update(d);
114
115 if (rpc->acs_offset && !s->disable_acs) {
116 pcie_acs_init(d, rpc->acs_offset);
117 }
118 return;
119
120 err:
121 pcie_chassis_del_slot(s);
122 err_pcie_cap:
123 pcie_cap_exit(d);
124 err_int:
125 if (rpc->interrupts_uninit) {
126 rpc->interrupts_uninit(d);
127 }
128 err_bridge:
129 pci_bridge_exitfn(d);
130 }
131
132 static void rp_exit(PCIDevice *d)
133 {
134 PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d);
135 PCIESlot *s = PCIE_SLOT(d);
136
137 pcie_aer_exit(d);
138 pcie_chassis_del_slot(s);
139 pcie_cap_exit(d);
140 if (rpc->interrupts_uninit) {
141 rpc->interrupts_uninit(d);
142 }
143 pci_bridge_exitfn(d);
144 }
145
146 static Property rp_props[] = {
147 DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present,
148 QEMU_PCIE_SLTCAP_PCP_BITNR, true),
149 DEFINE_PROP_BOOL("disable-acs", PCIESlot, disable_acs, false),
150 DEFINE_PROP_END_OF_LIST()
151 };
152
153 static void rp_instance_post_init(Object *obj)
154 {
155 PCIESlot *s = PCIE_SLOT(obj);
156
157 if (!s->speed) {
158 s->speed = QEMU_PCI_EXP_LNK_2_5GT;
159 }
160
161 if (!s->width) {
162 s->width = QEMU_PCI_EXP_LNK_X1;
163 }
164 }
165
166 static void rp_class_init(ObjectClass *klass, void *data)
167 {
168 DeviceClass *dc = DEVICE_CLASS(klass);
169 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
170
171 k->is_bridge = true;
172 k->config_write = rp_write_config;
173 k->realize = rp_realize;
174 k->exit = rp_exit;
175 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
176 dc->reset = rp_reset;
177 device_class_set_props(dc, rp_props);
178 }
179
180 static const TypeInfo rp_info = {
181 .name = TYPE_PCIE_ROOT_PORT,
182 .parent = TYPE_PCIE_SLOT,
183 .instance_post_init = rp_instance_post_init,
184 .class_init = rp_class_init,
185 .abstract = true,
186 .class_size = sizeof(PCIERootPortClass),
187 .interfaces = (InterfaceInfo[]) {
188 { INTERFACE_PCIE_DEVICE },
189 { }
190 },
191 };
192
193 static void rp_register_types(void)
194 {
195 type_register_static(&rp_info);
196 }
197
198 type_init(rp_register_types)