hw/arm/raspi: fix CPRMAN base address
[qemu.git] / hw / pci-host / bonito.c
1 /*
2 * bonito north bridge support
3 *
4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
5 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
6 *
7 * This code is licensed under the GNU GPL v2.
8 *
9 * Contributions after 2012-01-13 are licensed under the terms of the
10 * GNU GPL, version 2 or (at your option) any later version.
11 */
12
13 /*
14 * fuloong 2e mini pc has a bonito north bridge.
15 */
16
17 /*
18 * what is the meaning of devfn in qemu and IDSEL in bonito northbridge?
19 *
20 * devfn pci_slot<<3 + funno
21 * one pci bus can have 32 devices and each device can have 8 functions.
22 *
23 * In bonito north bridge, pci slot = IDSEL bit - 12.
24 * For example, PCI_IDSEL_VIA686B = 17,
25 * pci slot = 17-12=5
26 *
27 * so
28 * VT686B_FUN0's devfn = (5<<3)+0
29 * VT686B_FUN1's devfn = (5<<3)+1
30 *
31 * qemu also uses pci address for north bridge to access pci config register.
32 * bus_no [23:16]
33 * dev_no [15:11]
34 * fun_no [10:8]
35 * reg_no [7:2]
36 *
37 * so function bonito_sbridge_pciaddr for the translation from
38 * north bridge address to pci address.
39 */
40
41 #include "qemu/osdep.h"
42 #include "qemu/units.h"
43 #include "qapi/error.h"
44 #include "qemu/error-report.h"
45 #include "hw/pci/pci.h"
46 #include "hw/irq.h"
47 #include "hw/mips/mips.h"
48 #include "hw/pci/pci_host.h"
49 #include "migration/vmstate.h"
50 #include "sysemu/reset.h"
51 #include "sysemu/runstate.h"
52 #include "exec/address-spaces.h"
53 #include "hw/misc/unimp.h"
54 #include "hw/registerfields.h"
55 #include "qom/object.h"
56
57 /* #define DEBUG_BONITO */
58
59 #ifdef DEBUG_BONITO
60 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__)
61 #else
62 #define DPRINTF(fmt, ...)
63 #endif
64
65 /* from linux soure code. include/asm-mips/mips-boards/bonito64.h*/
66 #define BONITO_BOOT_BASE 0x1fc00000
67 #define BONITO_BOOT_SIZE 0x00100000
68 #define BONITO_BOOT_TOP (BONITO_BOOT_BASE + BONITO_BOOT_SIZE - 1)
69 #define BONITO_FLASH_BASE 0x1c000000
70 #define BONITO_FLASH_SIZE 0x03000000
71 #define BONITO_FLASH_TOP (BONITO_FLASH_BASE + BONITO_FLASH_SIZE - 1)
72 #define BONITO_SOCKET_BASE 0x1f800000
73 #define BONITO_SOCKET_SIZE 0x00400000
74 #define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE + BONITO_SOCKET_SIZE - 1)
75 #define BONITO_REG_BASE 0x1fe00000
76 #define BONITO_REG_SIZE 0x00040000
77 #define BONITO_REG_TOP (BONITO_REG_BASE + BONITO_REG_SIZE - 1)
78 #define BONITO_DEV_BASE 0x1ff00000
79 #define BONITO_DEV_SIZE 0x00100000
80 #define BONITO_DEV_TOP (BONITO_DEV_BASE + BONITO_DEV_SIZE - 1)
81 #define BONITO_PCILO_BASE 0x10000000
82 #define BONITO_PCILO_BASE_VA 0xb0000000
83 #define BONITO_PCILO_SIZE 0x0c000000
84 #define BONITO_PCILO_TOP (BONITO_PCILO_BASE + BONITO_PCILO_SIZE - 1)
85 #define BONITO_PCILO0_BASE 0x10000000
86 #define BONITO_PCILO1_BASE 0x14000000
87 #define BONITO_PCILO2_BASE 0x18000000
88 #define BONITO_PCIHI_BASE 0x20000000
89 #define BONITO_PCIHI_SIZE 0x60000000
90 #define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE + BONITO_PCIHI_SIZE - 1)
91 #define BONITO_PCIIO_BASE 0x1fd00000
92 #define BONITO_PCIIO_BASE_VA 0xbfd00000
93 #define BONITO_PCIIO_SIZE 0x00010000
94 #define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE + BONITO_PCIIO_SIZE - 1)
95 #define BONITO_PCICFG_BASE 0x1fe80000
96 #define BONITO_PCICFG_SIZE 0x00080000
97 #define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE + BONITO_PCICFG_SIZE - 1)
98
99
100 #define BONITO_PCICONFIGBASE 0x00
101 #define BONITO_REGBASE 0x100
102
103 #define BONITO_PCICONFIG_BASE (BONITO_PCICONFIGBASE + BONITO_REG_BASE)
104 #define BONITO_PCICONFIG_SIZE (0x100)
105
106 #define BONITO_INTERNAL_REG_BASE (BONITO_REGBASE + BONITO_REG_BASE)
107 #define BONITO_INTERNAL_REG_SIZE (0x70)
108
109 #define BONITO_SPCICONFIG_BASE (BONITO_PCICFG_BASE)
110 #define BONITO_SPCICONFIG_SIZE (BONITO_PCICFG_SIZE)
111
112
113
114 /* 1. Bonito h/w Configuration */
115 /* Power on register */
116
117 #define BONITO_BONPONCFG (0x00 >> 2) /* 0x100 */
118
119 /* PCI configuration register */
120 #define BONITO_BONGENCFG_OFFSET 0x4
121 #define BONITO_BONGENCFG (BONITO_BONGENCFG_OFFSET >> 2) /*0x104 */
122 REG32(BONGENCFG, 0x104)
123 FIELD(BONGENCFG, DEBUGMODE, 0, 1)
124 FIELD(BONGENCFG, SNOOP, 1, 1)
125 FIELD(BONGENCFG, CPUSELFRESET, 2, 1)
126 FIELD(BONGENCFG, BYTESWAP, 6, 1)
127 FIELD(BONGENCFG, UNCACHED, 7, 1)
128 FIELD(BONGENCFG, PREFETCH, 8, 1)
129 FIELD(BONGENCFG, WRITEBEHIND, 9, 1)
130 FIELD(BONGENCFG, PCIQUEUE, 12, 1)
131
132 /* 2. IO & IDE configuration */
133 #define BONITO_IODEVCFG (0x08 >> 2) /* 0x108 */
134
135 /* 3. IO & IDE configuration */
136 #define BONITO_SDCFG (0x0c >> 2) /* 0x10c */
137
138 /* 4. PCI address map control */
139 #define BONITO_PCIMAP (0x10 >> 2) /* 0x110 */
140 #define BONITO_PCIMEMBASECFG (0x14 >> 2) /* 0x114 */
141 #define BONITO_PCIMAP_CFG (0x18 >> 2) /* 0x118 */
142
143 /* 5. ICU & GPIO regs */
144 /* GPIO Regs - r/w */
145 #define BONITO_GPIODATA_OFFSET 0x1c
146 #define BONITO_GPIODATA (BONITO_GPIODATA_OFFSET >> 2) /* 0x11c */
147 #define BONITO_GPIOIE (0x20 >> 2) /* 0x120 */
148
149 /* ICU Configuration Regs - r/w */
150 #define BONITO_INTEDGE (0x24 >> 2) /* 0x124 */
151 #define BONITO_INTSTEER (0x28 >> 2) /* 0x128 */
152 #define BONITO_INTPOL (0x2c >> 2) /* 0x12c */
153
154 /* ICU Enable Regs - IntEn & IntISR are r/o. */
155 #define BONITO_INTENSET (0x30 >> 2) /* 0x130 */
156 #define BONITO_INTENCLR (0x34 >> 2) /* 0x134 */
157 #define BONITO_INTEN (0x38 >> 2) /* 0x138 */
158 #define BONITO_INTISR (0x3c >> 2) /* 0x13c */
159
160 /* PCI mail boxes */
161 #define BONITO_PCIMAIL0_OFFSET 0x40
162 #define BONITO_PCIMAIL1_OFFSET 0x44
163 #define BONITO_PCIMAIL2_OFFSET 0x48
164 #define BONITO_PCIMAIL3_OFFSET 0x4c
165 #define BONITO_PCIMAIL0 (0x40 >> 2) /* 0x140 */
166 #define BONITO_PCIMAIL1 (0x44 >> 2) /* 0x144 */
167 #define BONITO_PCIMAIL2 (0x48 >> 2) /* 0x148 */
168 #define BONITO_PCIMAIL3 (0x4c >> 2) /* 0x14c */
169
170 /* 6. PCI cache */
171 #define BONITO_PCICACHECTRL (0x50 >> 2) /* 0x150 */
172 #define BONITO_PCICACHETAG (0x54 >> 2) /* 0x154 */
173 #define BONITO_PCIBADADDR (0x58 >> 2) /* 0x158 */
174 #define BONITO_PCIMSTAT (0x5c >> 2) /* 0x15c */
175
176 /* 7. other*/
177 #define BONITO_TIMECFG (0x60 >> 2) /* 0x160 */
178 #define BONITO_CPUCFG (0x64 >> 2) /* 0x164 */
179 #define BONITO_DQCFG (0x68 >> 2) /* 0x168 */
180 #define BONITO_MEMSIZE (0x6C >> 2) /* 0x16c */
181
182 #define BONITO_REGS (0x70 >> 2)
183
184 /* PCI config for south bridge. type 0 */
185 #define BONITO_PCICONF_IDSEL_MASK 0xfffff800 /* [31:11] */
186 #define BONITO_PCICONF_IDSEL_OFFSET 11
187 #define BONITO_PCICONF_FUN_MASK 0x700 /* [10:8] */
188 #define BONITO_PCICONF_FUN_OFFSET 8
189 #define BONITO_PCICONF_REG_MASK 0xFC
190 #define BONITO_PCICONF_REG_OFFSET 0
191
192
193 /* idsel BIT = pci slot number +12 */
194 #define PCI_SLOT_BASE 12
195 #define PCI_IDSEL_VIA686B_BIT (17)
196 #define PCI_IDSEL_VIA686B (1 << PCI_IDSEL_VIA686B_BIT)
197
198 #define PCI_ADDR(busno , devno , funno , regno) \
199 ((((busno) << 16) & 0xff0000) + (((devno) << 11) & 0xf800) + \
200 (((funno) << 8) & 0x700) + (regno))
201
202 typedef struct BonitoState BonitoState;
203
204 struct PCIBonitoState {
205 PCIDevice dev;
206
207 BonitoState *pcihost;
208 uint32_t regs[BONITO_REGS];
209
210 struct bonldma {
211 uint32_t ldmactrl;
212 uint32_t ldmastat;
213 uint32_t ldmaaddr;
214 uint32_t ldmago;
215 } bonldma;
216
217 /* Based at 1fe00300, bonito Copier */
218 struct boncop {
219 uint32_t copctrl;
220 uint32_t copstat;
221 uint32_t coppaddr;
222 uint32_t copgo;
223 } boncop;
224
225 /* Bonito registers */
226 MemoryRegion iomem;
227 MemoryRegion iomem_ldma;
228 MemoryRegion iomem_cop;
229 MemoryRegion bonito_pciio;
230 MemoryRegion bonito_localio;
231
232 };
233 typedef struct PCIBonitoState PCIBonitoState;
234
235 struct BonitoState {
236 PCIHostState parent_obj;
237 qemu_irq *pic;
238 PCIBonitoState *pci_dev;
239 MemoryRegion pci_mem;
240 };
241
242 #define TYPE_BONITO_PCI_HOST_BRIDGE "Bonito-pcihost"
243 OBJECT_DECLARE_SIMPLE_TYPE(BonitoState, BONITO_PCI_HOST_BRIDGE)
244
245 #define TYPE_PCI_BONITO "Bonito"
246 OBJECT_DECLARE_SIMPLE_TYPE(PCIBonitoState, PCI_BONITO)
247
248 static void bonito_writel(void *opaque, hwaddr addr,
249 uint64_t val, unsigned size)
250 {
251 PCIBonitoState *s = opaque;
252 uint32_t saddr;
253 int reset = 0;
254
255 saddr = addr >> 2;
256
257 DPRINTF("bonito_writel "TARGET_FMT_plx" val %lx saddr %x\n",
258 addr, val, saddr);
259 switch (saddr) {
260 case BONITO_BONPONCFG:
261 case BONITO_IODEVCFG:
262 case BONITO_SDCFG:
263 case BONITO_PCIMAP:
264 case BONITO_PCIMEMBASECFG:
265 case BONITO_PCIMAP_CFG:
266 case BONITO_GPIODATA:
267 case BONITO_GPIOIE:
268 case BONITO_INTEDGE:
269 case BONITO_INTSTEER:
270 case BONITO_INTPOL:
271 case BONITO_PCIMAIL0:
272 case BONITO_PCIMAIL1:
273 case BONITO_PCIMAIL2:
274 case BONITO_PCIMAIL3:
275 case BONITO_PCICACHECTRL:
276 case BONITO_PCICACHETAG:
277 case BONITO_PCIBADADDR:
278 case BONITO_PCIMSTAT:
279 case BONITO_TIMECFG:
280 case BONITO_CPUCFG:
281 case BONITO_DQCFG:
282 case BONITO_MEMSIZE:
283 s->regs[saddr] = val;
284 break;
285 case BONITO_BONGENCFG:
286 if (!(s->regs[saddr] & 0x04) && (val & 0x04)) {
287 reset = 1; /* bit 2 jump from 0 to 1 cause reset */
288 }
289 s->regs[saddr] = val;
290 if (reset) {
291 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
292 }
293 break;
294 case BONITO_INTENSET:
295 s->regs[BONITO_INTENSET] = val;
296 s->regs[BONITO_INTEN] |= val;
297 break;
298 case BONITO_INTENCLR:
299 s->regs[BONITO_INTENCLR] = val;
300 s->regs[BONITO_INTEN] &= ~val;
301 break;
302 case BONITO_INTEN:
303 case BONITO_INTISR:
304 DPRINTF("write to readonly bonito register %x\n", saddr);
305 break;
306 default:
307 DPRINTF("write to unknown bonito register %x\n", saddr);
308 break;
309 }
310 }
311
312 static uint64_t bonito_readl(void *opaque, hwaddr addr,
313 unsigned size)
314 {
315 PCIBonitoState *s = opaque;
316 uint32_t saddr;
317
318 saddr = addr >> 2;
319
320 DPRINTF("bonito_readl "TARGET_FMT_plx"\n", addr);
321 switch (saddr) {
322 case BONITO_INTISR:
323 return s->regs[saddr];
324 default:
325 return s->regs[saddr];
326 }
327 }
328
329 static const MemoryRegionOps bonito_ops = {
330 .read = bonito_readl,
331 .write = bonito_writel,
332 .endianness = DEVICE_NATIVE_ENDIAN,
333 .valid = {
334 .min_access_size = 4,
335 .max_access_size = 4,
336 },
337 };
338
339 static void bonito_pciconf_writel(void *opaque, hwaddr addr,
340 uint64_t val, unsigned size)
341 {
342 PCIBonitoState *s = opaque;
343 PCIDevice *d = PCI_DEVICE(s);
344
345 DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %lx\n", addr, val);
346 d->config_write(d, addr, val, 4);
347 }
348
349 static uint64_t bonito_pciconf_readl(void *opaque, hwaddr addr,
350 unsigned size)
351 {
352
353 PCIBonitoState *s = opaque;
354 PCIDevice *d = PCI_DEVICE(s);
355
356 DPRINTF("bonito_pciconf_readl "TARGET_FMT_plx"\n", addr);
357 return d->config_read(d, addr, 4);
358 }
359
360 /* north bridge PCI configure space. 0x1fe0 0000 - 0x1fe0 00ff */
361
362 static const MemoryRegionOps bonito_pciconf_ops = {
363 .read = bonito_pciconf_readl,
364 .write = bonito_pciconf_writel,
365 .endianness = DEVICE_NATIVE_ENDIAN,
366 .valid = {
367 .min_access_size = 4,
368 .max_access_size = 4,
369 },
370 };
371
372 static uint64_t bonito_ldma_readl(void *opaque, hwaddr addr,
373 unsigned size)
374 {
375 uint32_t val;
376 PCIBonitoState *s = opaque;
377
378 if (addr >= sizeof(s->bonldma)) {
379 return 0;
380 }
381
382 val = ((uint32_t *)(&s->bonldma))[addr / sizeof(uint32_t)];
383
384 return val;
385 }
386
387 static void bonito_ldma_writel(void *opaque, hwaddr addr,
388 uint64_t val, unsigned size)
389 {
390 PCIBonitoState *s = opaque;
391
392 if (addr >= sizeof(s->bonldma)) {
393 return;
394 }
395
396 ((uint32_t *)(&s->bonldma))[addr / sizeof(uint32_t)] = val & 0xffffffff;
397 }
398
399 static const MemoryRegionOps bonito_ldma_ops = {
400 .read = bonito_ldma_readl,
401 .write = bonito_ldma_writel,
402 .endianness = DEVICE_NATIVE_ENDIAN,
403 .valid = {
404 .min_access_size = 4,
405 .max_access_size = 4,
406 },
407 };
408
409 static uint64_t bonito_cop_readl(void *opaque, hwaddr addr,
410 unsigned size)
411 {
412 uint32_t val;
413 PCIBonitoState *s = opaque;
414
415 if (addr >= sizeof(s->boncop)) {
416 return 0;
417 }
418
419 val = ((uint32_t *)(&s->boncop))[addr / sizeof(uint32_t)];
420
421 return val;
422 }
423
424 static void bonito_cop_writel(void *opaque, hwaddr addr,
425 uint64_t val, unsigned size)
426 {
427 PCIBonitoState *s = opaque;
428
429 if (addr >= sizeof(s->boncop)) {
430 return;
431 }
432
433 ((uint32_t *)(&s->boncop))[addr / sizeof(uint32_t)] = val & 0xffffffff;
434 }
435
436 static const MemoryRegionOps bonito_cop_ops = {
437 .read = bonito_cop_readl,
438 .write = bonito_cop_writel,
439 .endianness = DEVICE_NATIVE_ENDIAN,
440 .valid = {
441 .min_access_size = 4,
442 .max_access_size = 4,
443 },
444 };
445
446 static uint32_t bonito_sbridge_pciaddr(void *opaque, hwaddr addr)
447 {
448 PCIBonitoState *s = opaque;
449 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
450 uint32_t cfgaddr;
451 uint32_t idsel;
452 uint32_t devno;
453 uint32_t funno;
454 uint32_t regno;
455 uint32_t pciaddr;
456
457 /* support type0 pci config */
458 if ((s->regs[BONITO_PCIMAP_CFG] & 0x10000) != 0x0) {
459 return 0xffffffff;
460 }
461
462 cfgaddr = addr & 0xffff;
463 cfgaddr |= (s->regs[BONITO_PCIMAP_CFG] & 0xffff) << 16;
464
465 idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >>
466 BONITO_PCICONF_IDSEL_OFFSET;
467 devno = ctz32(idsel);
468 funno = (cfgaddr & BONITO_PCICONF_FUN_MASK) >> BONITO_PCICONF_FUN_OFFSET;
469 regno = (cfgaddr & BONITO_PCICONF_REG_MASK) >> BONITO_PCICONF_REG_OFFSET;
470
471 if (idsel == 0) {
472 error_report("error in bonito pci config address " TARGET_FMT_plx
473 ",pcimap_cfg=%x", addr, s->regs[BONITO_PCIMAP_CFG]);
474 exit(1);
475 }
476 pciaddr = PCI_ADDR(pci_bus_num(phb->bus), devno, funno, regno);
477 DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n",
478 cfgaddr, pciaddr, pci_bus_num(phb->bus), devno, funno, regno);
479
480 return pciaddr;
481 }
482
483 static void bonito_spciconf_write(void *opaque, hwaddr addr, uint64_t val,
484 unsigned size)
485 {
486 PCIBonitoState *s = opaque;
487 PCIDevice *d = PCI_DEVICE(s);
488 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
489 uint32_t pciaddr;
490 uint16_t status;
491
492 DPRINTF("bonito_spciconf_write "TARGET_FMT_plx" size %d val %lx\n",
493 addr, size, val);
494
495 pciaddr = bonito_sbridge_pciaddr(s, addr);
496
497 if (pciaddr == 0xffffffff) {
498 return;
499 }
500
501 /* set the pci address in s->config_reg */
502 phb->config_reg = (pciaddr) | (1u << 31);
503 pci_data_write(phb->bus, phb->config_reg, val, size);
504
505 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
506 status = pci_get_word(d->config + PCI_STATUS);
507 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
508 pci_set_word(d->config + PCI_STATUS, status);
509 }
510
511 static uint64_t bonito_spciconf_read(void *opaque, hwaddr addr, unsigned size)
512 {
513 PCIBonitoState *s = opaque;
514 PCIDevice *d = PCI_DEVICE(s);
515 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
516 uint32_t pciaddr;
517 uint16_t status;
518
519 DPRINTF("bonito_spciconf_read "TARGET_FMT_plx" size %d\n", addr, size);
520
521 pciaddr = bonito_sbridge_pciaddr(s, addr);
522
523 if (pciaddr == 0xffffffff) {
524 return MAKE_64BIT_MASK(0, size * 8);
525 }
526
527 /* set the pci address in s->config_reg */
528 phb->config_reg = (pciaddr) | (1u << 31);
529
530 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
531 status = pci_get_word(d->config + PCI_STATUS);
532 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
533 pci_set_word(d->config + PCI_STATUS, status);
534
535 return pci_data_read(phb->bus, phb->config_reg, size);
536 }
537
538 /* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */
539 static const MemoryRegionOps bonito_spciconf_ops = {
540 .read = bonito_spciconf_read,
541 .write = bonito_spciconf_write,
542 .valid.min_access_size = 1,
543 .valid.max_access_size = 4,
544 .impl.min_access_size = 1,
545 .impl.max_access_size = 4,
546 .endianness = DEVICE_NATIVE_ENDIAN,
547 };
548
549 #define BONITO_IRQ_BASE 32
550
551 static void pci_bonito_set_irq(void *opaque, int irq_num, int level)
552 {
553 BonitoState *s = opaque;
554 qemu_irq *pic = s->pic;
555 PCIBonitoState *bonito_state = s->pci_dev;
556 int internal_irq = irq_num - BONITO_IRQ_BASE;
557
558 if (bonito_state->regs[BONITO_INTEDGE] & (1 << internal_irq)) {
559 qemu_irq_pulse(*pic);
560 } else { /* level triggered */
561 if (bonito_state->regs[BONITO_INTPOL] & (1 << internal_irq)) {
562 qemu_irq_raise(*pic);
563 } else {
564 qemu_irq_lower(*pic);
565 }
566 }
567 }
568
569 /* map the original irq (0~3) to bonito irq (16~47, but 16~31 are unused) */
570 static int pci_bonito_map_irq(PCIDevice *pci_dev, int irq_num)
571 {
572 int slot;
573
574 slot = (pci_dev->devfn >> 3);
575
576 switch (slot) {
577 case 5: /* FULOONG2E_VIA_SLOT, SouthBridge, IDE, USB, ACPI, AC97, MC97 */
578 return irq_num % 4 + BONITO_IRQ_BASE;
579 case 6: /* FULOONG2E_ATI_SLOT, VGA */
580 return 4 + BONITO_IRQ_BASE;
581 case 7: /* FULOONG2E_RTL_SLOT, RTL8139 */
582 return 5 + BONITO_IRQ_BASE;
583 case 8 ... 12: /* PCI slot 1 to 4 */
584 return (slot - 8 + irq_num) + 6 + BONITO_IRQ_BASE;
585 default: /* Unknown device, don't do any translation */
586 return irq_num;
587 }
588 }
589
590 static void bonito_reset(void *opaque)
591 {
592 PCIBonitoState *s = opaque;
593 uint32_t val = 0;
594
595 /* set the default value of north bridge registers */
596
597 s->regs[BONITO_BONPONCFG] = 0xc40;
598 val = FIELD_DP32(val, BONGENCFG, PCIQUEUE, 1);
599 val = FIELD_DP32(val, BONGENCFG, WRITEBEHIND, 1);
600 val = FIELD_DP32(val, BONGENCFG, PREFETCH, 1);
601 val = FIELD_DP32(val, BONGENCFG, UNCACHED, 1);
602 val = FIELD_DP32(val, BONGENCFG, CPUSELFRESET, 1);
603 s->regs[BONITO_BONGENCFG] = val;
604
605 s->regs[BONITO_IODEVCFG] = 0x2bff8010;
606 s->regs[BONITO_SDCFG] = 0x255e0091;
607
608 s->regs[BONITO_GPIODATA] = 0x1ff;
609 s->regs[BONITO_GPIOIE] = 0x1ff;
610 s->regs[BONITO_DQCFG] = 0x8;
611 s->regs[BONITO_MEMSIZE] = 0x10000000;
612 s->regs[BONITO_PCIMAP] = 0x6140;
613 }
614
615 static const VMStateDescription vmstate_bonito = {
616 .name = "Bonito",
617 .version_id = 1,
618 .minimum_version_id = 1,
619 .fields = (VMStateField[]) {
620 VMSTATE_PCI_DEVICE(dev, PCIBonitoState),
621 VMSTATE_END_OF_LIST()
622 }
623 };
624
625 static void bonito_pcihost_realize(DeviceState *dev, Error **errp)
626 {
627 PCIHostState *phb = PCI_HOST_BRIDGE(dev);
628 BonitoState *bs = BONITO_PCI_HOST_BRIDGE(dev);
629 MemoryRegion *pcimem_lo_alias = g_new(MemoryRegion, 3);
630
631 memory_region_init(&bs->pci_mem, OBJECT(dev), "pci.mem", BONITO_PCIHI_SIZE);
632 phb->bus = pci_register_root_bus(dev, "pci",
633 pci_bonito_set_irq, pci_bonito_map_irq,
634 dev, &bs->pci_mem, get_system_io(),
635 0x28, 32, TYPE_PCI_BUS);
636
637 for (size_t i = 0; i < 3; i++) {
638 char *name = g_strdup_printf("pci.lomem%zu", i);
639
640 memory_region_init_alias(&pcimem_lo_alias[i], NULL, name,
641 &bs->pci_mem, i * 64 * MiB, 64 * MiB);
642 memory_region_add_subregion(get_system_memory(),
643 BONITO_PCILO_BASE + i * 64 * MiB,
644 &pcimem_lo_alias[i]);
645 g_free(name);
646 }
647
648 create_unimplemented_device("pci.io", BONITO_PCIIO_BASE, 1 * MiB);
649 }
650
651 static void bonito_realize(PCIDevice *dev, Error **errp)
652 {
653 PCIBonitoState *s = PCI_BONITO(dev);
654 SysBusDevice *sysbus = SYS_BUS_DEVICE(s->pcihost);
655 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
656 BonitoState *bs = BONITO_PCI_HOST_BRIDGE(s->pcihost);
657 MemoryRegion *pcimem_alias = g_new(MemoryRegion, 1);
658
659 /*
660 * Bonito North Bridge, built on FPGA,
661 * VENDOR_ID/DEVICE_ID are "undefined"
662 */
663 pci_config_set_prog_interface(dev->config, 0x00);
664
665 /* set the north bridge register mapping */
666 memory_region_init_io(&s->iomem, OBJECT(s), &bonito_ops, s,
667 "north-bridge-register", BONITO_INTERNAL_REG_SIZE);
668 sysbus_init_mmio(sysbus, &s->iomem);
669 sysbus_mmio_map(sysbus, 0, BONITO_INTERNAL_REG_BASE);
670
671 /* set the north bridge pci configure mapping */
672 memory_region_init_io(&phb->conf_mem, OBJECT(s), &bonito_pciconf_ops, s,
673 "north-bridge-pci-config", BONITO_PCICONFIG_SIZE);
674 sysbus_init_mmio(sysbus, &phb->conf_mem);
675 sysbus_mmio_map(sysbus, 1, BONITO_PCICONFIG_BASE);
676
677 /* set the south bridge pci configure mapping */
678 memory_region_init_io(&phb->data_mem, OBJECT(s), &bonito_spciconf_ops, s,
679 "south-bridge-pci-config", BONITO_SPCICONFIG_SIZE);
680 sysbus_init_mmio(sysbus, &phb->data_mem);
681 sysbus_mmio_map(sysbus, 2, BONITO_SPCICONFIG_BASE);
682
683 create_unimplemented_device("bonito", BONITO_REG_BASE, BONITO_REG_SIZE);
684
685 memory_region_init_io(&s->iomem_ldma, OBJECT(s), &bonito_ldma_ops, s,
686 "ldma", 0x100);
687 sysbus_init_mmio(sysbus, &s->iomem_ldma);
688 sysbus_mmio_map(sysbus, 3, 0x1fe00200);
689
690 /* PCI copier */
691 memory_region_init_io(&s->iomem_cop, OBJECT(s), &bonito_cop_ops, s,
692 "cop", 0x100);
693 sysbus_init_mmio(sysbus, &s->iomem_cop);
694 sysbus_mmio_map(sysbus, 4, 0x1fe00300);
695
696 create_unimplemented_device("ROMCS", BONITO_FLASH_BASE, 60 * MiB);
697
698 /* Map PCI IO Space 0x1fd0 0000 - 0x1fd1 0000 */
699 memory_region_init_alias(&s->bonito_pciio, OBJECT(s), "isa_mmio",
700 get_system_io(), 0, BONITO_PCIIO_SIZE);
701 sysbus_init_mmio(sysbus, &s->bonito_pciio);
702 sysbus_mmio_map(sysbus, 5, BONITO_PCIIO_BASE);
703
704 /* add pci local io mapping */
705
706 memory_region_init_alias(&s->bonito_localio, OBJECT(s), "IOCS[0]",
707 get_system_io(), 0, 256 * KiB);
708 sysbus_init_mmio(sysbus, &s->bonito_localio);
709 sysbus_mmio_map(sysbus, 6, BONITO_DEV_BASE);
710 create_unimplemented_device("IOCS[1]", BONITO_DEV_BASE + 1 * 256 * KiB,
711 256 * KiB);
712 create_unimplemented_device("IOCS[2]", BONITO_DEV_BASE + 2 * 256 * KiB,
713 256 * KiB);
714 create_unimplemented_device("IOCS[3]", BONITO_DEV_BASE + 3 * 256 * KiB,
715 256 * KiB);
716
717 memory_region_init_alias(pcimem_alias, NULL, "pci.mem.alias",
718 &bs->pci_mem, 0, BONITO_PCIHI_SIZE);
719 memory_region_add_subregion(get_system_memory(),
720 BONITO_PCIHI_BASE, pcimem_alias);
721 create_unimplemented_device("PCI_2",
722 (hwaddr)BONITO_PCIHI_BASE + BONITO_PCIHI_SIZE,
723 2 * GiB);
724
725 /* set the default value of north bridge pci config */
726 pci_set_word(dev->config + PCI_COMMAND, 0x0000);
727 pci_set_word(dev->config + PCI_STATUS, 0x0000);
728 pci_set_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID, 0x0000);
729 pci_set_word(dev->config + PCI_SUBSYSTEM_ID, 0x0000);
730
731 pci_set_byte(dev->config + PCI_INTERRUPT_LINE, 0x00);
732 pci_set_byte(dev->config + PCI_INTERRUPT_PIN, 0x01);
733 pci_set_byte(dev->config + PCI_MIN_GNT, 0x3c);
734 pci_set_byte(dev->config + PCI_MAX_LAT, 0x00);
735
736 qemu_register_reset(bonito_reset, s);
737 }
738
739 PCIBus *bonito_init(qemu_irq *pic)
740 {
741 DeviceState *dev;
742 BonitoState *pcihost;
743 PCIHostState *phb;
744 PCIBonitoState *s;
745 PCIDevice *d;
746
747 dev = qdev_new(TYPE_BONITO_PCI_HOST_BRIDGE);
748 phb = PCI_HOST_BRIDGE(dev);
749 pcihost = BONITO_PCI_HOST_BRIDGE(dev);
750 pcihost->pic = pic;
751 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
752
753 d = pci_new(PCI_DEVFN(0, 0), TYPE_PCI_BONITO);
754 s = PCI_BONITO(d);
755 s->pcihost = pcihost;
756 pcihost->pci_dev = s;
757 pci_realize_and_unref(d, phb->bus, &error_fatal);
758
759 return phb->bus;
760 }
761
762 static void bonito_class_init(ObjectClass *klass, void *data)
763 {
764 DeviceClass *dc = DEVICE_CLASS(klass);
765 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
766
767 k->realize = bonito_realize;
768 k->vendor_id = 0xdf53;
769 k->device_id = 0x00d5;
770 k->revision = 0x01;
771 k->class_id = PCI_CLASS_BRIDGE_HOST;
772 dc->desc = "Host bridge";
773 dc->vmsd = &vmstate_bonito;
774 /*
775 * PCI-facing part of the host bridge, not usable without the
776 * host-facing part, which can't be device_add'ed, yet.
777 */
778 dc->user_creatable = false;
779 }
780
781 static const TypeInfo bonito_info = {
782 .name = TYPE_PCI_BONITO,
783 .parent = TYPE_PCI_DEVICE,
784 .instance_size = sizeof(PCIBonitoState),
785 .class_init = bonito_class_init,
786 .interfaces = (InterfaceInfo[]) {
787 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
788 { },
789 },
790 };
791
792 static void bonito_pcihost_class_init(ObjectClass *klass, void *data)
793 {
794 DeviceClass *dc = DEVICE_CLASS(klass);
795
796 dc->realize = bonito_pcihost_realize;
797 }
798
799 static const TypeInfo bonito_pcihost_info = {
800 .name = TYPE_BONITO_PCI_HOST_BRIDGE,
801 .parent = TYPE_PCI_HOST_BRIDGE,
802 .instance_size = sizeof(BonitoState),
803 .class_init = bonito_pcihost_class_init,
804 };
805
806 static void bonito_register_types(void)
807 {
808 type_register_static(&bonito_pcihost_info);
809 type_register_static(&bonito_info);
810 }
811
812 type_init(bonito_register_types)