qdev: Convert uses of qdev_set_parent_bus() with Coccinelle
[qemu.git] / hw / pci-host / gpex.c
1 /*
2 * QEMU Generic PCI Express Bridge Emulation
3 *
4 * Copyright (C) 2015 Alexander Graf <agraf@suse.de>
5 *
6 * Code loosely based on q35.c.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 * Check out these documents for more information on the device:
27 *
28 * http://www.kernel.org/doc/Documentation/devicetree/bindings/pci/host-generic-pci.txt
29 * http://www.firmware.org/1275/practice/imap/imap0_9d.pdf
30 */
31
32 #include "qemu/osdep.h"
33 #include "qapi/error.h"
34 #include "hw/irq.h"
35 #include "hw/pci-host/gpex.h"
36 #include "hw/qdev-properties.h"
37 #include "migration/vmstate.h"
38 #include "qemu/module.h"
39
40 /****************************************************************************
41 * GPEX host
42 */
43
44 static void gpex_set_irq(void *opaque, int irq_num, int level)
45 {
46 GPEXHost *s = opaque;
47
48 qemu_set_irq(s->irq[irq_num], level);
49 }
50
51 int gpex_set_irq_num(GPEXHost *s, int index, int gsi)
52 {
53 if (index >= GPEX_NUM_IRQS) {
54 return -EINVAL;
55 }
56
57 s->irq_num[index] = gsi;
58 return 0;
59 }
60
61 static PCIINTxRoute gpex_route_intx_pin_to_irq(void *opaque, int pin)
62 {
63 PCIINTxRoute route;
64 GPEXHost *s = opaque;
65 int gsi = s->irq_num[pin];
66
67 route.irq = gsi;
68 if (gsi < 0) {
69 route.mode = PCI_INTX_DISABLED;
70 } else {
71 route.mode = PCI_INTX_ENABLED;
72 }
73
74 return route;
75 }
76
77 static void gpex_host_realize(DeviceState *dev, Error **errp)
78 {
79 PCIHostState *pci = PCI_HOST_BRIDGE(dev);
80 GPEXHost *s = GPEX_HOST(dev);
81 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
82 PCIExpressHost *pex = PCIE_HOST_BRIDGE(dev);
83 int i;
84
85 pcie_host_mmcfg_init(pex, PCIE_MMCFG_SIZE_MAX);
86 memory_region_init(&s->io_mmio, OBJECT(s), "gpex_mmio", UINT64_MAX);
87 memory_region_init(&s->io_ioport, OBJECT(s), "gpex_ioport", 64 * 1024);
88
89 sysbus_init_mmio(sbd, &pex->mmio);
90 sysbus_init_mmio(sbd, &s->io_mmio);
91 sysbus_init_mmio(sbd, &s->io_ioport);
92 for (i = 0; i < GPEX_NUM_IRQS; i++) {
93 sysbus_init_irq(sbd, &s->irq[i]);
94 s->irq_num[i] = -1;
95 }
96
97 pci->bus = pci_register_root_bus(dev, "pcie.0", gpex_set_irq,
98 pci_swizzle_map_irq_fn, s, &s->io_mmio,
99 &s->io_ioport, 0, 4, TYPE_PCIE_BUS);
100
101 pci_bus_set_route_irq_fn(pci->bus, gpex_route_intx_pin_to_irq);
102 qdev_realize(DEVICE(&s->gpex_root), BUS(pci->bus), &error_fatal);
103 }
104
105 static const char *gpex_host_root_bus_path(PCIHostState *host_bridge,
106 PCIBus *rootbus)
107 {
108 return "0000:00";
109 }
110
111 static void gpex_host_class_init(ObjectClass *klass, void *data)
112 {
113 DeviceClass *dc = DEVICE_CLASS(klass);
114 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
115
116 hc->root_bus_path = gpex_host_root_bus_path;
117 dc->realize = gpex_host_realize;
118 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
119 dc->fw_name = "pci";
120 }
121
122 static void gpex_host_initfn(Object *obj)
123 {
124 GPEXHost *s = GPEX_HOST(obj);
125 GPEXRootState *root = &s->gpex_root;
126
127 object_initialize_child(obj, "gpex_root", root, sizeof(*root),
128 TYPE_GPEX_ROOT_DEVICE, &error_abort, NULL);
129 qdev_prop_set_int32(DEVICE(root), "addr", PCI_DEVFN(0, 0));
130 qdev_prop_set_bit(DEVICE(root), "multifunction", false);
131 }
132
133 static const TypeInfo gpex_host_info = {
134 .name = TYPE_GPEX_HOST,
135 .parent = TYPE_PCIE_HOST_BRIDGE,
136 .instance_size = sizeof(GPEXHost),
137 .instance_init = gpex_host_initfn,
138 .class_init = gpex_host_class_init,
139 };
140
141 /****************************************************************************
142 * GPEX Root D0:F0
143 */
144
145 static const VMStateDescription vmstate_gpex_root = {
146 .name = "gpex_root",
147 .version_id = 1,
148 .minimum_version_id = 1,
149 .fields = (VMStateField[]) {
150 VMSTATE_PCI_DEVICE(parent_obj, GPEXRootState),
151 VMSTATE_END_OF_LIST()
152 }
153 };
154
155 static void gpex_root_class_init(ObjectClass *klass, void *data)
156 {
157 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
158 DeviceClass *dc = DEVICE_CLASS(klass);
159
160 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
161 dc->desc = "QEMU generic PCIe host bridge";
162 dc->vmsd = &vmstate_gpex_root;
163 k->vendor_id = PCI_VENDOR_ID_REDHAT;
164 k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_HOST;
165 k->revision = 0;
166 k->class_id = PCI_CLASS_BRIDGE_HOST;
167 /*
168 * PCI-facing part of the host bridge, not usable without the
169 * host-facing part, which can't be device_add'ed, yet.
170 */
171 dc->user_creatable = false;
172 }
173
174 static const TypeInfo gpex_root_info = {
175 .name = TYPE_GPEX_ROOT_DEVICE,
176 .parent = TYPE_PCI_DEVICE,
177 .instance_size = sizeof(GPEXRootState),
178 .class_init = gpex_root_class_init,
179 .interfaces = (InterfaceInfo[]) {
180 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
181 { },
182 },
183 };
184
185 static void gpex_register(void)
186 {
187 type_register_static(&gpex_root_info);
188 type_register_static(&gpex_host_info);
189 }
190
191 type_init(gpex_register)