xen/pt: allow QEMU to request MSI unmasking at bind time
[qemu.git] / hw / pci-host / piix.c
1 /*
2 * QEMU i440FX/PIIX3 PCI Bridge Emulation
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "hw/hw.h"
27 #include "hw/i386/pc.h"
28 #include "hw/pci/pci.h"
29 #include "hw/pci/pci_host.h"
30 #include "hw/isa/isa.h"
31 #include "hw/sysbus.h"
32 #include "qapi/error.h"
33 #include "qemu/range.h"
34 #include "hw/xen/xen.h"
35 #include "hw/pci-host/pam.h"
36 #include "sysemu/sysemu.h"
37 #include "hw/i386/ioapic.h"
38 #include "qapi/visitor.h"
39 #include "qemu/error-report.h"
40
41 /*
42 * I440FX chipset data sheet.
43 * http://download.intel.com/design/chipsets/datashts/29054901.pdf
44 */
45
46 #define I440FX_PCI_HOST_BRIDGE(obj) \
47 OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_PCI_HOST_BRIDGE)
48
49 typedef struct I440FXState {
50 PCIHostState parent_obj;
51 Range pci_hole;
52 uint64_t pci_hole64_size;
53 uint32_t short_root_bus;
54 } I440FXState;
55
56 #define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
57 #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
58 #define XEN_PIIX_NUM_PIRQS 128ULL
59 #define PIIX_PIRQC 0x60
60
61 typedef struct PIIX3State {
62 PCIDevice dev;
63
64 /*
65 * bitmap to track pic levels.
66 * The pic level is the logical OR of all the PCI irqs mapped to it
67 * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
68 *
69 * PIRQ is mapped to PIC pins, we track it by
70 * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
71 * pic_irq * PIIX_NUM_PIRQS + pirq
72 */
73 #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
74 #error "unable to encode pic state in 64bit in pic_levels."
75 #endif
76 uint64_t pic_levels;
77
78 qemu_irq *pic;
79
80 /* This member isn't used. Just for save/load compatibility */
81 int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
82
83 /* Reset Control Register contents */
84 uint8_t rcr;
85
86 /* IO memory region for Reset Control Register (RCR_IOPORT) */
87 MemoryRegion rcr_mem;
88 } PIIX3State;
89
90 #define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
91 #define PIIX3_PCI_DEVICE(obj) \
92 OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE)
93
94 #define I440FX_PCI_DEVICE(obj) \
95 OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)
96
97 struct PCII440FXState {
98 /*< private >*/
99 PCIDevice parent_obj;
100 /*< public >*/
101
102 MemoryRegion *system_memory;
103 MemoryRegion *pci_address_space;
104 MemoryRegion *ram_memory;
105 PAMMemoryRegion pam_regions[13];
106 MemoryRegion smram_region;
107 MemoryRegion smram, low_smram;
108 };
109
110
111 #define I440FX_PAM 0x59
112 #define I440FX_PAM_SIZE 7
113 #define I440FX_SMRAM 0x72
114
115 /* Older coreboot versions (4.0 and older) read a config register that doesn't
116 * exist in real hardware, to get the RAM size from QEMU.
117 */
118 #define I440FX_COREBOOT_RAM_SIZE 0x57
119
120 static void piix3_set_irq(void *opaque, int pirq, int level);
121 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
122 static void piix3_write_config_xen(PCIDevice *dev,
123 uint32_t address, uint32_t val, int len);
124
125 /* return the global irq number corresponding to a given device irq
126 pin. We could also use the bus number to have a more precise
127 mapping. */
128 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
129 {
130 int slot_addend;
131 slot_addend = (pci_dev->devfn >> 3) - 1;
132 return (pci_intx + slot_addend) & 3;
133 }
134
135 static void i440fx_update_memory_mappings(PCII440FXState *d)
136 {
137 int i;
138 PCIDevice *pd = PCI_DEVICE(d);
139
140 memory_region_transaction_begin();
141 for (i = 0; i < 13; i++) {
142 pam_update(&d->pam_regions[i], i,
143 pd->config[I440FX_PAM + (DIV_ROUND_UP(i, 2))]);
144 }
145 memory_region_set_enabled(&d->smram_region,
146 !(pd->config[I440FX_SMRAM] & SMRAM_D_OPEN));
147 memory_region_set_enabled(&d->smram,
148 pd->config[I440FX_SMRAM] & SMRAM_G_SMRAME);
149 memory_region_transaction_commit();
150 }
151
152
153 static void i440fx_write_config(PCIDevice *dev,
154 uint32_t address, uint32_t val, int len)
155 {
156 PCII440FXState *d = I440FX_PCI_DEVICE(dev);
157
158 /* XXX: implement SMRAM.D_LOCK */
159 pci_default_write_config(dev, address, val, len);
160 if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
161 range_covers_byte(address, len, I440FX_SMRAM)) {
162 i440fx_update_memory_mappings(d);
163 }
164 }
165
166 static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
167 {
168 PCII440FXState *d = opaque;
169 PCIDevice *pd = PCI_DEVICE(d);
170 int ret, i;
171 uint8_t smm_enabled;
172
173 ret = pci_device_load(pd, f);
174 if (ret < 0)
175 return ret;
176 i440fx_update_memory_mappings(d);
177 qemu_get_8s(f, &smm_enabled);
178
179 if (version_id == 2) {
180 for (i = 0; i < PIIX_NUM_PIRQS; i++) {
181 qemu_get_be32(f); /* dummy load for compatibility */
182 }
183 }
184
185 return 0;
186 }
187
188 static int i440fx_post_load(void *opaque, int version_id)
189 {
190 PCII440FXState *d = opaque;
191
192 i440fx_update_memory_mappings(d);
193 return 0;
194 }
195
196 static const VMStateDescription vmstate_i440fx = {
197 .name = "I440FX",
198 .version_id = 3,
199 .minimum_version_id = 3,
200 .minimum_version_id_old = 1,
201 .load_state_old = i440fx_load_old,
202 .post_load = i440fx_post_load,
203 .fields = (VMStateField[]) {
204 VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
205 /* Used to be smm_enabled, which was basically always zero because
206 * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code.
207 */
208 VMSTATE_UNUSED(1),
209 VMSTATE_END_OF_LIST()
210 }
211 };
212
213 static void i440fx_pcihost_get_pci_hole_start(Object *obj, Visitor *v,
214 const char *name, void *opaque,
215 Error **errp)
216 {
217 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
218 uint64_t val64;
219 uint32_t value;
220
221 val64 = range_is_empty(&s->pci_hole) ? 0 : range_lob(&s->pci_hole);
222 value = val64;
223 assert(value == val64);
224 visit_type_uint32(v, name, &value, errp);
225 }
226
227 static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v,
228 const char *name, void *opaque,
229 Error **errp)
230 {
231 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
232 uint64_t val64;
233 uint32_t value;
234
235 val64 = range_is_empty(&s->pci_hole) ? 0 : range_upb(&s->pci_hole) + 1;
236 value = val64;
237 assert(value == val64);
238 visit_type_uint32(v, name, &value, errp);
239 }
240
241 static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v,
242 const char *name,
243 void *opaque, Error **errp)
244 {
245 PCIHostState *h = PCI_HOST_BRIDGE(obj);
246 Range w64;
247 uint64_t value;
248
249 pci_bus_get_w64_range(h->bus, &w64);
250 value = range_is_empty(&w64) ? 0 : range_lob(&w64);
251 visit_type_uint64(v, name, &value, errp);
252 }
253
254 static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v,
255 const char *name, void *opaque,
256 Error **errp)
257 {
258 PCIHostState *h = PCI_HOST_BRIDGE(obj);
259 Range w64;
260 uint64_t value;
261
262 pci_bus_get_w64_range(h->bus, &w64);
263 value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1;
264 visit_type_uint64(v, name, &value, errp);
265 }
266
267 static void i440fx_pcihost_initfn(Object *obj)
268 {
269 PCIHostState *s = PCI_HOST_BRIDGE(obj);
270
271 memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s,
272 "pci-conf-idx", 4);
273 memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s,
274 "pci-conf-data", 4);
275
276 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32",
277 i440fx_pcihost_get_pci_hole_start,
278 NULL, NULL, NULL, NULL);
279
280 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "uint32",
281 i440fx_pcihost_get_pci_hole_end,
282 NULL, NULL, NULL, NULL);
283
284 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "uint64",
285 i440fx_pcihost_get_pci_hole64_start,
286 NULL, NULL, NULL, NULL);
287
288 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "uint64",
289 i440fx_pcihost_get_pci_hole64_end,
290 NULL, NULL, NULL, NULL);
291 }
292
293 static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)
294 {
295 PCIHostState *s = PCI_HOST_BRIDGE(dev);
296 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
297
298 sysbus_add_io(sbd, 0xcf8, &s->conf_mem);
299 sysbus_init_ioports(sbd, 0xcf8, 4);
300
301 sysbus_add_io(sbd, 0xcfc, &s->data_mem);
302 sysbus_init_ioports(sbd, 0xcfc, 4);
303 }
304
305 static void i440fx_realize(PCIDevice *dev, Error **errp)
306 {
307 dev->config[I440FX_SMRAM] = 0x02;
308
309 if (object_property_get_bool(qdev_get_machine(), "iommu", NULL)) {
310 warn_report("i440fx doesn't support emulated iommu");
311 }
312 }
313
314 PCIBus *i440fx_init(const char *host_type, const char *pci_type,
315 PCII440FXState **pi440fx_state,
316 int *piix3_devfn,
317 ISABus **isa_bus, qemu_irq *pic,
318 MemoryRegion *address_space_mem,
319 MemoryRegion *address_space_io,
320 ram_addr_t ram_size,
321 ram_addr_t below_4g_mem_size,
322 ram_addr_t above_4g_mem_size,
323 MemoryRegion *pci_address_space,
324 MemoryRegion *ram_memory)
325 {
326 DeviceState *dev;
327 PCIBus *b;
328 PCIDevice *d;
329 PCIHostState *s;
330 PIIX3State *piix3;
331 PCII440FXState *f;
332 unsigned i;
333 I440FXState *i440fx;
334
335 dev = qdev_create(NULL, host_type);
336 s = PCI_HOST_BRIDGE(dev);
337 b = pci_bus_new(dev, NULL, pci_address_space,
338 address_space_io, 0, TYPE_PCI_BUS);
339 s->bus = b;
340 object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL);
341 qdev_init_nofail(dev);
342
343 d = pci_create_simple(b, 0, pci_type);
344 *pi440fx_state = I440FX_PCI_DEVICE(d);
345 f = *pi440fx_state;
346 f->system_memory = address_space_mem;
347 f->pci_address_space = pci_address_space;
348 f->ram_memory = ram_memory;
349
350 i440fx = I440FX_PCI_HOST_BRIDGE(dev);
351 range_set_bounds(&i440fx->pci_hole, below_4g_mem_size,
352 IO_APIC_DEFAULT_ADDRESS - 1);
353
354 /* setup pci memory mapping */
355 pc_pci_as_mapping_init(OBJECT(f), f->system_memory,
356 f->pci_address_space);
357
358 /* if *disabled* show SMRAM to all CPUs */
359 memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region",
360 f->pci_address_space, 0xa0000, 0x20000);
361 memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
362 &f->smram_region, 1);
363 memory_region_set_enabled(&f->smram_region, true);
364
365 /* smram, as seen by SMM CPUs */
366 memory_region_init(&f->smram, OBJECT(d), "smram", 1ull << 32);
367 memory_region_set_enabled(&f->smram, true);
368 memory_region_init_alias(&f->low_smram, OBJECT(d), "smram-low",
369 f->ram_memory, 0xa0000, 0x20000);
370 memory_region_set_enabled(&f->low_smram, true);
371 memory_region_add_subregion(&f->smram, 0xa0000, &f->low_smram);
372 object_property_add_const_link(qdev_get_machine(), "smram",
373 OBJECT(&f->smram), &error_abort);
374
375 init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
376 &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
377 for (i = 0; i < 12; ++i) {
378 init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
379 &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
380 PAM_EXPAN_SIZE);
381 }
382
383 /* Xen supports additional interrupt routes from the PCI devices to
384 * the IOAPIC: the four pins of each PCI device on the bus are also
385 * connected to the IOAPIC directly.
386 * These additional routes can be discovered through ACPI. */
387 if (xen_enabled()) {
388 PCIDevice *pci_dev = pci_create_simple_multifunction(b,
389 -1, true, "PIIX3-xen");
390 piix3 = PIIX3_PCI_DEVICE(pci_dev);
391 pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
392 piix3, XEN_PIIX_NUM_PIRQS);
393 } else {
394 PCIDevice *pci_dev = pci_create_simple_multifunction(b,
395 -1, true, "PIIX3");
396 piix3 = PIIX3_PCI_DEVICE(pci_dev);
397 pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
398 PIIX_NUM_PIRQS);
399 pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);
400 }
401 piix3->pic = pic;
402 *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
403
404 *piix3_devfn = piix3->dev.devfn;
405
406 ram_size = ram_size / 8 / 1024 / 1024;
407 if (ram_size > 255) {
408 ram_size = 255;
409 }
410 d->config[I440FX_COREBOOT_RAM_SIZE] = ram_size;
411
412 i440fx_update_memory_mappings(f);
413
414 return b;
415 }
416
417 PCIBus *find_i440fx(void)
418 {
419 PCIHostState *s = OBJECT_CHECK(PCIHostState,
420 object_resolve_path("/machine/i440fx", NULL),
421 TYPE_PCI_HOST_BRIDGE);
422 return s ? s->bus : NULL;
423 }
424
425 /* PIIX3 PCI to ISA bridge */
426 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
427 {
428 qemu_set_irq(piix3->pic[pic_irq],
429 !!(piix3->pic_levels &
430 (((1ULL << PIIX_NUM_PIRQS) - 1) <<
431 (pic_irq * PIIX_NUM_PIRQS))));
432 }
433
434 static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
435 {
436 int pic_irq;
437 uint64_t mask;
438
439 pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
440 if (pic_irq >= PIIX_NUM_PIC_IRQS) {
441 return;
442 }
443
444 mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
445 piix3->pic_levels &= ~mask;
446 piix3->pic_levels |= mask * !!level;
447 }
448
449 static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
450 {
451 int pic_irq;
452
453 pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
454 if (pic_irq >= PIIX_NUM_PIC_IRQS) {
455 return;
456 }
457
458 piix3_set_irq_level_internal(piix3, pirq, level);
459
460 piix3_set_irq_pic(piix3, pic_irq);
461 }
462
463 static void piix3_set_irq(void *opaque, int pirq, int level)
464 {
465 PIIX3State *piix3 = opaque;
466 piix3_set_irq_level(piix3, pirq, level);
467 }
468
469 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
470 {
471 PIIX3State *piix3 = opaque;
472 int irq = piix3->dev.config[PIIX_PIRQC + pin];
473 PCIINTxRoute route;
474
475 if (irq < PIIX_NUM_PIC_IRQS) {
476 route.mode = PCI_INTX_ENABLED;
477 route.irq = irq;
478 } else {
479 route.mode = PCI_INTX_DISABLED;
480 route.irq = -1;
481 }
482 return route;
483 }
484
485 /* irq routing is changed. so rebuild bitmap */
486 static void piix3_update_irq_levels(PIIX3State *piix3)
487 {
488 int pirq;
489
490 piix3->pic_levels = 0;
491 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
492 piix3_set_irq_level(piix3, pirq,
493 pci_bus_get_irq_level(piix3->dev.bus, pirq));
494 }
495 }
496
497 static void piix3_write_config(PCIDevice *dev,
498 uint32_t address, uint32_t val, int len)
499 {
500 pci_default_write_config(dev, address, val, len);
501 if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
502 PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
503 int pic_irq;
504
505 pci_bus_fire_intx_routing_notifier(piix3->dev.bus);
506 piix3_update_irq_levels(piix3);
507 for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
508 piix3_set_irq_pic(piix3, pic_irq);
509 }
510 }
511 }
512
513 static void piix3_write_config_xen(PCIDevice *dev,
514 uint32_t address, uint32_t val, int len)
515 {
516 xen_piix_pci_write_config_client(address, val, len);
517 piix3_write_config(dev, address, val, len);
518 }
519
520 static void piix3_reset(void *opaque)
521 {
522 PIIX3State *d = opaque;
523 uint8_t *pci_conf = d->dev.config;
524
525 pci_conf[0x04] = 0x07; /* master, memory and I/O */
526 pci_conf[0x05] = 0x00;
527 pci_conf[0x06] = 0x00;
528 pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
529 pci_conf[0x4c] = 0x4d;
530 pci_conf[0x4e] = 0x03;
531 pci_conf[0x4f] = 0x00;
532 pci_conf[0x60] = 0x80;
533 pci_conf[0x61] = 0x80;
534 pci_conf[0x62] = 0x80;
535 pci_conf[0x63] = 0x80;
536 pci_conf[0x69] = 0x02;
537 pci_conf[0x70] = 0x80;
538 pci_conf[0x76] = 0x0c;
539 pci_conf[0x77] = 0x0c;
540 pci_conf[0x78] = 0x02;
541 pci_conf[0x79] = 0x00;
542 pci_conf[0x80] = 0x00;
543 pci_conf[0x82] = 0x00;
544 pci_conf[0xa0] = 0x08;
545 pci_conf[0xa2] = 0x00;
546 pci_conf[0xa3] = 0x00;
547 pci_conf[0xa4] = 0x00;
548 pci_conf[0xa5] = 0x00;
549 pci_conf[0xa6] = 0x00;
550 pci_conf[0xa7] = 0x00;
551 pci_conf[0xa8] = 0x0f;
552 pci_conf[0xaa] = 0x00;
553 pci_conf[0xab] = 0x00;
554 pci_conf[0xac] = 0x00;
555 pci_conf[0xae] = 0x00;
556
557 d->pic_levels = 0;
558 d->rcr = 0;
559 }
560
561 static int piix3_post_load(void *opaque, int version_id)
562 {
563 PIIX3State *piix3 = opaque;
564 int pirq;
565
566 /* Because the i8259 has not been deserialized yet, qemu_irq_raise
567 * might bring the system to a different state than the saved one;
568 * for example, the interrupt could be masked but the i8259 would
569 * not know that yet and would trigger an interrupt in the CPU.
570 *
571 * Here, we update irq levels without raising the interrupt.
572 * Interrupt state will be deserialized separately through the i8259.
573 */
574 piix3->pic_levels = 0;
575 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
576 piix3_set_irq_level_internal(piix3, pirq,
577 pci_bus_get_irq_level(piix3->dev.bus, pirq));
578 }
579 return 0;
580 }
581
582 static void piix3_pre_save(void *opaque)
583 {
584 int i;
585 PIIX3State *piix3 = opaque;
586
587 for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
588 piix3->pci_irq_levels_vmstate[i] =
589 pci_bus_get_irq_level(piix3->dev.bus, i);
590 }
591 }
592
593 static bool piix3_rcr_needed(void *opaque)
594 {
595 PIIX3State *piix3 = opaque;
596
597 return (piix3->rcr != 0);
598 }
599
600 static const VMStateDescription vmstate_piix3_rcr = {
601 .name = "PIIX3/rcr",
602 .version_id = 1,
603 .minimum_version_id = 1,
604 .needed = piix3_rcr_needed,
605 .fields = (VMStateField[]) {
606 VMSTATE_UINT8(rcr, PIIX3State),
607 VMSTATE_END_OF_LIST()
608 }
609 };
610
611 static const VMStateDescription vmstate_piix3 = {
612 .name = "PIIX3",
613 .version_id = 3,
614 .minimum_version_id = 2,
615 .post_load = piix3_post_load,
616 .pre_save = piix3_pre_save,
617 .fields = (VMStateField[]) {
618 VMSTATE_PCI_DEVICE(dev, PIIX3State),
619 VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
620 PIIX_NUM_PIRQS, 3),
621 VMSTATE_END_OF_LIST()
622 },
623 .subsections = (const VMStateDescription*[]) {
624 &vmstate_piix3_rcr,
625 NULL
626 }
627 };
628
629
630 static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
631 {
632 PIIX3State *d = opaque;
633
634 if (val & 4) {
635 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
636 return;
637 }
638 d->rcr = val & 2; /* keep System Reset type only */
639 }
640
641 static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
642 {
643 PIIX3State *d = opaque;
644
645 return d->rcr;
646 }
647
648 static const MemoryRegionOps rcr_ops = {
649 .read = rcr_read,
650 .write = rcr_write,
651 .endianness = DEVICE_LITTLE_ENDIAN
652 };
653
654 static void piix3_realize(PCIDevice *dev, Error **errp)
655 {
656 PIIX3State *d = PIIX3_PCI_DEVICE(dev);
657
658 if (!isa_bus_new(DEVICE(d), get_system_memory(),
659 pci_address_space_io(dev), errp)) {
660 return;
661 }
662
663 memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
664 "piix3-reset-control", 1);
665 memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT,
666 &d->rcr_mem, 1);
667
668 qemu_register_reset(piix3_reset, d);
669 }
670
671 static void pci_piix3_class_init(ObjectClass *klass, void *data)
672 {
673 DeviceClass *dc = DEVICE_CLASS(klass);
674 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
675
676 dc->desc = "ISA bridge";
677 dc->vmsd = &vmstate_piix3;
678 dc->hotpluggable = false;
679 k->realize = piix3_realize;
680 k->vendor_id = PCI_VENDOR_ID_INTEL;
681 /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
682 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
683 k->class_id = PCI_CLASS_BRIDGE_ISA;
684 /*
685 * Reason: part of PIIX3 southbridge, needs to be wired up by
686 * pc_piix.c's pc_init1()
687 */
688 dc->user_creatable = false;
689 }
690
691 static const TypeInfo piix3_pci_type_info = {
692 .name = TYPE_PIIX3_PCI_DEVICE,
693 .parent = TYPE_PCI_DEVICE,
694 .instance_size = sizeof(PIIX3State),
695 .abstract = true,
696 .class_init = pci_piix3_class_init,
697 };
698
699 static void piix3_class_init(ObjectClass *klass, void *data)
700 {
701 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
702
703 k->config_write = piix3_write_config;
704 }
705
706 static const TypeInfo piix3_info = {
707 .name = "PIIX3",
708 .parent = TYPE_PIIX3_PCI_DEVICE,
709 .class_init = piix3_class_init,
710 };
711
712 static void piix3_xen_class_init(ObjectClass *klass, void *data)
713 {
714 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
715
716 k->config_write = piix3_write_config_xen;
717 };
718
719 static const TypeInfo piix3_xen_info = {
720 .name = "PIIX3-xen",
721 .parent = TYPE_PIIX3_PCI_DEVICE,
722 .class_init = piix3_xen_class_init,
723 };
724
725 static void i440fx_class_init(ObjectClass *klass, void *data)
726 {
727 DeviceClass *dc = DEVICE_CLASS(klass);
728 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
729
730 k->realize = i440fx_realize;
731 k->config_write = i440fx_write_config;
732 k->vendor_id = PCI_VENDOR_ID_INTEL;
733 k->device_id = PCI_DEVICE_ID_INTEL_82441;
734 k->revision = 0x02;
735 k->class_id = PCI_CLASS_BRIDGE_HOST;
736 dc->desc = "Host bridge";
737 dc->vmsd = &vmstate_i440fx;
738 /*
739 * PCI-facing part of the host bridge, not usable without the
740 * host-facing part, which can't be device_add'ed, yet.
741 */
742 dc->user_creatable = false;
743 dc->hotpluggable = false;
744 }
745
746 static const TypeInfo i440fx_info = {
747 .name = TYPE_I440FX_PCI_DEVICE,
748 .parent = TYPE_PCI_DEVICE,
749 .instance_size = sizeof(PCII440FXState),
750 .class_init = i440fx_class_init,
751 };
752
753 /* IGD Passthrough Host Bridge. */
754 typedef struct {
755 uint8_t offset;
756 uint8_t len;
757 } IGDHostInfo;
758
759 /* Here we just expose minimal host bridge offset subset. */
760 static const IGDHostInfo igd_host_bridge_infos[] = {
761 {0x08, 2}, /* revision id */
762 {0x2c, 2}, /* sybsystem vendor id */
763 {0x2e, 2}, /* sybsystem id */
764 {0x50, 2}, /* SNB: processor graphics control register */
765 {0x52, 2}, /* processor graphics control register */
766 {0xa4, 4}, /* SNB: graphics base of stolen memory */
767 {0xa8, 4}, /* SNB: base of GTT stolen memory */
768 };
769
770 static int host_pci_config_read(int pos, int len, uint32_t *val)
771 {
772 char path[PATH_MAX];
773 int config_fd;
774 ssize_t size = sizeof(path);
775 /* Access real host bridge. */
776 int rc = snprintf(path, size, "/sys/bus/pci/devices/%04x:%02x:%02x.%d/%s",
777 0, 0, 0, 0, "config");
778 int ret = 0;
779
780 if (rc >= size || rc < 0) {
781 return -ENODEV;
782 }
783
784 config_fd = open(path, O_RDWR);
785 if (config_fd < 0) {
786 return -ENODEV;
787 }
788
789 if (lseek(config_fd, pos, SEEK_SET) != pos) {
790 ret = -errno;
791 goto out;
792 }
793
794 do {
795 rc = read(config_fd, (uint8_t *)val, len);
796 } while (rc < 0 && (errno == EINTR || errno == EAGAIN));
797 if (rc != len) {
798 ret = -errno;
799 }
800
801 out:
802 close(config_fd);
803 return ret;
804 }
805
806 static int igd_pt_i440fx_initfn(struct PCIDevice *pci_dev)
807 {
808 uint32_t val = 0;
809 int rc, i, num;
810 int pos, len;
811
812 num = ARRAY_SIZE(igd_host_bridge_infos);
813 for (i = 0; i < num; i++) {
814 pos = igd_host_bridge_infos[i].offset;
815 len = igd_host_bridge_infos[i].len;
816 rc = host_pci_config_read(pos, len, &val);
817 if (rc) {
818 return -ENODEV;
819 }
820 pci_default_write_config(pci_dev, pos, val, len);
821 }
822
823 return 0;
824 }
825
826 static void igd_passthrough_i440fx_class_init(ObjectClass *klass, void *data)
827 {
828 DeviceClass *dc = DEVICE_CLASS(klass);
829 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
830
831 k->init = igd_pt_i440fx_initfn;
832 dc->desc = "IGD Passthrough Host bridge";
833 }
834
835 static const TypeInfo igd_passthrough_i440fx_info = {
836 .name = TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE,
837 .parent = TYPE_I440FX_PCI_DEVICE,
838 .instance_size = sizeof(PCII440FXState),
839 .class_init = igd_passthrough_i440fx_class_init,
840 };
841
842 static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge,
843 PCIBus *rootbus)
844 {
845 I440FXState *s = I440FX_PCI_HOST_BRIDGE(host_bridge);
846
847 /* For backwards compat with old device paths */
848 if (s->short_root_bus) {
849 return "0000";
850 }
851 return "0000:00";
852 }
853
854 static Property i440fx_props[] = {
855 DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState,
856 pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE),
857 DEFINE_PROP_UINT32("short_root_bus", I440FXState, short_root_bus, 0),
858 DEFINE_PROP_END_OF_LIST(),
859 };
860
861 static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
862 {
863 DeviceClass *dc = DEVICE_CLASS(klass);
864 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
865
866 hc->root_bus_path = i440fx_pcihost_root_bus_path;
867 dc->realize = i440fx_pcihost_realize;
868 dc->fw_name = "pci";
869 dc->props = i440fx_props;
870 /* Reason: needs to be wired up by pc_init1 */
871 dc->user_creatable = false;
872 }
873
874 static const TypeInfo i440fx_pcihost_info = {
875 .name = TYPE_I440FX_PCI_HOST_BRIDGE,
876 .parent = TYPE_PCI_HOST_BRIDGE,
877 .instance_size = sizeof(I440FXState),
878 .instance_init = i440fx_pcihost_initfn,
879 .class_init = i440fx_pcihost_class_init,
880 };
881
882 static void i440fx_register_types(void)
883 {
884 type_register_static(&i440fx_info);
885 type_register_static(&igd_passthrough_i440fx_info);
886 type_register_static(&piix3_pci_type_info);
887 type_register_static(&piix3_info);
888 type_register_static(&piix3_xen_info);
889 type_register_static(&i440fx_pcihost_info);
890 }
891
892 type_init(i440fx_register_types)