sm501: Add missing arbitration control register
[qemu.git] / hw / pci-host / piix.c
1 /*
2 * QEMU i440FX/PIIX3 PCI Bridge Emulation
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "hw/hw.h"
27 #include "hw/i386/pc.h"
28 #include "hw/pci/pci.h"
29 #include "hw/pci/pci_host.h"
30 #include "hw/isa/isa.h"
31 #include "hw/sysbus.h"
32 #include "qapi/error.h"
33 #include "qemu/range.h"
34 #include "hw/xen/xen.h"
35 #include "hw/pci-host/pam.h"
36 #include "sysemu/sysemu.h"
37 #include "hw/i386/ioapic.h"
38 #include "qapi/visitor.h"
39 #include "qemu/error-report.h"
40
41 /*
42 * I440FX chipset data sheet.
43 * http://download.intel.com/design/chipsets/datashts/29054901.pdf
44 */
45
46 #define I440FX_PCI_HOST_BRIDGE(obj) \
47 OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_PCI_HOST_BRIDGE)
48
49 typedef struct I440FXState {
50 PCIHostState parent_obj;
51 Range pci_hole;
52 uint64_t pci_hole64_size;
53 uint32_t short_root_bus;
54 } I440FXState;
55
56 #define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
57 #define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
58 #define XEN_PIIX_NUM_PIRQS 128ULL
59 #define PIIX_PIRQC 0x60
60
61 /*
62 * Reset Control Register: PCI-accessible ISA-Compatible Register at address
63 * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
64 */
65 #define RCR_IOPORT 0xcf9
66
67 typedef struct PIIX3State {
68 PCIDevice dev;
69
70 /*
71 * bitmap to track pic levels.
72 * The pic level is the logical OR of all the PCI irqs mapped to it
73 * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
74 *
75 * PIRQ is mapped to PIC pins, we track it by
76 * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
77 * pic_irq * PIIX_NUM_PIRQS + pirq
78 */
79 #if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
80 #error "unable to encode pic state in 64bit in pic_levels."
81 #endif
82 uint64_t pic_levels;
83
84 qemu_irq *pic;
85
86 /* This member isn't used. Just for save/load compatibility */
87 int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
88
89 /* Reset Control Register contents */
90 uint8_t rcr;
91
92 /* IO memory region for Reset Control Register (RCR_IOPORT) */
93 MemoryRegion rcr_mem;
94 } PIIX3State;
95
96 #define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
97 #define PIIX3_PCI_DEVICE(obj) \
98 OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE)
99
100 #define I440FX_PCI_DEVICE(obj) \
101 OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)
102
103 struct PCII440FXState {
104 /*< private >*/
105 PCIDevice parent_obj;
106 /*< public >*/
107
108 MemoryRegion *system_memory;
109 MemoryRegion *pci_address_space;
110 MemoryRegion *ram_memory;
111 PAMMemoryRegion pam_regions[13];
112 MemoryRegion smram_region;
113 MemoryRegion smram, low_smram;
114 };
115
116
117 #define I440FX_PAM 0x59
118 #define I440FX_PAM_SIZE 7
119 #define I440FX_SMRAM 0x72
120
121 /* Older coreboot versions (4.0 and older) read a config register that doesn't
122 * exist in real hardware, to get the RAM size from QEMU.
123 */
124 #define I440FX_COREBOOT_RAM_SIZE 0x57
125
126 static void piix3_set_irq(void *opaque, int pirq, int level);
127 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
128 static void piix3_write_config_xen(PCIDevice *dev,
129 uint32_t address, uint32_t val, int len);
130
131 /* return the global irq number corresponding to a given device irq
132 pin. We could also use the bus number to have a more precise
133 mapping. */
134 static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
135 {
136 int slot_addend;
137 slot_addend = (pci_dev->devfn >> 3) - 1;
138 return (pci_intx + slot_addend) & 3;
139 }
140
141 static void i440fx_update_memory_mappings(PCII440FXState *d)
142 {
143 int i;
144 PCIDevice *pd = PCI_DEVICE(d);
145
146 memory_region_transaction_begin();
147 for (i = 0; i < 13; i++) {
148 pam_update(&d->pam_regions[i], i,
149 pd->config[I440FX_PAM + ((i + 1) / 2)]);
150 }
151 memory_region_set_enabled(&d->smram_region,
152 !(pd->config[I440FX_SMRAM] & SMRAM_D_OPEN));
153 memory_region_set_enabled(&d->smram,
154 pd->config[I440FX_SMRAM] & SMRAM_G_SMRAME);
155 memory_region_transaction_commit();
156 }
157
158
159 static void i440fx_write_config(PCIDevice *dev,
160 uint32_t address, uint32_t val, int len)
161 {
162 PCII440FXState *d = I440FX_PCI_DEVICE(dev);
163
164 /* XXX: implement SMRAM.D_LOCK */
165 pci_default_write_config(dev, address, val, len);
166 if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
167 range_covers_byte(address, len, I440FX_SMRAM)) {
168 i440fx_update_memory_mappings(d);
169 }
170 }
171
172 static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
173 {
174 PCII440FXState *d = opaque;
175 PCIDevice *pd = PCI_DEVICE(d);
176 int ret, i;
177 uint8_t smm_enabled;
178
179 ret = pci_device_load(pd, f);
180 if (ret < 0)
181 return ret;
182 i440fx_update_memory_mappings(d);
183 qemu_get_8s(f, &smm_enabled);
184
185 if (version_id == 2) {
186 for (i = 0; i < PIIX_NUM_PIRQS; i++) {
187 qemu_get_be32(f); /* dummy load for compatibility */
188 }
189 }
190
191 return 0;
192 }
193
194 static int i440fx_post_load(void *opaque, int version_id)
195 {
196 PCII440FXState *d = opaque;
197
198 i440fx_update_memory_mappings(d);
199 return 0;
200 }
201
202 static const VMStateDescription vmstate_i440fx = {
203 .name = "I440FX",
204 .version_id = 3,
205 .minimum_version_id = 3,
206 .minimum_version_id_old = 1,
207 .load_state_old = i440fx_load_old,
208 .post_load = i440fx_post_load,
209 .fields = (VMStateField[]) {
210 VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
211 /* Used to be smm_enabled, which was basically always zero because
212 * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code.
213 */
214 VMSTATE_UNUSED(1),
215 VMSTATE_END_OF_LIST()
216 }
217 };
218
219 static void i440fx_pcihost_get_pci_hole_start(Object *obj, Visitor *v,
220 const char *name, void *opaque,
221 Error **errp)
222 {
223 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
224 uint64_t val64;
225 uint32_t value;
226
227 val64 = range_is_empty(&s->pci_hole) ? 0 : range_lob(&s->pci_hole);
228 value = val64;
229 assert(value == val64);
230 visit_type_uint32(v, name, &value, errp);
231 }
232
233 static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v,
234 const char *name, void *opaque,
235 Error **errp)
236 {
237 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
238 uint64_t val64;
239 uint32_t value;
240
241 val64 = range_is_empty(&s->pci_hole) ? 0 : range_upb(&s->pci_hole) + 1;
242 value = val64;
243 assert(value == val64);
244 visit_type_uint32(v, name, &value, errp);
245 }
246
247 static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v,
248 const char *name,
249 void *opaque, Error **errp)
250 {
251 PCIHostState *h = PCI_HOST_BRIDGE(obj);
252 Range w64;
253 uint64_t value;
254
255 pci_bus_get_w64_range(h->bus, &w64);
256 value = range_is_empty(&w64) ? 0 : range_lob(&w64);
257 visit_type_uint64(v, name, &value, errp);
258 }
259
260 static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v,
261 const char *name, void *opaque,
262 Error **errp)
263 {
264 PCIHostState *h = PCI_HOST_BRIDGE(obj);
265 Range w64;
266 uint64_t value;
267
268 pci_bus_get_w64_range(h->bus, &w64);
269 value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1;
270 visit_type_uint64(v, name, &value, errp);
271 }
272
273 static void i440fx_pcihost_initfn(Object *obj)
274 {
275 PCIHostState *s = PCI_HOST_BRIDGE(obj);
276
277 memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s,
278 "pci-conf-idx", 4);
279 memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s,
280 "pci-conf-data", 4);
281
282 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int",
283 i440fx_pcihost_get_pci_hole_start,
284 NULL, NULL, NULL, NULL);
285
286 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "int",
287 i440fx_pcihost_get_pci_hole_end,
288 NULL, NULL, NULL, NULL);
289
290 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "int",
291 i440fx_pcihost_get_pci_hole64_start,
292 NULL, NULL, NULL, NULL);
293
294 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "int",
295 i440fx_pcihost_get_pci_hole64_end,
296 NULL, NULL, NULL, NULL);
297 }
298
299 static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)
300 {
301 PCIHostState *s = PCI_HOST_BRIDGE(dev);
302 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
303
304 sysbus_add_io(sbd, 0xcf8, &s->conf_mem);
305 sysbus_init_ioports(sbd, 0xcf8, 4);
306
307 sysbus_add_io(sbd, 0xcfc, &s->data_mem);
308 sysbus_init_ioports(sbd, 0xcfc, 4);
309 }
310
311 static void i440fx_realize(PCIDevice *dev, Error **errp)
312 {
313 dev->config[I440FX_SMRAM] = 0x02;
314
315 if (object_property_get_bool(qdev_get_machine(), "iommu", NULL)) {
316 error_report("warning: i440fx doesn't support emulated iommu");
317 }
318 }
319
320 PCIBus *i440fx_init(const char *host_type, const char *pci_type,
321 PCII440FXState **pi440fx_state,
322 int *piix3_devfn,
323 ISABus **isa_bus, qemu_irq *pic,
324 MemoryRegion *address_space_mem,
325 MemoryRegion *address_space_io,
326 ram_addr_t ram_size,
327 ram_addr_t below_4g_mem_size,
328 ram_addr_t above_4g_mem_size,
329 MemoryRegion *pci_address_space,
330 MemoryRegion *ram_memory)
331 {
332 DeviceState *dev;
333 PCIBus *b;
334 PCIDevice *d;
335 PCIHostState *s;
336 PIIX3State *piix3;
337 PCII440FXState *f;
338 unsigned i;
339 I440FXState *i440fx;
340
341 dev = qdev_create(NULL, host_type);
342 s = PCI_HOST_BRIDGE(dev);
343 b = pci_bus_new(dev, NULL, pci_address_space,
344 address_space_io, 0, TYPE_PCI_BUS);
345 s->bus = b;
346 object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL);
347 qdev_init_nofail(dev);
348
349 d = pci_create_simple(b, 0, pci_type);
350 *pi440fx_state = I440FX_PCI_DEVICE(d);
351 f = *pi440fx_state;
352 f->system_memory = address_space_mem;
353 f->pci_address_space = pci_address_space;
354 f->ram_memory = ram_memory;
355
356 i440fx = I440FX_PCI_HOST_BRIDGE(dev);
357 range_set_bounds(&i440fx->pci_hole, below_4g_mem_size,
358 IO_APIC_DEFAULT_ADDRESS - 1);
359
360 /* setup pci memory mapping */
361 pc_pci_as_mapping_init(OBJECT(f), f->system_memory,
362 f->pci_address_space);
363
364 /* if *disabled* show SMRAM to all CPUs */
365 memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region",
366 f->pci_address_space, 0xa0000, 0x20000);
367 memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
368 &f->smram_region, 1);
369 memory_region_set_enabled(&f->smram_region, true);
370
371 /* smram, as seen by SMM CPUs */
372 memory_region_init(&f->smram, OBJECT(d), "smram", 1ull << 32);
373 memory_region_set_enabled(&f->smram, true);
374 memory_region_init_alias(&f->low_smram, OBJECT(d), "smram-low",
375 f->ram_memory, 0xa0000, 0x20000);
376 memory_region_set_enabled(&f->low_smram, true);
377 memory_region_add_subregion(&f->smram, 0xa0000, &f->low_smram);
378 object_property_add_const_link(qdev_get_machine(), "smram",
379 OBJECT(&f->smram), &error_abort);
380
381 init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
382 &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
383 for (i = 0; i < 12; ++i) {
384 init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
385 &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
386 PAM_EXPAN_SIZE);
387 }
388
389 /* Xen supports additional interrupt routes from the PCI devices to
390 * the IOAPIC: the four pins of each PCI device on the bus are also
391 * connected to the IOAPIC directly.
392 * These additional routes can be discovered through ACPI. */
393 if (xen_enabled()) {
394 PCIDevice *pci_dev = pci_create_simple_multifunction(b,
395 -1, true, "PIIX3-xen");
396 piix3 = PIIX3_PCI_DEVICE(pci_dev);
397 pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
398 piix3, XEN_PIIX_NUM_PIRQS);
399 } else {
400 PCIDevice *pci_dev = pci_create_simple_multifunction(b,
401 -1, true, "PIIX3");
402 piix3 = PIIX3_PCI_DEVICE(pci_dev);
403 pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
404 PIIX_NUM_PIRQS);
405 pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);
406 }
407 piix3->pic = pic;
408 *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
409
410 *piix3_devfn = piix3->dev.devfn;
411
412 ram_size = ram_size / 8 / 1024 / 1024;
413 if (ram_size > 255) {
414 ram_size = 255;
415 }
416 d->config[I440FX_COREBOOT_RAM_SIZE] = ram_size;
417
418 i440fx_update_memory_mappings(f);
419
420 return b;
421 }
422
423 PCIBus *find_i440fx(void)
424 {
425 PCIHostState *s = OBJECT_CHECK(PCIHostState,
426 object_resolve_path("/machine/i440fx", NULL),
427 TYPE_PCI_HOST_BRIDGE);
428 return s ? s->bus : NULL;
429 }
430
431 /* PIIX3 PCI to ISA bridge */
432 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
433 {
434 qemu_set_irq(piix3->pic[pic_irq],
435 !!(piix3->pic_levels &
436 (((1ULL << PIIX_NUM_PIRQS) - 1) <<
437 (pic_irq * PIIX_NUM_PIRQS))));
438 }
439
440 static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
441 {
442 int pic_irq;
443 uint64_t mask;
444
445 pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
446 if (pic_irq >= PIIX_NUM_PIC_IRQS) {
447 return;
448 }
449
450 mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
451 piix3->pic_levels &= ~mask;
452 piix3->pic_levels |= mask * !!level;
453 }
454
455 static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
456 {
457 int pic_irq;
458
459 pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
460 if (pic_irq >= PIIX_NUM_PIC_IRQS) {
461 return;
462 }
463
464 piix3_set_irq_level_internal(piix3, pirq, level);
465
466 piix3_set_irq_pic(piix3, pic_irq);
467 }
468
469 static void piix3_set_irq(void *opaque, int pirq, int level)
470 {
471 PIIX3State *piix3 = opaque;
472 piix3_set_irq_level(piix3, pirq, level);
473 }
474
475 static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
476 {
477 PIIX3State *piix3 = opaque;
478 int irq = piix3->dev.config[PIIX_PIRQC + pin];
479 PCIINTxRoute route;
480
481 if (irq < PIIX_NUM_PIC_IRQS) {
482 route.mode = PCI_INTX_ENABLED;
483 route.irq = irq;
484 } else {
485 route.mode = PCI_INTX_DISABLED;
486 route.irq = -1;
487 }
488 return route;
489 }
490
491 /* irq routing is changed. so rebuild bitmap */
492 static void piix3_update_irq_levels(PIIX3State *piix3)
493 {
494 int pirq;
495
496 piix3->pic_levels = 0;
497 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
498 piix3_set_irq_level(piix3, pirq,
499 pci_bus_get_irq_level(piix3->dev.bus, pirq));
500 }
501 }
502
503 static void piix3_write_config(PCIDevice *dev,
504 uint32_t address, uint32_t val, int len)
505 {
506 pci_default_write_config(dev, address, val, len);
507 if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
508 PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
509 int pic_irq;
510
511 pci_bus_fire_intx_routing_notifier(piix3->dev.bus);
512 piix3_update_irq_levels(piix3);
513 for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
514 piix3_set_irq_pic(piix3, pic_irq);
515 }
516 }
517 }
518
519 static void piix3_write_config_xen(PCIDevice *dev,
520 uint32_t address, uint32_t val, int len)
521 {
522 xen_piix_pci_write_config_client(address, val, len);
523 piix3_write_config(dev, address, val, len);
524 }
525
526 static void piix3_reset(void *opaque)
527 {
528 PIIX3State *d = opaque;
529 uint8_t *pci_conf = d->dev.config;
530
531 pci_conf[0x04] = 0x07; /* master, memory and I/O */
532 pci_conf[0x05] = 0x00;
533 pci_conf[0x06] = 0x00;
534 pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
535 pci_conf[0x4c] = 0x4d;
536 pci_conf[0x4e] = 0x03;
537 pci_conf[0x4f] = 0x00;
538 pci_conf[0x60] = 0x80;
539 pci_conf[0x61] = 0x80;
540 pci_conf[0x62] = 0x80;
541 pci_conf[0x63] = 0x80;
542 pci_conf[0x69] = 0x02;
543 pci_conf[0x70] = 0x80;
544 pci_conf[0x76] = 0x0c;
545 pci_conf[0x77] = 0x0c;
546 pci_conf[0x78] = 0x02;
547 pci_conf[0x79] = 0x00;
548 pci_conf[0x80] = 0x00;
549 pci_conf[0x82] = 0x00;
550 pci_conf[0xa0] = 0x08;
551 pci_conf[0xa2] = 0x00;
552 pci_conf[0xa3] = 0x00;
553 pci_conf[0xa4] = 0x00;
554 pci_conf[0xa5] = 0x00;
555 pci_conf[0xa6] = 0x00;
556 pci_conf[0xa7] = 0x00;
557 pci_conf[0xa8] = 0x0f;
558 pci_conf[0xaa] = 0x00;
559 pci_conf[0xab] = 0x00;
560 pci_conf[0xac] = 0x00;
561 pci_conf[0xae] = 0x00;
562
563 d->pic_levels = 0;
564 d->rcr = 0;
565 }
566
567 static int piix3_post_load(void *opaque, int version_id)
568 {
569 PIIX3State *piix3 = opaque;
570 int pirq;
571
572 /* Because the i8259 has not been deserialized yet, qemu_irq_raise
573 * might bring the system to a different state than the saved one;
574 * for example, the interrupt could be masked but the i8259 would
575 * not know that yet and would trigger an interrupt in the CPU.
576 *
577 * Here, we update irq levels without raising the interrupt.
578 * Interrupt state will be deserialized separately through the i8259.
579 */
580 piix3->pic_levels = 0;
581 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
582 piix3_set_irq_level_internal(piix3, pirq,
583 pci_bus_get_irq_level(piix3->dev.bus, pirq));
584 }
585 return 0;
586 }
587
588 static void piix3_pre_save(void *opaque)
589 {
590 int i;
591 PIIX3State *piix3 = opaque;
592
593 for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
594 piix3->pci_irq_levels_vmstate[i] =
595 pci_bus_get_irq_level(piix3->dev.bus, i);
596 }
597 }
598
599 static bool piix3_rcr_needed(void *opaque)
600 {
601 PIIX3State *piix3 = opaque;
602
603 return (piix3->rcr != 0);
604 }
605
606 static const VMStateDescription vmstate_piix3_rcr = {
607 .name = "PIIX3/rcr",
608 .version_id = 1,
609 .minimum_version_id = 1,
610 .needed = piix3_rcr_needed,
611 .fields = (VMStateField[]) {
612 VMSTATE_UINT8(rcr, PIIX3State),
613 VMSTATE_END_OF_LIST()
614 }
615 };
616
617 static const VMStateDescription vmstate_piix3 = {
618 .name = "PIIX3",
619 .version_id = 3,
620 .minimum_version_id = 2,
621 .post_load = piix3_post_load,
622 .pre_save = piix3_pre_save,
623 .fields = (VMStateField[]) {
624 VMSTATE_PCI_DEVICE(dev, PIIX3State),
625 VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
626 PIIX_NUM_PIRQS, 3),
627 VMSTATE_END_OF_LIST()
628 },
629 .subsections = (const VMStateDescription*[]) {
630 &vmstate_piix3_rcr,
631 NULL
632 }
633 };
634
635
636 static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
637 {
638 PIIX3State *d = opaque;
639
640 if (val & 4) {
641 qemu_system_reset_request();
642 return;
643 }
644 d->rcr = val & 2; /* keep System Reset type only */
645 }
646
647 static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
648 {
649 PIIX3State *d = opaque;
650
651 return d->rcr;
652 }
653
654 static const MemoryRegionOps rcr_ops = {
655 .read = rcr_read,
656 .write = rcr_write,
657 .endianness = DEVICE_LITTLE_ENDIAN
658 };
659
660 static void piix3_realize(PCIDevice *dev, Error **errp)
661 {
662 PIIX3State *d = PIIX3_PCI_DEVICE(dev);
663
664 if (!isa_bus_new(DEVICE(d), get_system_memory(),
665 pci_address_space_io(dev), errp)) {
666 return;
667 }
668
669 memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
670 "piix3-reset-control", 1);
671 memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT,
672 &d->rcr_mem, 1);
673
674 qemu_register_reset(piix3_reset, d);
675 }
676
677 static void pci_piix3_class_init(ObjectClass *klass, void *data)
678 {
679 DeviceClass *dc = DEVICE_CLASS(klass);
680 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
681
682 dc->desc = "ISA bridge";
683 dc->vmsd = &vmstate_piix3;
684 dc->hotpluggable = false;
685 k->realize = piix3_realize;
686 k->vendor_id = PCI_VENDOR_ID_INTEL;
687 /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
688 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
689 k->class_id = PCI_CLASS_BRIDGE_ISA;
690 /*
691 * Reason: part of PIIX3 southbridge, needs to be wired up by
692 * pc_piix.c's pc_init1()
693 */
694 dc->cannot_instantiate_with_device_add_yet = true;
695 }
696
697 static const TypeInfo piix3_pci_type_info = {
698 .name = TYPE_PIIX3_PCI_DEVICE,
699 .parent = TYPE_PCI_DEVICE,
700 .instance_size = sizeof(PIIX3State),
701 .abstract = true,
702 .class_init = pci_piix3_class_init,
703 };
704
705 static void piix3_class_init(ObjectClass *klass, void *data)
706 {
707 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
708
709 k->config_write = piix3_write_config;
710 }
711
712 static const TypeInfo piix3_info = {
713 .name = "PIIX3",
714 .parent = TYPE_PIIX3_PCI_DEVICE,
715 .class_init = piix3_class_init,
716 };
717
718 static void piix3_xen_class_init(ObjectClass *klass, void *data)
719 {
720 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
721
722 k->config_write = piix3_write_config_xen;
723 };
724
725 static const TypeInfo piix3_xen_info = {
726 .name = "PIIX3-xen",
727 .parent = TYPE_PIIX3_PCI_DEVICE,
728 .class_init = piix3_xen_class_init,
729 };
730
731 static void i440fx_class_init(ObjectClass *klass, void *data)
732 {
733 DeviceClass *dc = DEVICE_CLASS(klass);
734 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
735
736 k->realize = i440fx_realize;
737 k->config_write = i440fx_write_config;
738 k->vendor_id = PCI_VENDOR_ID_INTEL;
739 k->device_id = PCI_DEVICE_ID_INTEL_82441;
740 k->revision = 0x02;
741 k->class_id = PCI_CLASS_BRIDGE_HOST;
742 dc->desc = "Host bridge";
743 dc->vmsd = &vmstate_i440fx;
744 /*
745 * PCI-facing part of the host bridge, not usable without the
746 * host-facing part, which can't be device_add'ed, yet.
747 */
748 dc->cannot_instantiate_with_device_add_yet = true;
749 dc->hotpluggable = false;
750 }
751
752 static const TypeInfo i440fx_info = {
753 .name = TYPE_I440FX_PCI_DEVICE,
754 .parent = TYPE_PCI_DEVICE,
755 .instance_size = sizeof(PCII440FXState),
756 .class_init = i440fx_class_init,
757 };
758
759 /* IGD Passthrough Host Bridge. */
760 typedef struct {
761 uint8_t offset;
762 uint8_t len;
763 } IGDHostInfo;
764
765 /* Here we just expose minimal host bridge offset subset. */
766 static const IGDHostInfo igd_host_bridge_infos[] = {
767 {0x08, 2}, /* revision id */
768 {0x2c, 2}, /* sybsystem vendor id */
769 {0x2e, 2}, /* sybsystem id */
770 {0x50, 2}, /* SNB: processor graphics control register */
771 {0x52, 2}, /* processor graphics control register */
772 {0xa4, 4}, /* SNB: graphics base of stolen memory */
773 {0xa8, 4}, /* SNB: base of GTT stolen memory */
774 };
775
776 static int host_pci_config_read(int pos, int len, uint32_t *val)
777 {
778 char path[PATH_MAX];
779 int config_fd;
780 ssize_t size = sizeof(path);
781 /* Access real host bridge. */
782 int rc = snprintf(path, size, "/sys/bus/pci/devices/%04x:%02x:%02x.%d/%s",
783 0, 0, 0, 0, "config");
784 int ret = 0;
785
786 if (rc >= size || rc < 0) {
787 return -ENODEV;
788 }
789
790 config_fd = open(path, O_RDWR);
791 if (config_fd < 0) {
792 return -ENODEV;
793 }
794
795 if (lseek(config_fd, pos, SEEK_SET) != pos) {
796 ret = -errno;
797 goto out;
798 }
799
800 do {
801 rc = read(config_fd, (uint8_t *)val, len);
802 } while (rc < 0 && (errno == EINTR || errno == EAGAIN));
803 if (rc != len) {
804 ret = -errno;
805 }
806
807 out:
808 close(config_fd);
809 return ret;
810 }
811
812 static int igd_pt_i440fx_initfn(struct PCIDevice *pci_dev)
813 {
814 uint32_t val = 0;
815 int rc, i, num;
816 int pos, len;
817
818 num = ARRAY_SIZE(igd_host_bridge_infos);
819 for (i = 0; i < num; i++) {
820 pos = igd_host_bridge_infos[i].offset;
821 len = igd_host_bridge_infos[i].len;
822 rc = host_pci_config_read(pos, len, &val);
823 if (rc) {
824 return -ENODEV;
825 }
826 pci_default_write_config(pci_dev, pos, val, len);
827 }
828
829 return 0;
830 }
831
832 static void igd_passthrough_i440fx_class_init(ObjectClass *klass, void *data)
833 {
834 DeviceClass *dc = DEVICE_CLASS(klass);
835 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
836
837 k->init = igd_pt_i440fx_initfn;
838 dc->desc = "IGD Passthrough Host bridge";
839 }
840
841 static const TypeInfo igd_passthrough_i440fx_info = {
842 .name = TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE,
843 .parent = TYPE_I440FX_PCI_DEVICE,
844 .instance_size = sizeof(PCII440FXState),
845 .class_init = igd_passthrough_i440fx_class_init,
846 };
847
848 static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge,
849 PCIBus *rootbus)
850 {
851 I440FXState *s = I440FX_PCI_HOST_BRIDGE(host_bridge);
852
853 /* For backwards compat with old device paths */
854 if (s->short_root_bus) {
855 return "0000";
856 }
857 return "0000:00";
858 }
859
860 static Property i440fx_props[] = {
861 DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState,
862 pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE),
863 DEFINE_PROP_UINT32("short_root_bus", I440FXState, short_root_bus, 0),
864 DEFINE_PROP_END_OF_LIST(),
865 };
866
867 static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
868 {
869 DeviceClass *dc = DEVICE_CLASS(klass);
870 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
871
872 hc->root_bus_path = i440fx_pcihost_root_bus_path;
873 dc->realize = i440fx_pcihost_realize;
874 dc->fw_name = "pci";
875 dc->props = i440fx_props;
876 /* Reason: needs to be wired up by pc_init1 */
877 dc->cannot_instantiate_with_device_add_yet = true;
878 }
879
880 static const TypeInfo i440fx_pcihost_info = {
881 .name = TYPE_I440FX_PCI_HOST_BRIDGE,
882 .parent = TYPE_PCI_HOST_BRIDGE,
883 .instance_size = sizeof(I440FXState),
884 .instance_init = i440fx_pcihost_initfn,
885 .class_init = i440fx_pcihost_class_init,
886 };
887
888 static void i440fx_register_types(void)
889 {
890 type_register_static(&i440fx_info);
891 type_register_static(&igd_passthrough_i440fx_info);
892 type_register_static(&piix3_pci_type_info);
893 type_register_static(&piix3_info);
894 type_register_static(&piix3_xen_info);
895 type_register_static(&i440fx_pcihost_info);
896 }
897
898 type_init(i440fx_register_types)