hw/arm/raspi: fix CPRMAN base address
[qemu.git] / hw / pci-host / prep.c
1 /*
2 * QEMU PREP PCI host
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 * Copyright (c) 2011-2013 Andreas Färber
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 #include "qemu/osdep.h"
27 #include "qemu-common.h"
28 #include "qemu/units.h"
29 #include "qapi/error.h"
30 #include "hw/pci/pci.h"
31 #include "hw/pci/pci_bus.h"
32 #include "hw/pci/pci_host.h"
33 #include "hw/qdev-properties.h"
34 #include "migration/vmstate.h"
35 #include "hw/intc/i8259.h"
36 #include "hw/irq.h"
37 #include "hw/loader.h"
38 #include "hw/or-irq.h"
39 #include "exec/address-spaces.h"
40 #include "elf.h"
41 #include "qom/object.h"
42
43 #define TYPE_RAVEN_PCI_DEVICE "raven"
44 #define TYPE_RAVEN_PCI_HOST_BRIDGE "raven-pcihost"
45
46 OBJECT_DECLARE_SIMPLE_TYPE(RavenPCIState, RAVEN_PCI_DEVICE)
47
48 struct RavenPCIState {
49 PCIDevice dev;
50
51 uint32_t elf_machine;
52 char *bios_name;
53 MemoryRegion bios;
54 };
55
56 typedef struct PRePPCIState PREPPCIState;
57 DECLARE_INSTANCE_CHECKER(PREPPCIState, RAVEN_PCI_HOST_BRIDGE,
58 TYPE_RAVEN_PCI_HOST_BRIDGE)
59
60 struct PRePPCIState {
61 PCIHostState parent_obj;
62
63 qemu_or_irq *or_irq;
64 qemu_irq pci_irqs[PCI_NUM_PINS];
65 PCIBus pci_bus;
66 AddressSpace pci_io_as;
67 MemoryRegion pci_io;
68 MemoryRegion pci_io_non_contiguous;
69 MemoryRegion pci_memory;
70 MemoryRegion pci_intack;
71 MemoryRegion bm;
72 MemoryRegion bm_ram_alias;
73 MemoryRegion bm_pci_memory_alias;
74 AddressSpace bm_as;
75 RavenPCIState pci_dev;
76
77 int contiguous_map;
78 bool is_legacy_prep;
79 };
80
81 #define BIOS_SIZE (1 * MiB)
82
83 static inline uint32_t raven_pci_io_config(hwaddr addr)
84 {
85 int i;
86
87 for (i = 0; i < 11; i++) {
88 if ((addr & (1 << (11 + i))) != 0) {
89 break;
90 }
91 }
92 return (addr & 0x7ff) | (i << 11);
93 }
94
95 static void raven_pci_io_write(void *opaque, hwaddr addr,
96 uint64_t val, unsigned int size)
97 {
98 PREPPCIState *s = opaque;
99 PCIHostState *phb = PCI_HOST_BRIDGE(s);
100 pci_data_write(phb->bus, raven_pci_io_config(addr), val, size);
101 }
102
103 static uint64_t raven_pci_io_read(void *opaque, hwaddr addr,
104 unsigned int size)
105 {
106 PREPPCIState *s = opaque;
107 PCIHostState *phb = PCI_HOST_BRIDGE(s);
108 return pci_data_read(phb->bus, raven_pci_io_config(addr), size);
109 }
110
111 static const MemoryRegionOps raven_pci_io_ops = {
112 .read = raven_pci_io_read,
113 .write = raven_pci_io_write,
114 .endianness = DEVICE_LITTLE_ENDIAN,
115 };
116
117 static uint64_t raven_intack_read(void *opaque, hwaddr addr,
118 unsigned int size)
119 {
120 return pic_read_irq(isa_pic);
121 }
122
123 static const MemoryRegionOps raven_intack_ops = {
124 .read = raven_intack_read,
125 .valid = {
126 .max_access_size = 1,
127 },
128 };
129
130 static inline hwaddr raven_io_address(PREPPCIState *s,
131 hwaddr addr)
132 {
133 if (s->contiguous_map == 0) {
134 /* 64 KB contiguous space for IOs */
135 addr &= 0xFFFF;
136 } else {
137 /* 8 MB non-contiguous space for IOs */
138 addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
139 }
140
141 /* FIXME: handle endianness switch */
142
143 return addr;
144 }
145
146 static uint64_t raven_io_read(void *opaque, hwaddr addr,
147 unsigned int size)
148 {
149 PREPPCIState *s = opaque;
150 uint8_t buf[4];
151
152 addr = raven_io_address(s, addr);
153 address_space_read(&s->pci_io_as, addr + 0x80000000,
154 MEMTXATTRS_UNSPECIFIED, buf, size);
155
156 if (size == 1) {
157 return buf[0];
158 } else if (size == 2) {
159 return lduw_le_p(buf);
160 } else if (size == 4) {
161 return ldl_le_p(buf);
162 } else {
163 g_assert_not_reached();
164 }
165 }
166
167 static void raven_io_write(void *opaque, hwaddr addr,
168 uint64_t val, unsigned int size)
169 {
170 PREPPCIState *s = opaque;
171 uint8_t buf[4];
172
173 addr = raven_io_address(s, addr);
174
175 if (size == 1) {
176 buf[0] = val;
177 } else if (size == 2) {
178 stw_le_p(buf, val);
179 } else if (size == 4) {
180 stl_le_p(buf, val);
181 } else {
182 g_assert_not_reached();
183 }
184
185 address_space_write(&s->pci_io_as, addr + 0x80000000,
186 MEMTXATTRS_UNSPECIFIED, buf, size);
187 }
188
189 static const MemoryRegionOps raven_io_ops = {
190 .read = raven_io_read,
191 .write = raven_io_write,
192 .endianness = DEVICE_LITTLE_ENDIAN,
193 .impl.max_access_size = 4,
194 .valid.unaligned = true,
195 };
196
197 static int raven_map_irq(PCIDevice *pci_dev, int irq_num)
198 {
199 return (irq_num + (pci_dev->devfn >> 3)) & 1;
200 }
201
202 static void raven_set_irq(void *opaque, int irq_num, int level)
203 {
204 PREPPCIState *s = opaque;
205
206 qemu_set_irq(s->pci_irqs[irq_num], level);
207 }
208
209 static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque,
210 int devfn)
211 {
212 PREPPCIState *s = opaque;
213
214 return &s->bm_as;
215 }
216
217 static void raven_change_gpio(void *opaque, int n, int level)
218 {
219 PREPPCIState *s = opaque;
220
221 s->contiguous_map = level;
222 }
223
224 static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
225 {
226 SysBusDevice *dev = SYS_BUS_DEVICE(d);
227 PCIHostState *h = PCI_HOST_BRIDGE(dev);
228 PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(dev);
229 MemoryRegion *address_space_mem = get_system_memory();
230 int i;
231
232 if (s->is_legacy_prep) {
233 for (i = 0; i < PCI_NUM_PINS; i++) {
234 sysbus_init_irq(dev, &s->pci_irqs[i]);
235 }
236 } else {
237 /* According to PReP specification section 6.1.6 "System Interrupt
238 * Assignments", all PCI interrupts are routed via IRQ 15 */
239 s->or_irq = OR_IRQ(object_new(TYPE_OR_IRQ));
240 object_property_set_int(OBJECT(s->or_irq), "num-lines", PCI_NUM_PINS,
241 &error_fatal);
242 qdev_realize(DEVICE(s->or_irq), NULL, &error_fatal);
243 sysbus_init_irq(dev, &s->or_irq->out_irq);
244
245 for (i = 0; i < PCI_NUM_PINS; i++) {
246 s->pci_irqs[i] = qdev_get_gpio_in(DEVICE(s->or_irq), i);
247 }
248 }
249
250 qdev_init_gpio_in(d, raven_change_gpio, 1);
251
252 pci_bus_irqs(&s->pci_bus, raven_set_irq, raven_map_irq, s, PCI_NUM_PINS);
253
254 memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, s,
255 "pci-conf-idx", 4);
256 memory_region_add_subregion(&s->pci_io, 0xcf8, &h->conf_mem);
257
258 memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, s,
259 "pci-conf-data", 4);
260 memory_region_add_subregion(&s->pci_io, 0xcfc, &h->data_mem);
261
262 memory_region_init_io(&h->mmcfg, OBJECT(s), &raven_pci_io_ops, s,
263 "pciio", 0x00400000);
264 memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg);
265
266 memory_region_init_io(&s->pci_intack, OBJECT(s), &raven_intack_ops, s,
267 "pci-intack", 1);
268 memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->pci_intack);
269
270 /* TODO Remove once realize propagates to child devices. */
271 qdev_realize(DEVICE(&s->pci_dev), BUS(&s->pci_bus), errp);
272 }
273
274 static void raven_pcihost_initfn(Object *obj)
275 {
276 PCIHostState *h = PCI_HOST_BRIDGE(obj);
277 PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(obj);
278 MemoryRegion *address_space_mem = get_system_memory();
279 DeviceState *pci_dev;
280
281 memory_region_init(&s->pci_io, obj, "pci-io", 0x3f800000);
282 memory_region_init_io(&s->pci_io_non_contiguous, obj, &raven_io_ops, s,
283 "pci-io-non-contiguous", 0x00800000);
284 memory_region_init(&s->pci_memory, obj, "pci-memory", 0x3f000000);
285 address_space_init(&s->pci_io_as, &s->pci_io, "raven-io");
286
287 /* CPU address space */
288 memory_region_add_subregion(address_space_mem, 0x80000000, &s->pci_io);
289 memory_region_add_subregion_overlap(address_space_mem, 0x80000000,
290 &s->pci_io_non_contiguous, 1);
291 memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory);
292 pci_root_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL,
293 &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS);
294
295 /* Bus master address space */
296 memory_region_init(&s->bm, obj, "bm-raven", 4 * GiB);
297 memory_region_init_alias(&s->bm_pci_memory_alias, obj, "bm-pci-memory",
298 &s->pci_memory, 0,
299 memory_region_size(&s->pci_memory));
300 memory_region_init_alias(&s->bm_ram_alias, obj, "bm-system",
301 get_system_memory(), 0, 0x80000000);
302 memory_region_add_subregion(&s->bm, 0 , &s->bm_pci_memory_alias);
303 memory_region_add_subregion(&s->bm, 0x80000000, &s->bm_ram_alias);
304 address_space_init(&s->bm_as, &s->bm, "raven-bm");
305 pci_setup_iommu(&s->pci_bus, raven_pcihost_set_iommu, s);
306
307 h->bus = &s->pci_bus;
308
309 object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_RAVEN_PCI_DEVICE);
310 pci_dev = DEVICE(&s->pci_dev);
311 object_property_set_int(OBJECT(&s->pci_dev), "addr", PCI_DEVFN(0, 0),
312 NULL);
313 qdev_prop_set_bit(pci_dev, "multifunction", false);
314 }
315
316 static void raven_realize(PCIDevice *d, Error **errp)
317 {
318 RavenPCIState *s = RAVEN_PCI_DEVICE(d);
319 char *filename;
320 int bios_size = -1;
321
322 d->config[0x0C] = 0x08; // cache_line_size
323 d->config[0x0D] = 0x10; // latency_timer
324 d->config[0x34] = 0x00; // capabilities_pointer
325
326 memory_region_init_rom_nomigrate(&s->bios, OBJECT(s), "bios", BIOS_SIZE,
327 &error_fatal);
328 memory_region_add_subregion(get_system_memory(), (uint32_t)(-BIOS_SIZE),
329 &s->bios);
330 if (s->bios_name) {
331 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, s->bios_name);
332 if (filename) {
333 if (s->elf_machine != EM_NONE) {
334 bios_size = load_elf(filename, NULL, NULL, NULL, NULL,
335 NULL, NULL, NULL, 1, s->elf_machine,
336 0, 0);
337 }
338 if (bios_size < 0) {
339 bios_size = get_image_size(filename);
340 if (bios_size > 0 && bios_size <= BIOS_SIZE) {
341 hwaddr bios_addr;
342 bios_size = (bios_size + 0xfff) & ~0xfff;
343 bios_addr = (uint32_t)(-BIOS_SIZE);
344 bios_size = load_image_targphys(filename, bios_addr,
345 bios_size);
346 }
347 }
348 }
349 g_free(filename);
350 if (bios_size < 0 || bios_size > BIOS_SIZE) {
351 memory_region_del_subregion(get_system_memory(), &s->bios);
352 error_setg(errp, "Could not load bios image '%s'", s->bios_name);
353 return;
354 }
355 }
356
357 vmstate_register_ram_global(&s->bios);
358 }
359
360 static const VMStateDescription vmstate_raven = {
361 .name = "raven",
362 .version_id = 0,
363 .minimum_version_id = 0,
364 .fields = (VMStateField[]) {
365 VMSTATE_PCI_DEVICE(dev, RavenPCIState),
366 VMSTATE_END_OF_LIST()
367 },
368 };
369
370 static void raven_class_init(ObjectClass *klass, void *data)
371 {
372 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
373 DeviceClass *dc = DEVICE_CLASS(klass);
374
375 k->realize = raven_realize;
376 k->vendor_id = PCI_VENDOR_ID_MOTOROLA;
377 k->device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN;
378 k->revision = 0x00;
379 k->class_id = PCI_CLASS_BRIDGE_HOST;
380 dc->desc = "PReP Host Bridge - Motorola Raven";
381 dc->vmsd = &vmstate_raven;
382 /*
383 * Reason: PCI-facing part of the host bridge, not usable without
384 * the host-facing part, which can't be device_add'ed, yet.
385 */
386 dc->user_creatable = false;
387 }
388
389 static const TypeInfo raven_info = {
390 .name = TYPE_RAVEN_PCI_DEVICE,
391 .parent = TYPE_PCI_DEVICE,
392 .instance_size = sizeof(RavenPCIState),
393 .class_init = raven_class_init,
394 .interfaces = (InterfaceInfo[]) {
395 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
396 { },
397 },
398 };
399
400 static Property raven_pcihost_properties[] = {
401 DEFINE_PROP_UINT32("elf-machine", PREPPCIState, pci_dev.elf_machine,
402 EM_NONE),
403 DEFINE_PROP_STRING("bios-name", PREPPCIState, pci_dev.bios_name),
404 /* Temporary workaround until legacy prep machine is removed */
405 DEFINE_PROP_BOOL("is-legacy-prep", PREPPCIState, is_legacy_prep,
406 false),
407 DEFINE_PROP_END_OF_LIST()
408 };
409
410 static void raven_pcihost_class_init(ObjectClass *klass, void *data)
411 {
412 DeviceClass *dc = DEVICE_CLASS(klass);
413
414 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
415 dc->realize = raven_pcihost_realizefn;
416 device_class_set_props(dc, raven_pcihost_properties);
417 dc->fw_name = "pci";
418 }
419
420 static const TypeInfo raven_pcihost_info = {
421 .name = TYPE_RAVEN_PCI_HOST_BRIDGE,
422 .parent = TYPE_PCI_HOST_BRIDGE,
423 .instance_size = sizeof(PREPPCIState),
424 .instance_init = raven_pcihost_initfn,
425 .class_init = raven_pcihost_class_init,
426 };
427
428 static void raven_register_types(void)
429 {
430 type_register_static(&raven_pcihost_info);
431 type_register_static(&raven_info);
432 }
433
434 type_init(raven_register_types)