raven: Fix PCI bus accesses with size > 1
[qemu.git] / hw / pci-host / prep.c
1 /*
2 * QEMU PREP PCI host
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 * Copyright (c) 2011-2013 Andreas Färber
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 #include "hw/hw.h"
27 #include "hw/pci/pci.h"
28 #include "hw/pci/pci_bus.h"
29 #include "hw/pci/pci_host.h"
30 #include "hw/i386/pc.h"
31 #include "hw/loader.h"
32 #include "exec/address-spaces.h"
33 #include "elf.h"
34
35 #define TYPE_RAVEN_PCI_DEVICE "raven"
36 #define TYPE_RAVEN_PCI_HOST_BRIDGE "raven-pcihost"
37
38 #define RAVEN_PCI_DEVICE(obj) \
39 OBJECT_CHECK(RavenPCIState, (obj), TYPE_RAVEN_PCI_DEVICE)
40
41 typedef struct RavenPCIState {
42 PCIDevice dev;
43
44 uint32_t elf_machine;
45 char *bios_name;
46 MemoryRegion bios;
47 } RavenPCIState;
48
49 #define RAVEN_PCI_HOST_BRIDGE(obj) \
50 OBJECT_CHECK(PREPPCIState, (obj), TYPE_RAVEN_PCI_HOST_BRIDGE)
51
52 typedef struct PRePPCIState {
53 PCIHostState parent_obj;
54
55 qemu_irq irq[PCI_NUM_PINS];
56 PCIBus pci_bus;
57 AddressSpace pci_io_as;
58 MemoryRegion pci_io;
59 MemoryRegion pci_io_non_contiguous;
60 MemoryRegion pci_memory;
61 MemoryRegion pci_intack;
62 MemoryRegion bm;
63 MemoryRegion bm_ram_alias;
64 MemoryRegion bm_pci_memory_alias;
65 AddressSpace bm_as;
66 RavenPCIState pci_dev;
67
68 int contiguous_map;
69 } PREPPCIState;
70
71 #define BIOS_SIZE (1024 * 1024)
72
73 static inline uint32_t PPC_PCIIO_config(hwaddr addr)
74 {
75 int i;
76
77 for (i = 0; i < 11; i++) {
78 if ((addr & (1 << (11 + i))) != 0) {
79 break;
80 }
81 }
82 return (addr & 0x7ff) | (i << 11);
83 }
84
85 static void ppc_pci_io_write(void *opaque, hwaddr addr,
86 uint64_t val, unsigned int size)
87 {
88 PREPPCIState *s = opaque;
89 PCIHostState *phb = PCI_HOST_BRIDGE(s);
90 pci_data_write(phb->bus, PPC_PCIIO_config(addr), val, size);
91 }
92
93 static uint64_t ppc_pci_io_read(void *opaque, hwaddr addr,
94 unsigned int size)
95 {
96 PREPPCIState *s = opaque;
97 PCIHostState *phb = PCI_HOST_BRIDGE(s);
98 return pci_data_read(phb->bus, PPC_PCIIO_config(addr), size);
99 }
100
101 static const MemoryRegionOps PPC_PCIIO_ops = {
102 .read = ppc_pci_io_read,
103 .write = ppc_pci_io_write,
104 .endianness = DEVICE_LITTLE_ENDIAN,
105 };
106
107 static uint64_t ppc_intack_read(void *opaque, hwaddr addr,
108 unsigned int size)
109 {
110 return pic_read_irq(isa_pic);
111 }
112
113 static const MemoryRegionOps PPC_intack_ops = {
114 .read = ppc_intack_read,
115 .valid = {
116 .max_access_size = 1,
117 },
118 };
119
120 static inline hwaddr raven_io_address(PREPPCIState *s,
121 hwaddr addr)
122 {
123 if (s->contiguous_map == 0) {
124 /* 64 KB contiguous space for IOs */
125 addr &= 0xFFFF;
126 } else {
127 /* 8 MB non-contiguous space for IOs */
128 addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
129 }
130
131 /* FIXME: handle endianness switch */
132
133 return addr;
134 }
135
136 static uint64_t raven_io_read(void *opaque, hwaddr addr,
137 unsigned int size)
138 {
139 PREPPCIState *s = opaque;
140 uint8_t buf[4];
141
142 addr = raven_io_address(s, addr);
143 address_space_read(&s->pci_io_as, addr + 0x80000000, buf, size);
144
145 if (size == 1) {
146 return buf[0];
147 } else if (size == 2) {
148 return lduw_p(buf);
149 } else if (size == 4) {
150 return ldl_p(buf);
151 } else {
152 g_assert_not_reached();
153 }
154 }
155
156 static void raven_io_write(void *opaque, hwaddr addr,
157 uint64_t val, unsigned int size)
158 {
159 PREPPCIState *s = opaque;
160 uint8_t buf[4];
161
162 addr = raven_io_address(s, addr);
163
164 if (size == 1) {
165 buf[0] = val;
166 } else if (size == 2) {
167 stw_p(buf, val);
168 } else if (size == 4) {
169 stl_p(buf, val);
170 } else {
171 g_assert_not_reached();
172 }
173
174 address_space_write(&s->pci_io_as, addr + 0x80000000, buf, size);
175 }
176
177 static const MemoryRegionOps raven_io_ops = {
178 .read = raven_io_read,
179 .write = raven_io_write,
180 .endianness = DEVICE_LITTLE_ENDIAN,
181 .impl.max_access_size = 4,
182 .valid.unaligned = true,
183 };
184
185 static int prep_map_irq(PCIDevice *pci_dev, int irq_num)
186 {
187 return (irq_num + (pci_dev->devfn >> 3)) & 1;
188 }
189
190 static void prep_set_irq(void *opaque, int irq_num, int level)
191 {
192 qemu_irq *pic = opaque;
193
194 qemu_set_irq(pic[irq_num] , level);
195 }
196
197 static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque,
198 int devfn)
199 {
200 PREPPCIState *s = opaque;
201
202 return &s->bm_as;
203 }
204
205 static void raven_change_gpio(void *opaque, int n, int level)
206 {
207 PREPPCIState *s = opaque;
208
209 s->contiguous_map = level;
210 }
211
212 static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
213 {
214 SysBusDevice *dev = SYS_BUS_DEVICE(d);
215 PCIHostState *h = PCI_HOST_BRIDGE(dev);
216 PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(dev);
217 MemoryRegion *address_space_mem = get_system_memory();
218 int i;
219
220 for (i = 0; i < PCI_NUM_PINS; i++) {
221 sysbus_init_irq(dev, &s->irq[i]);
222 }
223
224 qdev_init_gpio_in(d, raven_change_gpio, 1);
225
226 pci_bus_irqs(&s->pci_bus, prep_set_irq, prep_map_irq, s->irq, PCI_NUM_PINS);
227
228 memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, s,
229 "pci-conf-idx", 4);
230 memory_region_add_subregion(&s->pci_io, 0xcf8, &h->conf_mem);
231
232 memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, s,
233 "pci-conf-data", 4);
234 memory_region_add_subregion(&s->pci_io, 0xcfc, &h->data_mem);
235
236 memory_region_init_io(&h->mmcfg, OBJECT(s), &PPC_PCIIO_ops, s, "pciio", 0x00400000);
237 memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg);
238
239 memory_region_init_io(&s->pci_intack, OBJECT(s), &PPC_intack_ops, s,
240 "pci-intack", 1);
241 memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->pci_intack);
242
243 /* TODO Remove once realize propagates to child devices. */
244 object_property_set_bool(OBJECT(&s->pci_dev), true, "realized", errp);
245 }
246
247 static void raven_pcihost_initfn(Object *obj)
248 {
249 PCIHostState *h = PCI_HOST_BRIDGE(obj);
250 PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(obj);
251 MemoryRegion *address_space_mem = get_system_memory();
252 DeviceState *pci_dev;
253
254 memory_region_init(&s->pci_io, obj, "pci-io", 0x3f800000);
255 memory_region_init_io(&s->pci_io_non_contiguous, obj, &raven_io_ops, s,
256 "pci-io-non-contiguous", 0x00800000);
257 /* Open Hack'Ware hack: real size should be only 0x3f000000 bytes */
258 memory_region_init(&s->pci_memory, obj, "pci-memory",
259 0x3f000000 + 0xc0000000ULL);
260 address_space_init(&s->pci_io_as, &s->pci_io, "raven-io");
261
262 /* CPU address space */
263 memory_region_add_subregion(address_space_mem, 0x80000000, &s->pci_io);
264 memory_region_add_subregion_overlap(address_space_mem, 0x80000000,
265 &s->pci_io_non_contiguous, 1);
266 memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory);
267 pci_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL,
268 &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS);
269
270 /* Bus master address space */
271 memory_region_init(&s->bm, obj, "bm-raven", UINT32_MAX);
272 memory_region_init_alias(&s->bm_pci_memory_alias, obj, "bm-pci-memory",
273 &s->pci_memory, 0,
274 memory_region_size(&s->pci_memory));
275 memory_region_init_alias(&s->bm_ram_alias, obj, "bm-system",
276 get_system_memory(), 0, 0x80000000);
277 memory_region_add_subregion(&s->bm, 0 , &s->bm_pci_memory_alias);
278 memory_region_add_subregion(&s->bm, 0x80000000, &s->bm_ram_alias);
279 address_space_init(&s->bm_as, &s->bm, "raven-bm");
280 pci_setup_iommu(&s->pci_bus, raven_pcihost_set_iommu, s);
281
282 h->bus = &s->pci_bus;
283
284 object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_RAVEN_PCI_DEVICE);
285 pci_dev = DEVICE(&s->pci_dev);
286 qdev_set_parent_bus(pci_dev, BUS(&s->pci_bus));
287 object_property_set_int(OBJECT(&s->pci_dev), PCI_DEVFN(0, 0), "addr",
288 NULL);
289 qdev_prop_set_bit(pci_dev, "multifunction", false);
290 }
291
292 static int raven_init(PCIDevice *d)
293 {
294 RavenPCIState *s = RAVEN_PCI_DEVICE(d);
295 char *filename;
296 int bios_size = -1;
297
298 d->config[0x0C] = 0x08; // cache_line_size
299 d->config[0x0D] = 0x10; // latency_timer
300 d->config[0x34] = 0x00; // capabilities_pointer
301
302 memory_region_init_ram(&s->bios, OBJECT(s), "bios", BIOS_SIZE);
303 memory_region_set_readonly(&s->bios, true);
304 memory_region_add_subregion(get_system_memory(), (uint32_t)(-BIOS_SIZE),
305 &s->bios);
306 vmstate_register_ram_global(&s->bios);
307 if (s->bios_name) {
308 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, s->bios_name);
309 if (filename) {
310 if (s->elf_machine != EM_NONE) {
311 bios_size = load_elf(filename, NULL, NULL, NULL,
312 NULL, NULL, 1, s->elf_machine, 0);
313 }
314 if (bios_size < 0) {
315 bios_size = get_image_size(filename);
316 if (bios_size > 0 && bios_size <= BIOS_SIZE) {
317 hwaddr bios_addr;
318 bios_size = (bios_size + 0xfff) & ~0xfff;
319 bios_addr = (uint32_t)(-BIOS_SIZE);
320 bios_size = load_image_targphys(filename, bios_addr,
321 bios_size);
322 }
323 }
324 }
325 if (bios_size < 0 || bios_size > BIOS_SIZE) {
326 hw_error("qemu: could not load bios image '%s'\n", s->bios_name);
327 }
328 if (filename) {
329 g_free(filename);
330 }
331 }
332
333 return 0;
334 }
335
336 static const VMStateDescription vmstate_raven = {
337 .name = "raven",
338 .version_id = 0,
339 .minimum_version_id = 0,
340 .fields = (VMStateField[]) {
341 VMSTATE_PCI_DEVICE(dev, RavenPCIState),
342 VMSTATE_END_OF_LIST()
343 },
344 };
345
346 static void raven_class_init(ObjectClass *klass, void *data)
347 {
348 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
349 DeviceClass *dc = DEVICE_CLASS(klass);
350
351 k->init = raven_init;
352 k->vendor_id = PCI_VENDOR_ID_MOTOROLA;
353 k->device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN;
354 k->revision = 0x00;
355 k->class_id = PCI_CLASS_BRIDGE_HOST;
356 dc->desc = "PReP Host Bridge - Motorola Raven";
357 dc->vmsd = &vmstate_raven;
358 /*
359 * PCI-facing part of the host bridge, not usable without the
360 * host-facing part, which can't be device_add'ed, yet.
361 */
362 dc->cannot_instantiate_with_device_add_yet = true;
363 }
364
365 static const TypeInfo raven_info = {
366 .name = TYPE_RAVEN_PCI_DEVICE,
367 .parent = TYPE_PCI_DEVICE,
368 .instance_size = sizeof(RavenPCIState),
369 .class_init = raven_class_init,
370 };
371
372 static Property raven_pcihost_properties[] = {
373 DEFINE_PROP_UINT32("elf-machine", PREPPCIState, pci_dev.elf_machine,
374 EM_NONE),
375 DEFINE_PROP_STRING("bios-name", PREPPCIState, pci_dev.bios_name),
376 DEFINE_PROP_END_OF_LIST()
377 };
378
379 static void raven_pcihost_class_init(ObjectClass *klass, void *data)
380 {
381 DeviceClass *dc = DEVICE_CLASS(klass);
382
383 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
384 dc->realize = raven_pcihost_realizefn;
385 dc->props = raven_pcihost_properties;
386 dc->fw_name = "pci";
387 }
388
389 static const TypeInfo raven_pcihost_info = {
390 .name = TYPE_RAVEN_PCI_HOST_BRIDGE,
391 .parent = TYPE_PCI_HOST_BRIDGE,
392 .instance_size = sizeof(PREPPCIState),
393 .instance_init = raven_pcihost_initfn,
394 .class_init = raven_pcihost_class_init,
395 };
396
397 static void raven_register_types(void)
398 {
399 type_register_static(&raven_pcihost_info);
400 type_register_static(&raven_info);
401 }
402
403 type_init(raven_register_types)