Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into staging
[qemu.git] / hw / pci-host / raven.c
1 /*
2 * QEMU PREP PCI host
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 * Copyright (c) 2011-2013 Andreas Färber
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 #include "qemu/osdep.h"
27 #include "qemu-common.h"
28 #include "qemu/datadir.h"
29 #include "qemu/units.h"
30 #include "qemu/log.h"
31 #include "qapi/error.h"
32 #include "hw/pci/pci.h"
33 #include "hw/pci/pci_bus.h"
34 #include "hw/pci/pci_host.h"
35 #include "hw/qdev-properties.h"
36 #include "migration/vmstate.h"
37 #include "hw/intc/i8259.h"
38 #include "hw/irq.h"
39 #include "hw/loader.h"
40 #include "hw/or-irq.h"
41 #include "elf.h"
42 #include "qom/object.h"
43
44 #define TYPE_RAVEN_PCI_DEVICE "raven"
45 #define TYPE_RAVEN_PCI_HOST_BRIDGE "raven-pcihost"
46
47 OBJECT_DECLARE_SIMPLE_TYPE(RavenPCIState, RAVEN_PCI_DEVICE)
48
49 struct RavenPCIState {
50 PCIDevice dev;
51
52 uint32_t elf_machine;
53 char *bios_name;
54 MemoryRegion bios;
55 };
56
57 typedef struct PRePPCIState PREPPCIState;
58 DECLARE_INSTANCE_CHECKER(PREPPCIState, RAVEN_PCI_HOST_BRIDGE,
59 TYPE_RAVEN_PCI_HOST_BRIDGE)
60
61 struct PRePPCIState {
62 PCIHostState parent_obj;
63
64 qemu_or_irq *or_irq;
65 qemu_irq pci_irqs[PCI_NUM_PINS];
66 PCIBus pci_bus;
67 AddressSpace pci_io_as;
68 MemoryRegion pci_io;
69 MemoryRegion pci_io_non_contiguous;
70 MemoryRegion pci_memory;
71 MemoryRegion pci_intack;
72 MemoryRegion bm;
73 MemoryRegion bm_ram_alias;
74 MemoryRegion bm_pci_memory_alias;
75 AddressSpace bm_as;
76 RavenPCIState pci_dev;
77
78 int contiguous_map;
79 bool is_legacy_prep;
80 };
81
82 #define BIOS_SIZE (1 * MiB)
83
84 #define PCI_IO_BASE_ADDR 0x80000000 /* Physical address on main bus */
85
86 static inline uint32_t raven_pci_io_config(hwaddr addr)
87 {
88 int i;
89
90 for (i = 0; i < 11; i++) {
91 if ((addr & (1 << (11 + i))) != 0) {
92 break;
93 }
94 }
95 return (addr & 0x7ff) | (i << 11);
96 }
97
98 static void raven_pci_io_write(void *opaque, hwaddr addr,
99 uint64_t val, unsigned int size)
100 {
101 PREPPCIState *s = opaque;
102 PCIHostState *phb = PCI_HOST_BRIDGE(s);
103 pci_data_write(phb->bus, raven_pci_io_config(addr), val, size);
104 }
105
106 static uint64_t raven_pci_io_read(void *opaque, hwaddr addr,
107 unsigned int size)
108 {
109 PREPPCIState *s = opaque;
110 PCIHostState *phb = PCI_HOST_BRIDGE(s);
111 return pci_data_read(phb->bus, raven_pci_io_config(addr), size);
112 }
113
114 static const MemoryRegionOps raven_pci_io_ops = {
115 .read = raven_pci_io_read,
116 .write = raven_pci_io_write,
117 .endianness = DEVICE_LITTLE_ENDIAN,
118 };
119
120 static uint64_t raven_intack_read(void *opaque, hwaddr addr,
121 unsigned int size)
122 {
123 return pic_read_irq(isa_pic);
124 }
125
126 static void raven_intack_write(void *opaque, hwaddr addr,
127 uint64_t data, unsigned size)
128 {
129 qemu_log_mask(LOG_UNIMP, "%s not implemented\n", __func__);
130 }
131
132 static const MemoryRegionOps raven_intack_ops = {
133 .read = raven_intack_read,
134 .write = raven_intack_write,
135 .valid = {
136 .max_access_size = 1,
137 },
138 };
139
140 static inline hwaddr raven_io_address(PREPPCIState *s,
141 hwaddr addr)
142 {
143 if (s->contiguous_map == 0) {
144 /* 64 KB contiguous space for IOs */
145 addr &= 0xFFFF;
146 } else {
147 /* 8 MB non-contiguous space for IOs */
148 addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
149 }
150
151 /* FIXME: handle endianness switch */
152
153 return addr;
154 }
155
156 static uint64_t raven_io_read(void *opaque, hwaddr addr,
157 unsigned int size)
158 {
159 PREPPCIState *s = opaque;
160 uint8_t buf[4];
161
162 addr = raven_io_address(s, addr);
163 address_space_read(&s->pci_io_as, addr + PCI_IO_BASE_ADDR,
164 MEMTXATTRS_UNSPECIFIED, buf, size);
165
166 if (size == 1) {
167 return buf[0];
168 } else if (size == 2) {
169 return lduw_le_p(buf);
170 } else if (size == 4) {
171 return ldl_le_p(buf);
172 } else {
173 g_assert_not_reached();
174 }
175 }
176
177 static void raven_io_write(void *opaque, hwaddr addr,
178 uint64_t val, unsigned int size)
179 {
180 PREPPCIState *s = opaque;
181 uint8_t buf[4];
182
183 addr = raven_io_address(s, addr);
184
185 if (size == 1) {
186 buf[0] = val;
187 } else if (size == 2) {
188 stw_le_p(buf, val);
189 } else if (size == 4) {
190 stl_le_p(buf, val);
191 } else {
192 g_assert_not_reached();
193 }
194
195 address_space_write(&s->pci_io_as, addr + PCI_IO_BASE_ADDR,
196 MEMTXATTRS_UNSPECIFIED, buf, size);
197 }
198
199 static const MemoryRegionOps raven_io_ops = {
200 .read = raven_io_read,
201 .write = raven_io_write,
202 .endianness = DEVICE_LITTLE_ENDIAN,
203 .impl.max_access_size = 4,
204 .valid.unaligned = true,
205 };
206
207 static int raven_map_irq(PCIDevice *pci_dev, int irq_num)
208 {
209 return (irq_num + (pci_dev->devfn >> 3)) & 1;
210 }
211
212 static void raven_set_irq(void *opaque, int irq_num, int level)
213 {
214 PREPPCIState *s = opaque;
215
216 qemu_set_irq(s->pci_irqs[irq_num], level);
217 }
218
219 static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque,
220 int devfn)
221 {
222 PREPPCIState *s = opaque;
223
224 return &s->bm_as;
225 }
226
227 static void raven_change_gpio(void *opaque, int n, int level)
228 {
229 PREPPCIState *s = opaque;
230
231 s->contiguous_map = level;
232 }
233
234 static void raven_pcihost_realizefn(DeviceState *d, Error **errp)
235 {
236 SysBusDevice *dev = SYS_BUS_DEVICE(d);
237 PCIHostState *h = PCI_HOST_BRIDGE(dev);
238 PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(dev);
239 MemoryRegion *address_space_mem = get_system_memory();
240 int i;
241
242 if (s->is_legacy_prep) {
243 for (i = 0; i < PCI_NUM_PINS; i++) {
244 sysbus_init_irq(dev, &s->pci_irqs[i]);
245 }
246 } else {
247 /* According to PReP specification section 6.1.6 "System Interrupt
248 * Assignments", all PCI interrupts are routed via IRQ 15 */
249 s->or_irq = OR_IRQ(object_new(TYPE_OR_IRQ));
250 object_property_set_int(OBJECT(s->or_irq), "num-lines", PCI_NUM_PINS,
251 &error_fatal);
252 qdev_realize(DEVICE(s->or_irq), NULL, &error_fatal);
253 sysbus_init_irq(dev, &s->or_irq->out_irq);
254
255 for (i = 0; i < PCI_NUM_PINS; i++) {
256 s->pci_irqs[i] = qdev_get_gpio_in(DEVICE(s->or_irq), i);
257 }
258 }
259
260 qdev_init_gpio_in(d, raven_change_gpio, 1);
261
262 pci_bus_irqs(&s->pci_bus, raven_set_irq, raven_map_irq, s, PCI_NUM_PINS);
263
264 memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, s,
265 "pci-conf-idx", 4);
266 memory_region_add_subregion(&s->pci_io, 0xcf8, &h->conf_mem);
267
268 memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, s,
269 "pci-conf-data", 4);
270 memory_region_add_subregion(&s->pci_io, 0xcfc, &h->data_mem);
271
272 memory_region_init_io(&h->mmcfg, OBJECT(s), &raven_pci_io_ops, s,
273 "pciio", 0x00400000);
274 memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg);
275
276 memory_region_init_io(&s->pci_intack, OBJECT(s), &raven_intack_ops, s,
277 "pci-intack", 1);
278 memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->pci_intack);
279
280 /* TODO Remove once realize propagates to child devices. */
281 qdev_realize(DEVICE(&s->pci_dev), BUS(&s->pci_bus), errp);
282 }
283
284 static void raven_pcihost_initfn(Object *obj)
285 {
286 PCIHostState *h = PCI_HOST_BRIDGE(obj);
287 PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(obj);
288 MemoryRegion *address_space_mem = get_system_memory();
289 DeviceState *pci_dev;
290
291 memory_region_init(&s->pci_io, obj, "pci-io", 0x3f800000);
292 memory_region_init_io(&s->pci_io_non_contiguous, obj, &raven_io_ops, s,
293 "pci-io-non-contiguous", 0x00800000);
294 memory_region_init(&s->pci_memory, obj, "pci-memory", 0x3f000000);
295 address_space_init(&s->pci_io_as, &s->pci_io, "raven-io");
296
297 /* CPU address space */
298 memory_region_add_subregion(address_space_mem, PCI_IO_BASE_ADDR,
299 &s->pci_io);
300 memory_region_add_subregion_overlap(address_space_mem, PCI_IO_BASE_ADDR,
301 &s->pci_io_non_contiguous, 1);
302 memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory);
303 pci_root_bus_init(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL,
304 &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS);
305
306 /* Bus master address space */
307 memory_region_init(&s->bm, obj, "bm-raven", 4 * GiB);
308 memory_region_init_alias(&s->bm_pci_memory_alias, obj, "bm-pci-memory",
309 &s->pci_memory, 0,
310 memory_region_size(&s->pci_memory));
311 memory_region_init_alias(&s->bm_ram_alias, obj, "bm-system",
312 get_system_memory(), 0, 0x80000000);
313 memory_region_add_subregion(&s->bm, 0 , &s->bm_pci_memory_alias);
314 memory_region_add_subregion(&s->bm, 0x80000000, &s->bm_ram_alias);
315 address_space_init(&s->bm_as, &s->bm, "raven-bm");
316 pci_setup_iommu(&s->pci_bus, raven_pcihost_set_iommu, s);
317
318 h->bus = &s->pci_bus;
319
320 object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_RAVEN_PCI_DEVICE);
321 pci_dev = DEVICE(&s->pci_dev);
322 object_property_set_int(OBJECT(&s->pci_dev), "addr", PCI_DEVFN(0, 0),
323 NULL);
324 qdev_prop_set_bit(pci_dev, "multifunction", false);
325 }
326
327 static void raven_realize(PCIDevice *d, Error **errp)
328 {
329 RavenPCIState *s = RAVEN_PCI_DEVICE(d);
330 char *filename;
331 int bios_size = -1;
332
333 d->config[0x0C] = 0x08; // cache_line_size
334 d->config[0x0D] = 0x10; // latency_timer
335 d->config[0x34] = 0x00; // capabilities_pointer
336
337 memory_region_init_rom_nomigrate(&s->bios, OBJECT(s), "bios", BIOS_SIZE,
338 &error_fatal);
339 memory_region_add_subregion(get_system_memory(), (uint32_t)(-BIOS_SIZE),
340 &s->bios);
341 if (s->bios_name) {
342 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, s->bios_name);
343 if (filename) {
344 if (s->elf_machine != EM_NONE) {
345 bios_size = load_elf(filename, NULL, NULL, NULL, NULL,
346 NULL, NULL, NULL, 1, s->elf_machine,
347 0, 0);
348 }
349 if (bios_size < 0) {
350 bios_size = get_image_size(filename);
351 if (bios_size > 0 && bios_size <= BIOS_SIZE) {
352 hwaddr bios_addr;
353 bios_size = (bios_size + 0xfff) & ~0xfff;
354 bios_addr = (uint32_t)(-BIOS_SIZE);
355 bios_size = load_image_targphys(filename, bios_addr,
356 bios_size);
357 }
358 }
359 }
360 g_free(filename);
361 if (bios_size < 0 || bios_size > BIOS_SIZE) {
362 memory_region_del_subregion(get_system_memory(), &s->bios);
363 error_setg(errp, "Could not load bios image '%s'", s->bios_name);
364 return;
365 }
366 }
367
368 vmstate_register_ram_global(&s->bios);
369 }
370
371 static const VMStateDescription vmstate_raven = {
372 .name = "raven",
373 .version_id = 0,
374 .minimum_version_id = 0,
375 .fields = (VMStateField[]) {
376 VMSTATE_PCI_DEVICE(dev, RavenPCIState),
377 VMSTATE_END_OF_LIST()
378 },
379 };
380
381 static void raven_class_init(ObjectClass *klass, void *data)
382 {
383 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
384 DeviceClass *dc = DEVICE_CLASS(klass);
385
386 k->realize = raven_realize;
387 k->vendor_id = PCI_VENDOR_ID_MOTOROLA;
388 k->device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN;
389 k->revision = 0x00;
390 k->class_id = PCI_CLASS_BRIDGE_HOST;
391 dc->desc = "PReP Host Bridge - Motorola Raven";
392 dc->vmsd = &vmstate_raven;
393 /*
394 * Reason: PCI-facing part of the host bridge, not usable without
395 * the host-facing part, which can't be device_add'ed, yet.
396 */
397 dc->user_creatable = false;
398 }
399
400 static const TypeInfo raven_info = {
401 .name = TYPE_RAVEN_PCI_DEVICE,
402 .parent = TYPE_PCI_DEVICE,
403 .instance_size = sizeof(RavenPCIState),
404 .class_init = raven_class_init,
405 .interfaces = (InterfaceInfo[]) {
406 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
407 { },
408 },
409 };
410
411 static Property raven_pcihost_properties[] = {
412 DEFINE_PROP_UINT32("elf-machine", PREPPCIState, pci_dev.elf_machine,
413 EM_NONE),
414 DEFINE_PROP_STRING("bios-name", PREPPCIState, pci_dev.bios_name),
415 /* Temporary workaround until legacy prep machine is removed */
416 DEFINE_PROP_BOOL("is-legacy-prep", PREPPCIState, is_legacy_prep,
417 false),
418 DEFINE_PROP_END_OF_LIST()
419 };
420
421 static void raven_pcihost_class_init(ObjectClass *klass, void *data)
422 {
423 DeviceClass *dc = DEVICE_CLASS(klass);
424
425 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
426 dc->realize = raven_pcihost_realizefn;
427 device_class_set_props(dc, raven_pcihost_properties);
428 dc->fw_name = "pci";
429 }
430
431 static const TypeInfo raven_pcihost_info = {
432 .name = TYPE_RAVEN_PCI_HOST_BRIDGE,
433 .parent = TYPE_PCI_HOST_BRIDGE,
434 .instance_size = sizeof(PREPPCIState),
435 .instance_init = raven_pcihost_initfn,
436 .class_init = raven_pcihost_class_init,
437 };
438
439 static void raven_register_types(void)
440 {
441 type_register_static(&raven_pcihost_info);
442 type_register_static(&raven_info);
443 }
444
445 type_init(raven_register_types)