Merge remote-tracking branch 'stefanha/trivial-patches' into staging
[qemu.git] / hw / pci.c
1 /*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "pci.h"
26 #include "pci_bridge.h"
27 #include "pci_internals.h"
28 #include "monitor.h"
29 #include "net.h"
30 #include "sysemu.h"
31 #include "loader.h"
32 #include "qemu-objects.h"
33 #include "range.h"
34
35 //#define DEBUG_PCI
36 #ifdef DEBUG_PCI
37 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
38 #else
39 # define PCI_DPRINTF(format, ...) do { } while (0)
40 #endif
41
42 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
43 static char *pcibus_get_dev_path(DeviceState *dev);
44 static char *pcibus_get_fw_dev_path(DeviceState *dev);
45 static int pcibus_reset(BusState *qbus);
46
47 struct BusInfo pci_bus_info = {
48 .name = "PCI",
49 .size = sizeof(PCIBus),
50 .print_dev = pcibus_dev_print,
51 .get_dev_path = pcibus_get_dev_path,
52 .get_fw_dev_path = pcibus_get_fw_dev_path,
53 .reset = pcibus_reset,
54 .props = (Property[]) {
55 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
56 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
57 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
58 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
59 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
60 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
61 QEMU_PCI_CAP_SERR_BITNR, true),
62 DEFINE_PROP_END_OF_LIST()
63 }
64 };
65
66 static void pci_update_mappings(PCIDevice *d);
67 static void pci_set_irq(void *opaque, int irq_num, int level);
68 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom);
69 static void pci_del_option_rom(PCIDevice *pdev);
70
71 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
72 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
73
74 struct PCIHostBus {
75 int domain;
76 struct PCIBus *bus;
77 QLIST_ENTRY(PCIHostBus) next;
78 };
79 static QLIST_HEAD(, PCIHostBus) host_buses;
80
81 static const VMStateDescription vmstate_pcibus = {
82 .name = "PCIBUS",
83 .version_id = 1,
84 .minimum_version_id = 1,
85 .minimum_version_id_old = 1,
86 .fields = (VMStateField []) {
87 VMSTATE_INT32_EQUAL(nirq, PCIBus),
88 VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
89 VMSTATE_END_OF_LIST()
90 }
91 };
92
93 static int pci_bar(PCIDevice *d, int reg)
94 {
95 uint8_t type;
96
97 if (reg != PCI_ROM_SLOT)
98 return PCI_BASE_ADDRESS_0 + reg * 4;
99
100 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
101 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
102 }
103
104 static inline int pci_irq_state(PCIDevice *d, int irq_num)
105 {
106 return (d->irq_state >> irq_num) & 0x1;
107 }
108
109 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
110 {
111 d->irq_state &= ~(0x1 << irq_num);
112 d->irq_state |= level << irq_num;
113 }
114
115 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
116 {
117 PCIBus *bus;
118 for (;;) {
119 bus = pci_dev->bus;
120 irq_num = bus->map_irq(pci_dev, irq_num);
121 if (bus->set_irq)
122 break;
123 pci_dev = bus->parent_dev;
124 }
125 bus->irq_count[irq_num] += change;
126 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
127 }
128
129 int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
130 {
131 assert(irq_num >= 0);
132 assert(irq_num < bus->nirq);
133 return !!bus->irq_count[irq_num];
134 }
135
136 /* Update interrupt status bit in config space on interrupt
137 * state change. */
138 static void pci_update_irq_status(PCIDevice *dev)
139 {
140 if (dev->irq_state) {
141 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
142 } else {
143 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
144 }
145 }
146
147 void pci_device_deassert_intx(PCIDevice *dev)
148 {
149 int i;
150 for (i = 0; i < PCI_NUM_PINS; ++i) {
151 qemu_set_irq(dev->irq[i], 0);
152 }
153 }
154
155 /*
156 * This function is called on #RST and FLR.
157 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
158 */
159 void pci_device_reset(PCIDevice *dev)
160 {
161 int r;
162 /* TODO: call the below unconditionally once all pci devices
163 * are qdevified */
164 if (dev->qdev.info) {
165 qdev_reset_all(&dev->qdev);
166 }
167
168 dev->irq_state = 0;
169 pci_update_irq_status(dev);
170 pci_device_deassert_intx(dev);
171 /* Clear all writable bits */
172 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
173 pci_get_word(dev->wmask + PCI_COMMAND) |
174 pci_get_word(dev->w1cmask + PCI_COMMAND));
175 pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
176 pci_get_word(dev->wmask + PCI_STATUS) |
177 pci_get_word(dev->w1cmask + PCI_STATUS));
178 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
179 dev->config[PCI_INTERRUPT_LINE] = 0x0;
180 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
181 PCIIORegion *region = &dev->io_regions[r];
182 if (!region->size) {
183 continue;
184 }
185
186 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
187 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
188 pci_set_quad(dev->config + pci_bar(dev, r), region->type);
189 } else {
190 pci_set_long(dev->config + pci_bar(dev, r), region->type);
191 }
192 }
193 pci_update_mappings(dev);
194 }
195
196 /*
197 * Trigger pci bus reset under a given bus.
198 * To be called on RST# assert.
199 */
200 void pci_bus_reset(PCIBus *bus)
201 {
202 int i;
203
204 for (i = 0; i < bus->nirq; i++) {
205 bus->irq_count[i] = 0;
206 }
207 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
208 if (bus->devices[i]) {
209 pci_device_reset(bus->devices[i]);
210 }
211 }
212 }
213
214 static int pcibus_reset(BusState *qbus)
215 {
216 pci_bus_reset(DO_UPCAST(PCIBus, qbus, qbus));
217
218 /* topology traverse is done by pci_bus_reset().
219 Tell qbus/qdev walker not to traverse the tree */
220 return 1;
221 }
222
223 static void pci_host_bus_register(int domain, PCIBus *bus)
224 {
225 struct PCIHostBus *host;
226 host = qemu_mallocz(sizeof(*host));
227 host->domain = domain;
228 host->bus = bus;
229 QLIST_INSERT_HEAD(&host_buses, host, next);
230 }
231
232 PCIBus *pci_find_root_bus(int domain)
233 {
234 struct PCIHostBus *host;
235
236 QLIST_FOREACH(host, &host_buses, next) {
237 if (host->domain == domain) {
238 return host->bus;
239 }
240 }
241
242 return NULL;
243 }
244
245 int pci_find_domain(const PCIBus *bus)
246 {
247 PCIDevice *d;
248 struct PCIHostBus *host;
249
250 /* obtain root bus */
251 while ((d = bus->parent_dev) != NULL) {
252 bus = d->bus;
253 }
254
255 QLIST_FOREACH(host, &host_buses, next) {
256 if (host->bus == bus) {
257 return host->domain;
258 }
259 }
260
261 abort(); /* should not be reached */
262 return -1;
263 }
264
265 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
266 const char *name, uint8_t devfn_min)
267 {
268 qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
269 assert(PCI_FUNC(devfn_min) == 0);
270 bus->devfn_min = devfn_min;
271
272 /* host bridge */
273 QLIST_INIT(&bus->child);
274 pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
275
276 vmstate_register(NULL, -1, &vmstate_pcibus, bus);
277 }
278
279 PCIBus *pci_bus_new(DeviceState *parent, const char *name, uint8_t devfn_min)
280 {
281 PCIBus *bus;
282
283 bus = qemu_mallocz(sizeof(*bus));
284 bus->qbus.qdev_allocated = 1;
285 pci_bus_new_inplace(bus, parent, name, devfn_min);
286 return bus;
287 }
288
289 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
290 void *irq_opaque, int nirq)
291 {
292 bus->set_irq = set_irq;
293 bus->map_irq = map_irq;
294 bus->irq_opaque = irq_opaque;
295 bus->nirq = nirq;
296 bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
297 }
298
299 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
300 {
301 bus->qbus.allow_hotplug = 1;
302 bus->hotplug = hotplug;
303 bus->hotplug_qdev = qdev;
304 }
305
306 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base)
307 {
308 bus->mem_base = base;
309 }
310
311 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
312 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
313 void *irq_opaque, uint8_t devfn_min, int nirq)
314 {
315 PCIBus *bus;
316
317 bus = pci_bus_new(parent, name, devfn_min);
318 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
319 return bus;
320 }
321
322 int pci_bus_num(PCIBus *s)
323 {
324 if (!s->parent_dev)
325 return 0; /* pci host bridge */
326 return s->parent_dev->config[PCI_SECONDARY_BUS];
327 }
328
329 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
330 {
331 PCIDevice *s = container_of(pv, PCIDevice, config);
332 uint8_t *config;
333 int i;
334
335 assert(size == pci_config_size(s));
336 config = qemu_malloc(size);
337
338 qemu_get_buffer(f, config, size);
339 for (i = 0; i < size; ++i) {
340 if ((config[i] ^ s->config[i]) &
341 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
342 qemu_free(config);
343 return -EINVAL;
344 }
345 }
346 memcpy(s->config, config, size);
347
348 pci_update_mappings(s);
349
350 qemu_free(config);
351 return 0;
352 }
353
354 /* just put buffer */
355 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
356 {
357 const uint8_t **v = pv;
358 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
359 qemu_put_buffer(f, *v, size);
360 }
361
362 static VMStateInfo vmstate_info_pci_config = {
363 .name = "pci config",
364 .get = get_pci_config_device,
365 .put = put_pci_config_device,
366 };
367
368 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
369 {
370 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
371 uint32_t irq_state[PCI_NUM_PINS];
372 int i;
373 for (i = 0; i < PCI_NUM_PINS; ++i) {
374 irq_state[i] = qemu_get_be32(f);
375 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
376 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
377 irq_state[i]);
378 return -EINVAL;
379 }
380 }
381
382 for (i = 0; i < PCI_NUM_PINS; ++i) {
383 pci_set_irq_state(s, i, irq_state[i]);
384 }
385
386 return 0;
387 }
388
389 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
390 {
391 int i;
392 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
393
394 for (i = 0; i < PCI_NUM_PINS; ++i) {
395 qemu_put_be32(f, pci_irq_state(s, i));
396 }
397 }
398
399 static VMStateInfo vmstate_info_pci_irq_state = {
400 .name = "pci irq state",
401 .get = get_pci_irq_state,
402 .put = put_pci_irq_state,
403 };
404
405 const VMStateDescription vmstate_pci_device = {
406 .name = "PCIDevice",
407 .version_id = 2,
408 .minimum_version_id = 1,
409 .minimum_version_id_old = 1,
410 .fields = (VMStateField []) {
411 VMSTATE_INT32_LE(version_id, PCIDevice),
412 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
413 vmstate_info_pci_config,
414 PCI_CONFIG_SPACE_SIZE),
415 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
416 vmstate_info_pci_irq_state,
417 PCI_NUM_PINS * sizeof(int32_t)),
418 VMSTATE_END_OF_LIST()
419 }
420 };
421
422 const VMStateDescription vmstate_pcie_device = {
423 .name = "PCIDevice",
424 .version_id = 2,
425 .minimum_version_id = 1,
426 .minimum_version_id_old = 1,
427 .fields = (VMStateField []) {
428 VMSTATE_INT32_LE(version_id, PCIDevice),
429 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
430 vmstate_info_pci_config,
431 PCIE_CONFIG_SPACE_SIZE),
432 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
433 vmstate_info_pci_irq_state,
434 PCI_NUM_PINS * sizeof(int32_t)),
435 VMSTATE_END_OF_LIST()
436 }
437 };
438
439 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
440 {
441 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
442 }
443
444 void pci_device_save(PCIDevice *s, QEMUFile *f)
445 {
446 /* Clear interrupt status bit: it is implicit
447 * in irq_state which we are saving.
448 * This makes us compatible with old devices
449 * which never set or clear this bit. */
450 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
451 vmstate_save_state(f, pci_get_vmstate(s), s);
452 /* Restore the interrupt status bit. */
453 pci_update_irq_status(s);
454 }
455
456 int pci_device_load(PCIDevice *s, QEMUFile *f)
457 {
458 int ret;
459 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
460 /* Restore the interrupt status bit. */
461 pci_update_irq_status(s);
462 return ret;
463 }
464
465 static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
466 {
467 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
468 pci_default_sub_vendor_id);
469 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
470 pci_default_sub_device_id);
471 }
472
473 /*
474 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
475 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
476 */
477 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
478 unsigned int *slotp, unsigned int *funcp)
479 {
480 const char *p;
481 char *e;
482 unsigned long val;
483 unsigned long dom = 0, bus = 0;
484 unsigned int slot = 0;
485 unsigned int func = 0;
486
487 p = addr;
488 val = strtoul(p, &e, 16);
489 if (e == p)
490 return -1;
491 if (*e == ':') {
492 bus = val;
493 p = e + 1;
494 val = strtoul(p, &e, 16);
495 if (e == p)
496 return -1;
497 if (*e == ':') {
498 dom = bus;
499 bus = val;
500 p = e + 1;
501 val = strtoul(p, &e, 16);
502 if (e == p)
503 return -1;
504 }
505 }
506
507 slot = val;
508
509 if (funcp != NULL) {
510 if (*e != '.')
511 return -1;
512
513 p = e + 1;
514 val = strtoul(p, &e, 16);
515 if (e == p)
516 return -1;
517
518 func = val;
519 }
520
521 /* if funcp == NULL func is 0 */
522 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
523 return -1;
524
525 if (*e)
526 return -1;
527
528 /* Note: QEMU doesn't implement domains other than 0 */
529 if (!pci_find_bus(pci_find_root_bus(dom), bus))
530 return -1;
531
532 *domp = dom;
533 *busp = bus;
534 *slotp = slot;
535 if (funcp != NULL)
536 *funcp = func;
537 return 0;
538 }
539
540 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
541 unsigned *slotp)
542 {
543 /* strip legacy tag */
544 if (!strncmp(addr, "pci_addr=", 9)) {
545 addr += 9;
546 }
547 if (pci_parse_devaddr(addr, domp, busp, slotp, NULL)) {
548 monitor_printf(mon, "Invalid pci address\n");
549 return -1;
550 }
551 return 0;
552 }
553
554 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
555 {
556 int dom, bus;
557 unsigned slot;
558
559 if (!devaddr) {
560 *devfnp = -1;
561 return pci_find_bus(pci_find_root_bus(0), 0);
562 }
563
564 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
565 return NULL;
566 }
567
568 *devfnp = PCI_DEVFN(slot, 0);
569 return pci_find_bus(pci_find_root_bus(dom), bus);
570 }
571
572 static void pci_init_cmask(PCIDevice *dev)
573 {
574 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
575 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
576 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
577 dev->cmask[PCI_REVISION_ID] = 0xff;
578 dev->cmask[PCI_CLASS_PROG] = 0xff;
579 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
580 dev->cmask[PCI_HEADER_TYPE] = 0xff;
581 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
582 }
583
584 static void pci_init_wmask(PCIDevice *dev)
585 {
586 int config_size = pci_config_size(dev);
587
588 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
589 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
590 pci_set_word(dev->wmask + PCI_COMMAND,
591 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
592 PCI_COMMAND_INTX_DISABLE);
593 if (dev->cap_present & QEMU_PCI_CAP_SERR) {
594 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
595 }
596
597 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
598 config_size - PCI_CONFIG_HEADER_SIZE);
599 }
600
601 static void pci_init_w1cmask(PCIDevice *dev)
602 {
603 /*
604 * Note: It's okay to set w1cmask even for readonly bits as
605 * long as their value is hardwired to 0.
606 */
607 pci_set_word(dev->w1cmask + PCI_STATUS,
608 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
609 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
610 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
611 }
612
613 static void pci_init_wmask_bridge(PCIDevice *d)
614 {
615 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
616 PCI_SEC_LETENCY_TIMER */
617 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
618
619 /* base and limit */
620 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
621 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
622 pci_set_word(d->wmask + PCI_MEMORY_BASE,
623 PCI_MEMORY_RANGE_MASK & 0xffff);
624 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
625 PCI_MEMORY_RANGE_MASK & 0xffff);
626 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
627 PCI_PREF_RANGE_MASK & 0xffff);
628 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
629 PCI_PREF_RANGE_MASK & 0xffff);
630
631 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
632 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
633
634 /* TODO: add this define to pci_regs.h in linux and then in qemu. */
635 #define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */
636 #define PCI_BRIDGE_CTL_DISCARD 0x100 /* Primary discard timer */
637 #define PCI_BRIDGE_CTL_SEC_DISCARD 0x200 /* Secondary discard timer */
638 #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */
639 #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */
640 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
641 PCI_BRIDGE_CTL_PARITY |
642 PCI_BRIDGE_CTL_SERR |
643 PCI_BRIDGE_CTL_ISA |
644 PCI_BRIDGE_CTL_VGA |
645 PCI_BRIDGE_CTL_VGA_16BIT |
646 PCI_BRIDGE_CTL_MASTER_ABORT |
647 PCI_BRIDGE_CTL_BUS_RESET |
648 PCI_BRIDGE_CTL_FAST_BACK |
649 PCI_BRIDGE_CTL_DISCARD |
650 PCI_BRIDGE_CTL_SEC_DISCARD |
651 PCI_BRIDGE_CTL_DISCARD_SERR);
652 /* Below does not do anything as we never set this bit, put here for
653 * completeness. */
654 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
655 PCI_BRIDGE_CTL_DISCARD_STATUS);
656 }
657
658 static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
659 {
660 uint8_t slot = PCI_SLOT(dev->devfn);
661 uint8_t func;
662
663 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
664 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
665 }
666
667 /*
668 * multifunction bit is interpreted in two ways as follows.
669 * - all functions must set the bit to 1.
670 * Example: Intel X53
671 * - function 0 must set the bit, but the rest function (> 0)
672 * is allowed to leave the bit to 0.
673 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
674 *
675 * So OS (at least Linux) checks the bit of only function 0,
676 * and doesn't see the bit of function > 0.
677 *
678 * The below check allows both interpretation.
679 */
680 if (PCI_FUNC(dev->devfn)) {
681 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
682 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
683 /* function 0 should set multifunction bit */
684 error_report("PCI: single function device can't be populated "
685 "in function %x.%x", slot, PCI_FUNC(dev->devfn));
686 return -1;
687 }
688 return 0;
689 }
690
691 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
692 return 0;
693 }
694 /* function 0 indicates single function, so function > 0 must be NULL */
695 for (func = 1; func < PCI_FUNC_MAX; ++func) {
696 if (bus->devices[PCI_DEVFN(slot, func)]) {
697 error_report("PCI: %x.0 indicates single function, "
698 "but %x.%x is already populated.",
699 slot, slot, func);
700 return -1;
701 }
702 }
703 return 0;
704 }
705
706 static void pci_config_alloc(PCIDevice *pci_dev)
707 {
708 int config_size = pci_config_size(pci_dev);
709
710 pci_dev->config = qemu_mallocz(config_size);
711 pci_dev->cmask = qemu_mallocz(config_size);
712 pci_dev->wmask = qemu_mallocz(config_size);
713 pci_dev->w1cmask = qemu_mallocz(config_size);
714 pci_dev->used = qemu_mallocz(config_size);
715 }
716
717 static void pci_config_free(PCIDevice *pci_dev)
718 {
719 qemu_free(pci_dev->config);
720 qemu_free(pci_dev->cmask);
721 qemu_free(pci_dev->wmask);
722 qemu_free(pci_dev->w1cmask);
723 qemu_free(pci_dev->used);
724 }
725
726 /* -1 for devfn means auto assign */
727 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
728 const char *name, int devfn,
729 PCIConfigReadFunc *config_read,
730 PCIConfigWriteFunc *config_write,
731 bool is_bridge)
732 {
733 if (devfn < 0) {
734 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
735 devfn += PCI_FUNC_MAX) {
736 if (!bus->devices[devfn])
737 goto found;
738 }
739 error_report("PCI: no slot/function available for %s, all in use", name);
740 return NULL;
741 found: ;
742 } else if (bus->devices[devfn]) {
743 error_report("PCI: slot %d function %d not available for %s, in use by %s",
744 PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
745 return NULL;
746 }
747 pci_dev->bus = bus;
748 pci_dev->devfn = devfn;
749 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
750 pci_dev->irq_state = 0;
751 pci_config_alloc(pci_dev);
752
753 if (!is_bridge) {
754 pci_set_default_subsystem_id(pci_dev);
755 }
756 pci_init_cmask(pci_dev);
757 pci_init_wmask(pci_dev);
758 pci_init_w1cmask(pci_dev);
759 if (is_bridge) {
760 pci_init_wmask_bridge(pci_dev);
761 }
762 if (pci_init_multifunction(bus, pci_dev)) {
763 pci_config_free(pci_dev);
764 return NULL;
765 }
766
767 if (!config_read)
768 config_read = pci_default_read_config;
769 if (!config_write)
770 config_write = pci_default_write_config;
771 pci_dev->config_read = config_read;
772 pci_dev->config_write = config_write;
773 bus->devices[devfn] = pci_dev;
774 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
775 pci_dev->version_id = 2; /* Current pci device vmstate version */
776 return pci_dev;
777 }
778
779 static void do_pci_unregister_device(PCIDevice *pci_dev)
780 {
781 qemu_free_irqs(pci_dev->irq);
782 pci_dev->bus->devices[pci_dev->devfn] = NULL;
783 pci_config_free(pci_dev);
784 }
785
786 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
787 int instance_size, int devfn,
788 PCIConfigReadFunc *config_read,
789 PCIConfigWriteFunc *config_write)
790 {
791 PCIDevice *pci_dev;
792
793 pci_dev = qemu_mallocz(instance_size);
794 pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
795 config_read, config_write,
796 PCI_HEADER_TYPE_NORMAL);
797 if (pci_dev == NULL) {
798 hw_error("PCI: can't register device\n");
799 }
800 return pci_dev;
801 }
802
803 static target_phys_addr_t pci_to_cpu_addr(PCIBus *bus,
804 target_phys_addr_t addr)
805 {
806 return addr + bus->mem_base;
807 }
808
809 static void pci_unregister_io_regions(PCIDevice *pci_dev)
810 {
811 PCIIORegion *r;
812 int i;
813
814 for(i = 0; i < PCI_NUM_REGIONS; i++) {
815 r = &pci_dev->io_regions[i];
816 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
817 continue;
818 if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
819 isa_unassign_ioport(r->addr, r->filtered_size);
820 } else {
821 cpu_register_physical_memory(pci_to_cpu_addr(pci_dev->bus,
822 r->addr),
823 r->filtered_size,
824 IO_MEM_UNASSIGNED);
825 }
826 }
827 }
828
829 static int pci_unregister_device(DeviceState *dev)
830 {
831 PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
832 PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
833 int ret = 0;
834
835 if (info->exit)
836 ret = info->exit(pci_dev);
837 if (ret)
838 return ret;
839
840 pci_unregister_io_regions(pci_dev);
841 pci_del_option_rom(pci_dev);
842 qemu_free(pci_dev->romfile);
843 do_pci_unregister_device(pci_dev);
844 return 0;
845 }
846
847 void pci_register_bar(PCIDevice *pci_dev, int region_num,
848 pcibus_t size, uint8_t type,
849 PCIMapIORegionFunc *map_func)
850 {
851 PCIIORegion *r;
852 uint32_t addr;
853 uint64_t wmask;
854
855 assert(region_num >= 0);
856 assert(region_num < PCI_NUM_REGIONS);
857 if (size & (size-1)) {
858 fprintf(stderr, "ERROR: PCI region size must be pow2 "
859 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
860 exit(1);
861 }
862
863 r = &pci_dev->io_regions[region_num];
864 r->addr = PCI_BAR_UNMAPPED;
865 r->size = size;
866 r->filtered_size = size;
867 r->type = type;
868 r->map_func = map_func;
869 r->ram_addr = IO_MEM_UNASSIGNED;
870
871 wmask = ~(size - 1);
872 addr = pci_bar(pci_dev, region_num);
873 if (region_num == PCI_ROM_SLOT) {
874 /* ROM enable bit is writable */
875 wmask |= PCI_ROM_ADDRESS_ENABLE;
876 }
877 pci_set_long(pci_dev->config + addr, type);
878 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
879 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
880 pci_set_quad(pci_dev->wmask + addr, wmask);
881 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
882 } else {
883 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
884 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
885 }
886 }
887
888 static void pci_simple_bar_mapfunc(PCIDevice *pci_dev, int region_num,
889 pcibus_t addr, pcibus_t size, int type)
890 {
891 cpu_register_physical_memory(addr, size,
892 pci_dev->io_regions[region_num].ram_addr);
893 }
894
895 void pci_register_bar_simple(PCIDevice *pci_dev, int region_num,
896 pcibus_t size, uint8_t attr, ram_addr_t ram_addr)
897 {
898 pci_register_bar(pci_dev, region_num, size,
899 PCI_BASE_ADDRESS_SPACE_MEMORY | attr,
900 pci_simple_bar_mapfunc);
901 pci_dev->io_regions[region_num].ram_addr = ram_addr;
902 }
903
904 static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,
905 uint8_t type)
906 {
907 pcibus_t base = *addr;
908 pcibus_t limit = *addr + *size - 1;
909 PCIDevice *br;
910
911 for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {
912 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
913
914 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
915 if (!(cmd & PCI_COMMAND_IO)) {
916 goto no_map;
917 }
918 } else {
919 if (!(cmd & PCI_COMMAND_MEMORY)) {
920 goto no_map;
921 }
922 }
923
924 base = MAX(base, pci_bridge_get_base(br, type));
925 limit = MIN(limit, pci_bridge_get_limit(br, type));
926 }
927
928 if (base > limit) {
929 goto no_map;
930 }
931 *addr = base;
932 *size = limit - base + 1;
933 return;
934 no_map:
935 *addr = PCI_BAR_UNMAPPED;
936 *size = 0;
937 }
938
939 static pcibus_t pci_bar_address(PCIDevice *d,
940 int reg, uint8_t type, pcibus_t size)
941 {
942 pcibus_t new_addr, last_addr;
943 int bar = pci_bar(d, reg);
944 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
945
946 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
947 if (!(cmd & PCI_COMMAND_IO)) {
948 return PCI_BAR_UNMAPPED;
949 }
950 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
951 last_addr = new_addr + size - 1;
952 /* NOTE: we have only 64K ioports on PC */
953 if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
954 return PCI_BAR_UNMAPPED;
955 }
956 return new_addr;
957 }
958
959 if (!(cmd & PCI_COMMAND_MEMORY)) {
960 return PCI_BAR_UNMAPPED;
961 }
962 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
963 new_addr = pci_get_quad(d->config + bar);
964 } else {
965 new_addr = pci_get_long(d->config + bar);
966 }
967 /* the ROM slot has a specific enable bit */
968 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
969 return PCI_BAR_UNMAPPED;
970 }
971 new_addr &= ~(size - 1);
972 last_addr = new_addr + size - 1;
973 /* NOTE: we do not support wrapping */
974 /* XXX: as we cannot support really dynamic
975 mappings, we handle specific values as invalid
976 mappings. */
977 if (last_addr <= new_addr || new_addr == 0 ||
978 last_addr == PCI_BAR_UNMAPPED) {
979 return PCI_BAR_UNMAPPED;
980 }
981
982 /* Now pcibus_t is 64bit.
983 * Check if 32 bit BAR wraps around explicitly.
984 * Without this, PC ide doesn't work well.
985 * TODO: remove this work around.
986 */
987 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
988 return PCI_BAR_UNMAPPED;
989 }
990
991 /*
992 * OS is allowed to set BAR beyond its addressable
993 * bits. For example, 32 bit OS can set 64bit bar
994 * to >4G. Check it. TODO: we might need to support
995 * it in the future for e.g. PAE.
996 */
997 if (last_addr >= TARGET_PHYS_ADDR_MAX) {
998 return PCI_BAR_UNMAPPED;
999 }
1000
1001 return new_addr;
1002 }
1003
1004 static void pci_update_mappings(PCIDevice *d)
1005 {
1006 PCIIORegion *r;
1007 int i;
1008 pcibus_t new_addr, filtered_size;
1009
1010 for(i = 0; i < PCI_NUM_REGIONS; i++) {
1011 r = &d->io_regions[i];
1012
1013 /* this region isn't registered */
1014 if (!r->size)
1015 continue;
1016
1017 new_addr = pci_bar_address(d, i, r->type, r->size);
1018
1019 /* bridge filtering */
1020 filtered_size = r->size;
1021 if (new_addr != PCI_BAR_UNMAPPED) {
1022 pci_bridge_filter(d, &new_addr, &filtered_size, r->type);
1023 }
1024
1025 /* This bar isn't changed */
1026 if (new_addr == r->addr && filtered_size == r->filtered_size)
1027 continue;
1028
1029 /* now do the real mapping */
1030 if (r->addr != PCI_BAR_UNMAPPED) {
1031 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1032 int class;
1033 /* NOTE: specific hack for IDE in PC case:
1034 only one byte must be mapped. */
1035 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1036 if (class == 0x0101 && r->size == 4) {
1037 isa_unassign_ioport(r->addr + 2, 1);
1038 } else {
1039 isa_unassign_ioport(r->addr, r->filtered_size);
1040 }
1041 } else {
1042 cpu_register_physical_memory(pci_to_cpu_addr(d->bus, r->addr),
1043 r->filtered_size,
1044 IO_MEM_UNASSIGNED);
1045 qemu_unregister_coalesced_mmio(r->addr, r->filtered_size);
1046 }
1047 }
1048 r->addr = new_addr;
1049 r->filtered_size = filtered_size;
1050 if (r->addr != PCI_BAR_UNMAPPED) {
1051 /*
1052 * TODO: currently almost all the map funcions assumes
1053 * filtered_size == size and addr & ~(size - 1) == addr.
1054 * However with bridge filtering, they aren't always true.
1055 * Teach them such cases, such that filtered_size < size and
1056 * addr & (size - 1) != 0.
1057 */
1058 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1059 r->map_func(d, i, r->addr, r->filtered_size, r->type);
1060 } else {
1061 r->map_func(d, i, pci_to_cpu_addr(d->bus, r->addr),
1062 r->filtered_size, r->type);
1063 }
1064 }
1065 }
1066 }
1067
1068 static inline int pci_irq_disabled(PCIDevice *d)
1069 {
1070 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1071 }
1072
1073 /* Called after interrupt disabled field update in config space,
1074 * assert/deassert interrupts if necessary.
1075 * Gets original interrupt disable bit value (before update). */
1076 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1077 {
1078 int i, disabled = pci_irq_disabled(d);
1079 if (disabled == was_irq_disabled)
1080 return;
1081 for (i = 0; i < PCI_NUM_PINS; ++i) {
1082 int state = pci_irq_state(d, i);
1083 pci_change_irq_level(d, i, disabled ? -state : state);
1084 }
1085 }
1086
1087 uint32_t pci_default_read_config(PCIDevice *d,
1088 uint32_t address, int len)
1089 {
1090 uint32_t val = 0;
1091 assert(len == 1 || len == 2 || len == 4);
1092 len = MIN(len, pci_config_size(d) - address);
1093 memcpy(&val, d->config + address, len);
1094 return le32_to_cpu(val);
1095 }
1096
1097 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
1098 {
1099 int i, was_irq_disabled = pci_irq_disabled(d);
1100 uint32_t config_size = pci_config_size(d);
1101
1102 for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {
1103 uint8_t wmask = d->wmask[addr + i];
1104 uint8_t w1cmask = d->w1cmask[addr + i];
1105 assert(!(wmask & w1cmask));
1106 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1107 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
1108 }
1109 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1110 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1111 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1112 range_covers_byte(addr, l, PCI_COMMAND))
1113 pci_update_mappings(d);
1114
1115 if (range_covers_byte(addr, l, PCI_COMMAND))
1116 pci_update_irq_disabled(d, was_irq_disabled);
1117 }
1118
1119 /***********************************************************/
1120 /* generic PCI irq support */
1121
1122 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1123 static void pci_set_irq(void *opaque, int irq_num, int level)
1124 {
1125 PCIDevice *pci_dev = opaque;
1126 int change;
1127
1128 change = level - pci_irq_state(pci_dev, irq_num);
1129 if (!change)
1130 return;
1131
1132 pci_set_irq_state(pci_dev, irq_num, level);
1133 pci_update_irq_status(pci_dev);
1134 if (pci_irq_disabled(pci_dev))
1135 return;
1136 pci_change_irq_level(pci_dev, irq_num, change);
1137 }
1138
1139 /***********************************************************/
1140 /* monitor info on PCI */
1141
1142 typedef struct {
1143 uint16_t class;
1144 const char *desc;
1145 const char *fw_name;
1146 uint16_t fw_ign_bits;
1147 } pci_class_desc;
1148
1149 static const pci_class_desc pci_class_descriptions[] =
1150 {
1151 { 0x0001, "VGA controller", "display"},
1152 { 0x0100, "SCSI controller", "scsi"},
1153 { 0x0101, "IDE controller", "ide"},
1154 { 0x0102, "Floppy controller", "fdc"},
1155 { 0x0103, "IPI controller", "ipi"},
1156 { 0x0104, "RAID controller", "raid"},
1157 { 0x0106, "SATA controller"},
1158 { 0x0107, "SAS controller"},
1159 { 0x0180, "Storage controller"},
1160 { 0x0200, "Ethernet controller", "ethernet"},
1161 { 0x0201, "Token Ring controller", "token-ring"},
1162 { 0x0202, "FDDI controller", "fddi"},
1163 { 0x0203, "ATM controller", "atm"},
1164 { 0x0280, "Network controller"},
1165 { 0x0300, "VGA controller", "display", 0x00ff},
1166 { 0x0301, "XGA controller"},
1167 { 0x0302, "3D controller"},
1168 { 0x0380, "Display controller"},
1169 { 0x0400, "Video controller", "video"},
1170 { 0x0401, "Audio controller", "sound"},
1171 { 0x0402, "Phone"},
1172 { 0x0403, "Audio controller", "sound"},
1173 { 0x0480, "Multimedia controller"},
1174 { 0x0500, "RAM controller", "memory"},
1175 { 0x0501, "Flash controller", "flash"},
1176 { 0x0580, "Memory controller"},
1177 { 0x0600, "Host bridge", "host"},
1178 { 0x0601, "ISA bridge", "isa"},
1179 { 0x0602, "EISA bridge", "eisa"},
1180 { 0x0603, "MC bridge", "mca"},
1181 { 0x0604, "PCI bridge", "pci"},
1182 { 0x0605, "PCMCIA bridge", "pcmcia"},
1183 { 0x0606, "NUBUS bridge", "nubus"},
1184 { 0x0607, "CARDBUS bridge", "cardbus"},
1185 { 0x0608, "RACEWAY bridge"},
1186 { 0x0680, "Bridge"},
1187 { 0x0700, "Serial port", "serial"},
1188 { 0x0701, "Parallel port", "parallel"},
1189 { 0x0800, "Interrupt controller", "interrupt-controller"},
1190 { 0x0801, "DMA controller", "dma-controller"},
1191 { 0x0802, "Timer", "timer"},
1192 { 0x0803, "RTC", "rtc"},
1193 { 0x0900, "Keyboard", "keyboard"},
1194 { 0x0901, "Pen", "pen"},
1195 { 0x0902, "Mouse", "mouse"},
1196 { 0x0A00, "Dock station", "dock", 0x00ff},
1197 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1198 { 0x0c00, "Fireware contorller", "fireware"},
1199 { 0x0c01, "Access bus controller", "access-bus"},
1200 { 0x0c02, "SSA controller", "ssa"},
1201 { 0x0c03, "USB controller", "usb"},
1202 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1203 { 0, NULL}
1204 };
1205
1206 static void pci_for_each_device_under_bus(PCIBus *bus,
1207 void (*fn)(PCIBus *b, PCIDevice *d))
1208 {
1209 PCIDevice *d;
1210 int devfn;
1211
1212 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1213 d = bus->devices[devfn];
1214 if (d) {
1215 fn(bus, d);
1216 }
1217 }
1218 }
1219
1220 void pci_for_each_device(PCIBus *bus, int bus_num,
1221 void (*fn)(PCIBus *b, PCIDevice *d))
1222 {
1223 bus = pci_find_bus(bus, bus_num);
1224
1225 if (bus) {
1226 pci_for_each_device_under_bus(bus, fn);
1227 }
1228 }
1229
1230 static void pci_device_print(Monitor *mon, QDict *device)
1231 {
1232 QDict *qdict;
1233 QListEntry *entry;
1234 uint64_t addr, size;
1235
1236 monitor_printf(mon, " Bus %2" PRId64 ", ", qdict_get_int(device, "bus"));
1237 monitor_printf(mon, "device %3" PRId64 ", function %" PRId64 ":\n",
1238 qdict_get_int(device, "slot"),
1239 qdict_get_int(device, "function"));
1240 monitor_printf(mon, " ");
1241
1242 qdict = qdict_get_qdict(device, "class_info");
1243 if (qdict_haskey(qdict, "desc")) {
1244 monitor_printf(mon, "%s", qdict_get_str(qdict, "desc"));
1245 } else {
1246 monitor_printf(mon, "Class %04" PRId64, qdict_get_int(qdict, "class"));
1247 }
1248
1249 qdict = qdict_get_qdict(device, "id");
1250 monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n",
1251 qdict_get_int(qdict, "device"),
1252 qdict_get_int(qdict, "vendor"));
1253
1254 if (qdict_haskey(device, "irq")) {
1255 monitor_printf(mon, " IRQ %" PRId64 ".\n",
1256 qdict_get_int(device, "irq"));
1257 }
1258
1259 if (qdict_haskey(device, "pci_bridge")) {
1260 QDict *info;
1261
1262 qdict = qdict_get_qdict(device, "pci_bridge");
1263
1264 info = qdict_get_qdict(qdict, "bus");
1265 monitor_printf(mon, " BUS %" PRId64 ".\n",
1266 qdict_get_int(info, "number"));
1267 monitor_printf(mon, " secondary bus %" PRId64 ".\n",
1268 qdict_get_int(info, "secondary"));
1269 monitor_printf(mon, " subordinate bus %" PRId64 ".\n",
1270 qdict_get_int(info, "subordinate"));
1271
1272 info = qdict_get_qdict(qdict, "io_range");
1273 monitor_printf(mon, " IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
1274 qdict_get_int(info, "base"),
1275 qdict_get_int(info, "limit"));
1276
1277 info = qdict_get_qdict(qdict, "memory_range");
1278 monitor_printf(mon,
1279 " memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
1280 qdict_get_int(info, "base"),
1281 qdict_get_int(info, "limit"));
1282
1283 info = qdict_get_qdict(qdict, "prefetchable_range");
1284 monitor_printf(mon, " prefetchable memory range "
1285 "[0x%08"PRIx64", 0x%08"PRIx64"]\n",
1286 qdict_get_int(info, "base"),
1287 qdict_get_int(info, "limit"));
1288 }
1289
1290 QLIST_FOREACH_ENTRY(qdict_get_qlist(device, "regions"), entry) {
1291 qdict = qobject_to_qdict(qlist_entry_obj(entry));
1292 monitor_printf(mon, " BAR%d: ", (int) qdict_get_int(qdict, "bar"));
1293
1294 addr = qdict_get_int(qdict, "address");
1295 size = qdict_get_int(qdict, "size");
1296
1297 if (!strcmp(qdict_get_str(qdict, "type"), "io")) {
1298 monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
1299 " [0x%04"FMT_PCIBUS"].\n",
1300 addr, addr + size - 1);
1301 } else {
1302 monitor_printf(mon, "%d bit%s memory at 0x%08"FMT_PCIBUS
1303 " [0x%08"FMT_PCIBUS"].\n",
1304 qdict_get_bool(qdict, "mem_type_64") ? 64 : 32,
1305 qdict_get_bool(qdict, "prefetch") ?
1306 " prefetchable" : "", addr, addr + size - 1);
1307 }
1308 }
1309
1310 monitor_printf(mon, " id \"%s\"\n", qdict_get_str(device, "qdev_id"));
1311
1312 if (qdict_haskey(device, "pci_bridge")) {
1313 qdict = qdict_get_qdict(device, "pci_bridge");
1314 if (qdict_haskey(qdict, "devices")) {
1315 QListEntry *dev;
1316 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1317 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1318 }
1319 }
1320 }
1321 }
1322
1323 void do_pci_info_print(Monitor *mon, const QObject *data)
1324 {
1325 QListEntry *bus, *dev;
1326
1327 QLIST_FOREACH_ENTRY(qobject_to_qlist(data), bus) {
1328 QDict *qdict = qobject_to_qdict(qlist_entry_obj(bus));
1329 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1330 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1331 }
1332 }
1333 }
1334
1335 static QObject *pci_get_dev_class(const PCIDevice *dev)
1336 {
1337 int class;
1338 const pci_class_desc *desc;
1339
1340 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1341 desc = pci_class_descriptions;
1342 while (desc->desc && class != desc->class)
1343 desc++;
1344
1345 if (desc->desc) {
1346 return qobject_from_jsonf("{ 'desc': %s, 'class': %d }",
1347 desc->desc, class);
1348 } else {
1349 return qobject_from_jsonf("{ 'class': %d }", class);
1350 }
1351 }
1352
1353 static QObject *pci_get_dev_id(const PCIDevice *dev)
1354 {
1355 return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }",
1356 pci_get_word(dev->config + PCI_VENDOR_ID),
1357 pci_get_word(dev->config + PCI_DEVICE_ID));
1358 }
1359
1360 static QObject *pci_get_regions_list(const PCIDevice *dev)
1361 {
1362 int i;
1363 QList *regions_list;
1364
1365 regions_list = qlist_new();
1366
1367 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1368 QObject *obj;
1369 const PCIIORegion *r = &dev->io_regions[i];
1370
1371 if (!r->size) {
1372 continue;
1373 }
1374
1375 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1376 obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'io', "
1377 "'address': %" PRId64 ", "
1378 "'size': %" PRId64 " }",
1379 i, r->addr, r->size);
1380 } else {
1381 int mem_type_64 = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64;
1382
1383 obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', "
1384 "'mem_type_64': %i, 'prefetch': %i, "
1385 "'address': %" PRId64 ", "
1386 "'size': %" PRId64 " }",
1387 i, mem_type_64,
1388 r->type & PCI_BASE_ADDRESS_MEM_PREFETCH,
1389 r->addr, r->size);
1390 }
1391
1392 qlist_append_obj(regions_list, obj);
1393 }
1394
1395 return QOBJECT(regions_list);
1396 }
1397
1398 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num);
1399
1400 static QObject *pci_get_dev_dict(PCIDevice *dev, PCIBus *bus, int bus_num)
1401 {
1402 uint8_t type;
1403 QObject *obj;
1404
1405 obj = qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d," "'class_info': %p, 'id': %p, 'regions': %p,"
1406 " 'qdev_id': %s }",
1407 bus_num,
1408 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
1409 pci_get_dev_class(dev), pci_get_dev_id(dev),
1410 pci_get_regions_list(dev),
1411 dev->qdev.id ? dev->qdev.id : "");
1412
1413 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1414 QDict *qdict = qobject_to_qdict(obj);
1415 qdict_put(qdict, "irq", qint_from_int(dev->config[PCI_INTERRUPT_LINE]));
1416 }
1417
1418 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1419 if (type == PCI_HEADER_TYPE_BRIDGE) {
1420 QDict *qdict;
1421 QObject *pci_bridge;
1422
1423 pci_bridge = qobject_from_jsonf("{ 'bus': "
1424 "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, "
1425 "'io_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1426 "'memory_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1427 "'prefetchable_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "} }",
1428 dev->config[PCI_PRIMARY_BUS], dev->config[PCI_SECONDARY_BUS],
1429 dev->config[PCI_SUBORDINATE_BUS],
1430 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO),
1431 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO),
1432 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1433 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1434 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1435 PCI_BASE_ADDRESS_MEM_PREFETCH),
1436 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1437 PCI_BASE_ADDRESS_MEM_PREFETCH));
1438
1439 if (dev->config[PCI_SECONDARY_BUS] != 0) {
1440 PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]);
1441
1442 if (child_bus) {
1443 qdict = qobject_to_qdict(pci_bridge);
1444 qdict_put_obj(qdict, "devices",
1445 pci_get_devices_list(child_bus,
1446 dev->config[PCI_SECONDARY_BUS]));
1447 }
1448 }
1449 qdict = qobject_to_qdict(obj);
1450 qdict_put_obj(qdict, "pci_bridge", pci_bridge);
1451 }
1452
1453 return obj;
1454 }
1455
1456 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num)
1457 {
1458 int devfn;
1459 PCIDevice *dev;
1460 QList *dev_list;
1461
1462 dev_list = qlist_new();
1463
1464 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1465 dev = bus->devices[devfn];
1466 if (dev) {
1467 qlist_append_obj(dev_list, pci_get_dev_dict(dev, bus, bus_num));
1468 }
1469 }
1470
1471 return QOBJECT(dev_list);
1472 }
1473
1474 static QObject *pci_get_bus_dict(PCIBus *bus, int bus_num)
1475 {
1476 bus = pci_find_bus(bus, bus_num);
1477 if (bus) {
1478 return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }",
1479 bus_num, pci_get_devices_list(bus, bus_num));
1480 }
1481
1482 return NULL;
1483 }
1484
1485 void do_pci_info(Monitor *mon, QObject **ret_data)
1486 {
1487 QList *bus_list;
1488 struct PCIHostBus *host;
1489
1490 bus_list = qlist_new();
1491
1492 QLIST_FOREACH(host, &host_buses, next) {
1493 QObject *obj = pci_get_bus_dict(host->bus, 0);
1494 if (obj) {
1495 qlist_append_obj(bus_list, obj);
1496 }
1497 }
1498
1499 *ret_data = QOBJECT(bus_list);
1500 }
1501
1502 static const char * const pci_nic_models[] = {
1503 "ne2k_pci",
1504 "i82551",
1505 "i82557b",
1506 "i82559er",
1507 "rtl8139",
1508 "e1000",
1509 "pcnet",
1510 "virtio",
1511 NULL
1512 };
1513
1514 static const char * const pci_nic_names[] = {
1515 "ne2k_pci",
1516 "i82551",
1517 "i82557b",
1518 "i82559er",
1519 "rtl8139",
1520 "e1000",
1521 "pcnet",
1522 "virtio-net-pci",
1523 NULL
1524 };
1525
1526 /* Initialize a PCI NIC. */
1527 /* FIXME callers should check for failure, but don't */
1528 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1529 const char *default_devaddr)
1530 {
1531 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1532 PCIBus *bus;
1533 int devfn;
1534 PCIDevice *pci_dev;
1535 DeviceState *dev;
1536 int i;
1537
1538 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1539 if (i < 0)
1540 return NULL;
1541
1542 bus = pci_get_bus_devfn(&devfn, devaddr);
1543 if (!bus) {
1544 error_report("Invalid PCI device address %s for device %s",
1545 devaddr, pci_nic_names[i]);
1546 return NULL;
1547 }
1548
1549 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1550 dev = &pci_dev->qdev;
1551 qdev_set_nic_properties(dev, nd);
1552 if (qdev_init(dev) < 0)
1553 return NULL;
1554 return pci_dev;
1555 }
1556
1557 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1558 const char *default_devaddr)
1559 {
1560 PCIDevice *res;
1561
1562 if (qemu_show_nic_models(nd->model, pci_nic_models))
1563 exit(0);
1564
1565 res = pci_nic_init(nd, default_model, default_devaddr);
1566 if (!res)
1567 exit(1);
1568 return res;
1569 }
1570
1571 static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d)
1572 {
1573 pci_update_mappings(d);
1574 }
1575
1576 void pci_bridge_update_mappings(PCIBus *b)
1577 {
1578 PCIBus *child;
1579
1580 pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn);
1581
1582 QLIST_FOREACH(child, &b->child, sibling) {
1583 pci_bridge_update_mappings(child);
1584 }
1585 }
1586
1587 /* Whether a given bus number is in range of the secondary
1588 * bus of the given bridge device. */
1589 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1590 {
1591 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1592 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
1593 dev->config[PCI_SECONDARY_BUS] < bus_num &&
1594 bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1595 }
1596
1597 PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1598 {
1599 PCIBus *sec;
1600
1601 if (!bus) {
1602 return NULL;
1603 }
1604
1605 if (pci_bus_num(bus) == bus_num) {
1606 return bus;
1607 }
1608
1609 /* Consider all bus numbers in range for the host pci bridge. */
1610 if (bus->parent_dev &&
1611 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
1612 return NULL;
1613 }
1614
1615 /* try child bus */
1616 for (; bus; bus = sec) {
1617 QLIST_FOREACH(sec, &bus->child, sibling) {
1618 assert(sec->parent_dev);
1619 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
1620 return sec;
1621 }
1622 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
1623 break;
1624 }
1625 }
1626 }
1627
1628 return NULL;
1629 }
1630
1631 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
1632 {
1633 bus = pci_find_bus(bus, bus_num);
1634
1635 if (!bus)
1636 return NULL;
1637
1638 return bus->devices[devfn];
1639 }
1640
1641 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1642 {
1643 PCIDevice *pci_dev = (PCIDevice *)qdev;
1644 PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1645 PCIBus *bus;
1646 int devfn, rc;
1647 bool is_default_rom;
1648
1649 /* initialize cap_present for pci_is_express() and pci_config_size() */
1650 if (info->is_express) {
1651 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1652 }
1653
1654 bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1655 devfn = pci_dev->devfn;
1656 pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
1657 info->config_read, info->config_write,
1658 info->is_bridge);
1659 if (pci_dev == NULL)
1660 return -1;
1661 if (qdev->hotplugged && info->no_hotplug) {
1662 qerror_report(QERR_DEVICE_NO_HOTPLUG, info->qdev.name);
1663 do_pci_unregister_device(pci_dev);
1664 return -1;
1665 }
1666 rc = info->init(pci_dev);
1667 if (rc != 0) {
1668 do_pci_unregister_device(pci_dev);
1669 return rc;
1670 }
1671
1672 /* rom loading */
1673 is_default_rom = false;
1674 if (pci_dev->romfile == NULL && info->romfile != NULL) {
1675 pci_dev->romfile = qemu_strdup(info->romfile);
1676 is_default_rom = true;
1677 }
1678 pci_add_option_rom(pci_dev, is_default_rom);
1679
1680 if (bus->hotplug) {
1681 /* Let buses differentiate between hotplug and when device is
1682 * enabled during qemu machine creation. */
1683 rc = bus->hotplug(bus->hotplug_qdev, pci_dev,
1684 qdev->hotplugged ? PCI_HOTPLUG_ENABLED:
1685 PCI_COLDPLUG_ENABLED);
1686 if (rc != 0) {
1687 int r = pci_unregister_device(&pci_dev->qdev);
1688 assert(!r);
1689 return rc;
1690 }
1691 }
1692 return 0;
1693 }
1694
1695 static int pci_unplug_device(DeviceState *qdev)
1696 {
1697 PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1698 PCIDeviceInfo *info = container_of(qdev->info, PCIDeviceInfo, qdev);
1699
1700 if (info->no_hotplug) {
1701 qerror_report(QERR_DEVICE_NO_HOTPLUG, info->qdev.name);
1702 return -1;
1703 }
1704 return dev->bus->hotplug(dev->bus->hotplug_qdev, dev,
1705 PCI_HOTPLUG_DISABLED);
1706 }
1707
1708 void pci_qdev_register(PCIDeviceInfo *info)
1709 {
1710 info->qdev.init = pci_qdev_init;
1711 info->qdev.unplug = pci_unplug_device;
1712 info->qdev.exit = pci_unregister_device;
1713 info->qdev.bus_info = &pci_bus_info;
1714 qdev_register(&info->qdev);
1715 }
1716
1717 void pci_qdev_register_many(PCIDeviceInfo *info)
1718 {
1719 while (info->qdev.name) {
1720 pci_qdev_register(info);
1721 info++;
1722 }
1723 }
1724
1725 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
1726 const char *name)
1727 {
1728 DeviceState *dev;
1729
1730 dev = qdev_create(&bus->qbus, name);
1731 qdev_prop_set_uint32(dev, "addr", devfn);
1732 qdev_prop_set_bit(dev, "multifunction", multifunction);
1733 return DO_UPCAST(PCIDevice, qdev, dev);
1734 }
1735
1736 PCIDevice *pci_try_create_multifunction(PCIBus *bus, int devfn,
1737 bool multifunction,
1738 const char *name)
1739 {
1740 DeviceState *dev;
1741
1742 dev = qdev_try_create(&bus->qbus, name);
1743 if (!dev) {
1744 return NULL;
1745 }
1746 qdev_prop_set_uint32(dev, "addr", devfn);
1747 qdev_prop_set_bit(dev, "multifunction", multifunction);
1748 return DO_UPCAST(PCIDevice, qdev, dev);
1749 }
1750
1751 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
1752 bool multifunction,
1753 const char *name)
1754 {
1755 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
1756 qdev_init_nofail(&dev->qdev);
1757 return dev;
1758 }
1759
1760 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1761 {
1762 return pci_create_multifunction(bus, devfn, false, name);
1763 }
1764
1765 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1766 {
1767 return pci_create_simple_multifunction(bus, devfn, false, name);
1768 }
1769
1770 PCIDevice *pci_try_create(PCIBus *bus, int devfn, const char *name)
1771 {
1772 return pci_try_create_multifunction(bus, devfn, false, name);
1773 }
1774
1775 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1776 {
1777 int config_size = pci_config_size(pdev);
1778 int offset = PCI_CONFIG_HEADER_SIZE;
1779 int i;
1780 for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1781 if (pdev->used[i])
1782 offset = i + 1;
1783 else if (i - offset + 1 == size)
1784 return offset;
1785 return 0;
1786 }
1787
1788 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1789 uint8_t *prev_p)
1790 {
1791 uint8_t next, prev;
1792
1793 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1794 return 0;
1795
1796 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1797 prev = next + PCI_CAP_LIST_NEXT)
1798 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1799 break;
1800
1801 if (prev_p)
1802 *prev_p = prev;
1803 return next;
1804 }
1805
1806 static void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr, pcibus_t size, int type)
1807 {
1808 cpu_register_physical_memory(addr, size, pdev->rom_offset);
1809 }
1810
1811 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
1812 This is needed for an option rom which is used for more than one device. */
1813 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
1814 {
1815 uint16_t vendor_id;
1816 uint16_t device_id;
1817 uint16_t rom_vendor_id;
1818 uint16_t rom_device_id;
1819 uint16_t rom_magic;
1820 uint16_t pcir_offset;
1821 uint8_t checksum;
1822
1823 /* Words in rom data are little endian (like in PCI configuration),
1824 so they can be read / written with pci_get_word / pci_set_word. */
1825
1826 /* Only a valid rom will be patched. */
1827 rom_magic = pci_get_word(ptr);
1828 if (rom_magic != 0xaa55) {
1829 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
1830 return;
1831 }
1832 pcir_offset = pci_get_word(ptr + 0x18);
1833 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
1834 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
1835 return;
1836 }
1837
1838 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
1839 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
1840 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
1841 rom_device_id = pci_get_word(ptr + pcir_offset + 6);
1842
1843 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
1844 vendor_id, device_id, rom_vendor_id, rom_device_id);
1845
1846 checksum = ptr[6];
1847
1848 if (vendor_id != rom_vendor_id) {
1849 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
1850 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
1851 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
1852 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1853 ptr[6] = checksum;
1854 pci_set_word(ptr + pcir_offset + 4, vendor_id);
1855 }
1856
1857 if (device_id != rom_device_id) {
1858 /* Patch device id and checksum (at offset 6 for etherboot roms). */
1859 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
1860 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
1861 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1862 ptr[6] = checksum;
1863 pci_set_word(ptr + pcir_offset + 6, device_id);
1864 }
1865 }
1866
1867 /* Add an option rom for the device */
1868 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom)
1869 {
1870 int size;
1871 char *path;
1872 void *ptr;
1873 char name[32];
1874
1875 if (!pdev->romfile)
1876 return 0;
1877 if (strlen(pdev->romfile) == 0)
1878 return 0;
1879
1880 if (!pdev->rom_bar) {
1881 /*
1882 * Load rom via fw_cfg instead of creating a rom bar,
1883 * for 0.11 compatibility.
1884 */
1885 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
1886 if (class == 0x0300) {
1887 rom_add_vga(pdev->romfile);
1888 } else {
1889 rom_add_option(pdev->romfile, -1);
1890 }
1891 return 0;
1892 }
1893
1894 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
1895 if (path == NULL) {
1896 path = qemu_strdup(pdev->romfile);
1897 }
1898
1899 size = get_image_size(path);
1900 if (size < 0) {
1901 error_report("%s: failed to find romfile \"%s\"",
1902 __FUNCTION__, pdev->romfile);
1903 qemu_free(path);
1904 return -1;
1905 }
1906 if (size & (size - 1)) {
1907 size = 1 << qemu_fls(size);
1908 }
1909
1910 if (pdev->qdev.info->vmsd)
1911 snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->vmsd->name);
1912 else
1913 snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->name);
1914 pdev->rom_offset = qemu_ram_alloc(&pdev->qdev, name, size);
1915
1916 ptr = qemu_get_ram_ptr(pdev->rom_offset);
1917 load_image(path, ptr);
1918 qemu_free(path);
1919
1920 if (is_default_rom) {
1921 /* Only the default rom images will be patched (if needed). */
1922 pci_patch_ids(pdev, ptr, size);
1923 }
1924
1925 qemu_put_ram_ptr(ptr);
1926
1927 pci_register_bar(pdev, PCI_ROM_SLOT, size,
1928 0, pci_map_option_rom);
1929
1930 return 0;
1931 }
1932
1933 static void pci_del_option_rom(PCIDevice *pdev)
1934 {
1935 if (!pdev->rom_offset)
1936 return;
1937
1938 qemu_ram_free(pdev->rom_offset);
1939 pdev->rom_offset = 0;
1940 }
1941
1942 /*
1943 * if !offset
1944 * Reserve space and add capability to the linked list in pci config space
1945 *
1946 * if offset = 0,
1947 * Find and reserve space and add capability to the linked list
1948 * in pci config space */
1949 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
1950 uint8_t offset, uint8_t size)
1951 {
1952 uint8_t *config;
1953 if (!offset) {
1954 offset = pci_find_space(pdev, size);
1955 if (!offset) {
1956 return -ENOSPC;
1957 }
1958 }
1959
1960 config = pdev->config + offset;
1961 config[PCI_CAP_LIST_ID] = cap_id;
1962 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1963 pdev->config[PCI_CAPABILITY_LIST] = offset;
1964 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1965 memset(pdev->used + offset, 0xFF, size);
1966 /* Make capability read-only by default */
1967 memset(pdev->wmask + offset, 0, size);
1968 /* Check capability by default */
1969 memset(pdev->cmask + offset, 0xFF, size);
1970 return offset;
1971 }
1972
1973 /* Unlink capability from the pci config space. */
1974 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1975 {
1976 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1977 if (!offset)
1978 return;
1979 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1980 /* Make capability writable again */
1981 memset(pdev->wmask + offset, 0xff, size);
1982 memset(pdev->w1cmask + offset, 0, size);
1983 /* Clear cmask as device-specific registers can't be checked */
1984 memset(pdev->cmask + offset, 0, size);
1985 memset(pdev->used + offset, 0, size);
1986
1987 if (!pdev->config[PCI_CAPABILITY_LIST])
1988 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1989 }
1990
1991 /* Reserve space for capability at a known offset (to call after load). */
1992 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1993 {
1994 memset(pdev->used + offset, 0xff, size);
1995 }
1996
1997 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1998 {
1999 return pci_find_capability_list(pdev, cap_id, NULL);
2000 }
2001
2002 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
2003 {
2004 PCIDevice *d = (PCIDevice *)dev;
2005 const pci_class_desc *desc;
2006 char ctxt[64];
2007 PCIIORegion *r;
2008 int i, class;
2009
2010 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2011 desc = pci_class_descriptions;
2012 while (desc->desc && class != desc->class)
2013 desc++;
2014 if (desc->desc) {
2015 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
2016 } else {
2017 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
2018 }
2019
2020 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
2021 "pci id %04x:%04x (sub %04x:%04x)\n",
2022 indent, "", ctxt, pci_bus_num(d->bus),
2023 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
2024 pci_get_word(d->config + PCI_VENDOR_ID),
2025 pci_get_word(d->config + PCI_DEVICE_ID),
2026 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
2027 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
2028 for (i = 0; i < PCI_NUM_REGIONS; i++) {
2029 r = &d->io_regions[i];
2030 if (!r->size)
2031 continue;
2032 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2033 " [0x%"FMT_PCIBUS"]\n",
2034 indent, "",
2035 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
2036 r->addr, r->addr + r->size - 1);
2037 }
2038 }
2039
2040 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
2041 {
2042 PCIDevice *d = (PCIDevice *)dev;
2043 const char *name = NULL;
2044 const pci_class_desc *desc = pci_class_descriptions;
2045 int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2046
2047 while (desc->desc &&
2048 (class & ~desc->fw_ign_bits) !=
2049 (desc->class & ~desc->fw_ign_bits)) {
2050 desc++;
2051 }
2052
2053 if (desc->desc) {
2054 name = desc->fw_name;
2055 }
2056
2057 if (name) {
2058 pstrcpy(buf, len, name);
2059 } else {
2060 snprintf(buf, len, "pci%04x,%04x",
2061 pci_get_word(d->config + PCI_VENDOR_ID),
2062 pci_get_word(d->config + PCI_DEVICE_ID));
2063 }
2064
2065 return buf;
2066 }
2067
2068 static char *pcibus_get_fw_dev_path(DeviceState *dev)
2069 {
2070 PCIDevice *d = (PCIDevice *)dev;
2071 char path[50], name[33];
2072 int off;
2073
2074 off = snprintf(path, sizeof(path), "%s@%x",
2075 pci_dev_fw_name(dev, name, sizeof name),
2076 PCI_SLOT(d->devfn));
2077 if (PCI_FUNC(d->devfn))
2078 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
2079 return strdup(path);
2080 }
2081
2082 static char *pcibus_get_dev_path(DeviceState *dev)
2083 {
2084 PCIDevice *d = container_of(dev, PCIDevice, qdev);
2085 PCIDevice *t;
2086 int slot_depth;
2087 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2088 * 00 is added here to make this format compatible with
2089 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2090 * Slot.Function list specifies the slot and function numbers for all
2091 * devices on the path from root to the specific device. */
2092 char domain[] = "DDDD:00";
2093 char slot[] = ":SS.F";
2094 int domain_len = sizeof domain - 1 /* For '\0' */;
2095 int slot_len = sizeof slot - 1 /* For '\0' */;
2096 int path_len;
2097 char *path, *p;
2098 int s;
2099
2100 /* Calculate # of slots on path between device and root. */;
2101 slot_depth = 0;
2102 for (t = d; t; t = t->bus->parent_dev) {
2103 ++slot_depth;
2104 }
2105
2106 path_len = domain_len + slot_len * slot_depth;
2107
2108 /* Allocate memory, fill in the terminating null byte. */
2109 path = qemu_malloc(path_len + 1 /* For '\0' */);
2110 path[path_len] = '\0';
2111
2112 /* First field is the domain. */
2113 s = snprintf(domain, sizeof domain, "%04x:00", pci_find_domain(d->bus));
2114 assert(s == domain_len);
2115 memcpy(path, domain, domain_len);
2116
2117 /* Fill in slot numbers. We walk up from device to root, so need to print
2118 * them in the reverse order, last to first. */
2119 p = path + path_len;
2120 for (t = d; t; t = t->bus->parent_dev) {
2121 p -= slot_len;
2122 s = snprintf(slot, sizeof slot, ":%02x.%x",
2123 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn));
2124 assert(s == slot_len);
2125 memcpy(p, slot, slot_len);
2126 }
2127
2128 return path;
2129 }
2130
2131 static int pci_qdev_find_recursive(PCIBus *bus,
2132 const char *id, PCIDevice **pdev)
2133 {
2134 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
2135 if (!qdev) {
2136 return -ENODEV;
2137 }
2138
2139 /* roughly check if given qdev is pci device */
2140 if (qdev->info->init == &pci_qdev_init &&
2141 qdev->parent_bus->info == &pci_bus_info) {
2142 *pdev = DO_UPCAST(PCIDevice, qdev, qdev);
2143 return 0;
2144 }
2145 return -EINVAL;
2146 }
2147
2148 int pci_qdev_find_device(const char *id, PCIDevice **pdev)
2149 {
2150 struct PCIHostBus *host;
2151 int rc = -ENODEV;
2152
2153 QLIST_FOREACH(host, &host_buses, next) {
2154 int tmp = pci_qdev_find_recursive(host->bus, id, pdev);
2155 if (!tmp) {
2156 rc = 0;
2157 break;
2158 }
2159 if (tmp != -ENODEV) {
2160 rc = tmp;
2161 }
2162 }
2163
2164 return rc;
2165 }