qdev: don't access name through info
[qemu.git] / hw / pci.c
1 /*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "pci.h"
26 #include "pci_bridge.h"
27 #include "pci_internals.h"
28 #include "monitor.h"
29 #include "net.h"
30 #include "sysemu.h"
31 #include "loader.h"
32 #include "range.h"
33 #include "qmp-commands.h"
34
35 //#define DEBUG_PCI
36 #ifdef DEBUG_PCI
37 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
38 #else
39 # define PCI_DPRINTF(format, ...) do { } while (0)
40 #endif
41
42 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
43 static char *pcibus_get_dev_path(DeviceState *dev);
44 static char *pcibus_get_fw_dev_path(DeviceState *dev);
45 static int pcibus_reset(BusState *qbus);
46
47 struct BusInfo pci_bus_info = {
48 .name = "PCI",
49 .size = sizeof(PCIBus),
50 .print_dev = pcibus_dev_print,
51 .get_dev_path = pcibus_get_dev_path,
52 .get_fw_dev_path = pcibus_get_fw_dev_path,
53 .reset = pcibus_reset,
54 .props = (Property[]) {
55 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
56 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
57 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
58 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
59 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
60 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
61 QEMU_PCI_CAP_SERR_BITNR, true),
62 DEFINE_PROP_END_OF_LIST()
63 }
64 };
65
66 static void pci_update_mappings(PCIDevice *d);
67 static void pci_set_irq(void *opaque, int irq_num, int level);
68 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom);
69 static void pci_del_option_rom(PCIDevice *pdev);
70
71 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
72 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
73
74 struct PCIHostBus {
75 int domain;
76 struct PCIBus *bus;
77 QLIST_ENTRY(PCIHostBus) next;
78 };
79 static QLIST_HEAD(, PCIHostBus) host_buses;
80
81 static const VMStateDescription vmstate_pcibus = {
82 .name = "PCIBUS",
83 .version_id = 1,
84 .minimum_version_id = 1,
85 .minimum_version_id_old = 1,
86 .fields = (VMStateField []) {
87 VMSTATE_INT32_EQUAL(nirq, PCIBus),
88 VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
89 VMSTATE_END_OF_LIST()
90 }
91 };
92
93 static int pci_bar(PCIDevice *d, int reg)
94 {
95 uint8_t type;
96
97 if (reg != PCI_ROM_SLOT)
98 return PCI_BASE_ADDRESS_0 + reg * 4;
99
100 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
101 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
102 }
103
104 static inline int pci_irq_state(PCIDevice *d, int irq_num)
105 {
106 return (d->irq_state >> irq_num) & 0x1;
107 }
108
109 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
110 {
111 d->irq_state &= ~(0x1 << irq_num);
112 d->irq_state |= level << irq_num;
113 }
114
115 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
116 {
117 PCIBus *bus;
118 for (;;) {
119 bus = pci_dev->bus;
120 irq_num = bus->map_irq(pci_dev, irq_num);
121 if (bus->set_irq)
122 break;
123 pci_dev = bus->parent_dev;
124 }
125 bus->irq_count[irq_num] += change;
126 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
127 }
128
129 int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
130 {
131 assert(irq_num >= 0);
132 assert(irq_num < bus->nirq);
133 return !!bus->irq_count[irq_num];
134 }
135
136 /* Update interrupt status bit in config space on interrupt
137 * state change. */
138 static void pci_update_irq_status(PCIDevice *dev)
139 {
140 if (dev->irq_state) {
141 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
142 } else {
143 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
144 }
145 }
146
147 void pci_device_deassert_intx(PCIDevice *dev)
148 {
149 int i;
150 for (i = 0; i < PCI_NUM_PINS; ++i) {
151 qemu_set_irq(dev->irq[i], 0);
152 }
153 }
154
155 /*
156 * This function is called on #RST and FLR.
157 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
158 */
159 void pci_device_reset(PCIDevice *dev)
160 {
161 int r;
162
163 qdev_reset_all(&dev->qdev);
164
165 dev->irq_state = 0;
166 pci_update_irq_status(dev);
167 pci_device_deassert_intx(dev);
168 /* Clear all writable bits */
169 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
170 pci_get_word(dev->wmask + PCI_COMMAND) |
171 pci_get_word(dev->w1cmask + PCI_COMMAND));
172 pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
173 pci_get_word(dev->wmask + PCI_STATUS) |
174 pci_get_word(dev->w1cmask + PCI_STATUS));
175 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
176 dev->config[PCI_INTERRUPT_LINE] = 0x0;
177 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
178 PCIIORegion *region = &dev->io_regions[r];
179 if (!region->size) {
180 continue;
181 }
182
183 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
184 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
185 pci_set_quad(dev->config + pci_bar(dev, r), region->type);
186 } else {
187 pci_set_long(dev->config + pci_bar(dev, r), region->type);
188 }
189 }
190 pci_update_mappings(dev);
191 }
192
193 /*
194 * Trigger pci bus reset under a given bus.
195 * To be called on RST# assert.
196 */
197 void pci_bus_reset(PCIBus *bus)
198 {
199 int i;
200
201 for (i = 0; i < bus->nirq; i++) {
202 bus->irq_count[i] = 0;
203 }
204 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
205 if (bus->devices[i]) {
206 pci_device_reset(bus->devices[i]);
207 }
208 }
209 }
210
211 static int pcibus_reset(BusState *qbus)
212 {
213 pci_bus_reset(DO_UPCAST(PCIBus, qbus, qbus));
214
215 /* topology traverse is done by pci_bus_reset().
216 Tell qbus/qdev walker not to traverse the tree */
217 return 1;
218 }
219
220 static void pci_host_bus_register(int domain, PCIBus *bus)
221 {
222 struct PCIHostBus *host;
223 host = g_malloc0(sizeof(*host));
224 host->domain = domain;
225 host->bus = bus;
226 QLIST_INSERT_HEAD(&host_buses, host, next);
227 }
228
229 PCIBus *pci_find_root_bus(int domain)
230 {
231 struct PCIHostBus *host;
232
233 QLIST_FOREACH(host, &host_buses, next) {
234 if (host->domain == domain) {
235 return host->bus;
236 }
237 }
238
239 return NULL;
240 }
241
242 int pci_find_domain(const PCIBus *bus)
243 {
244 PCIDevice *d;
245 struct PCIHostBus *host;
246
247 /* obtain root bus */
248 while ((d = bus->parent_dev) != NULL) {
249 bus = d->bus;
250 }
251
252 QLIST_FOREACH(host, &host_buses, next) {
253 if (host->bus == bus) {
254 return host->domain;
255 }
256 }
257
258 abort(); /* should not be reached */
259 return -1;
260 }
261
262 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
263 const char *name,
264 MemoryRegion *address_space_mem,
265 MemoryRegion *address_space_io,
266 uint8_t devfn_min)
267 {
268 qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
269 assert(PCI_FUNC(devfn_min) == 0);
270 bus->devfn_min = devfn_min;
271 bus->address_space_mem = address_space_mem;
272 bus->address_space_io = address_space_io;
273
274 /* host bridge */
275 QLIST_INIT(&bus->child);
276 pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
277
278 vmstate_register(NULL, -1, &vmstate_pcibus, bus);
279 }
280
281 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
282 MemoryRegion *address_space_mem,
283 MemoryRegion *address_space_io,
284 uint8_t devfn_min)
285 {
286 PCIBus *bus;
287
288 bus = g_malloc0(sizeof(*bus));
289 bus->qbus.qdev_allocated = 1;
290 pci_bus_new_inplace(bus, parent, name, address_space_mem,
291 address_space_io, devfn_min);
292 return bus;
293 }
294
295 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
296 void *irq_opaque, int nirq)
297 {
298 bus->set_irq = set_irq;
299 bus->map_irq = map_irq;
300 bus->irq_opaque = irq_opaque;
301 bus->nirq = nirq;
302 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0]));
303 }
304
305 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
306 {
307 bus->qbus.allow_hotplug = 1;
308 bus->hotplug = hotplug;
309 bus->hotplug_qdev = qdev;
310 }
311
312 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
313 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
314 void *irq_opaque,
315 MemoryRegion *address_space_mem,
316 MemoryRegion *address_space_io,
317 uint8_t devfn_min, int nirq)
318 {
319 PCIBus *bus;
320
321 bus = pci_bus_new(parent, name, address_space_mem,
322 address_space_io, devfn_min);
323 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
324 return bus;
325 }
326
327 int pci_bus_num(PCIBus *s)
328 {
329 if (!s->parent_dev)
330 return 0; /* pci host bridge */
331 return s->parent_dev->config[PCI_SECONDARY_BUS];
332 }
333
334 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
335 {
336 PCIDevice *s = container_of(pv, PCIDevice, config);
337 uint8_t *config;
338 int i;
339
340 assert(size == pci_config_size(s));
341 config = g_malloc(size);
342
343 qemu_get_buffer(f, config, size);
344 for (i = 0; i < size; ++i) {
345 if ((config[i] ^ s->config[i]) &
346 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
347 g_free(config);
348 return -EINVAL;
349 }
350 }
351 memcpy(s->config, config, size);
352
353 pci_update_mappings(s);
354
355 g_free(config);
356 return 0;
357 }
358
359 /* just put buffer */
360 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
361 {
362 const uint8_t **v = pv;
363 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
364 qemu_put_buffer(f, *v, size);
365 }
366
367 static VMStateInfo vmstate_info_pci_config = {
368 .name = "pci config",
369 .get = get_pci_config_device,
370 .put = put_pci_config_device,
371 };
372
373 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
374 {
375 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
376 uint32_t irq_state[PCI_NUM_PINS];
377 int i;
378 for (i = 0; i < PCI_NUM_PINS; ++i) {
379 irq_state[i] = qemu_get_be32(f);
380 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
381 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
382 irq_state[i]);
383 return -EINVAL;
384 }
385 }
386
387 for (i = 0; i < PCI_NUM_PINS; ++i) {
388 pci_set_irq_state(s, i, irq_state[i]);
389 }
390
391 return 0;
392 }
393
394 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
395 {
396 int i;
397 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
398
399 for (i = 0; i < PCI_NUM_PINS; ++i) {
400 qemu_put_be32(f, pci_irq_state(s, i));
401 }
402 }
403
404 static VMStateInfo vmstate_info_pci_irq_state = {
405 .name = "pci irq state",
406 .get = get_pci_irq_state,
407 .put = put_pci_irq_state,
408 };
409
410 const VMStateDescription vmstate_pci_device = {
411 .name = "PCIDevice",
412 .version_id = 2,
413 .minimum_version_id = 1,
414 .minimum_version_id_old = 1,
415 .fields = (VMStateField []) {
416 VMSTATE_INT32_LE(version_id, PCIDevice),
417 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
418 vmstate_info_pci_config,
419 PCI_CONFIG_SPACE_SIZE),
420 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
421 vmstate_info_pci_irq_state,
422 PCI_NUM_PINS * sizeof(int32_t)),
423 VMSTATE_END_OF_LIST()
424 }
425 };
426
427 const VMStateDescription vmstate_pcie_device = {
428 .name = "PCIDevice",
429 .version_id = 2,
430 .minimum_version_id = 1,
431 .minimum_version_id_old = 1,
432 .fields = (VMStateField []) {
433 VMSTATE_INT32_LE(version_id, PCIDevice),
434 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
435 vmstate_info_pci_config,
436 PCIE_CONFIG_SPACE_SIZE),
437 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
438 vmstate_info_pci_irq_state,
439 PCI_NUM_PINS * sizeof(int32_t)),
440 VMSTATE_END_OF_LIST()
441 }
442 };
443
444 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
445 {
446 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
447 }
448
449 void pci_device_save(PCIDevice *s, QEMUFile *f)
450 {
451 /* Clear interrupt status bit: it is implicit
452 * in irq_state which we are saving.
453 * This makes us compatible with old devices
454 * which never set or clear this bit. */
455 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
456 vmstate_save_state(f, pci_get_vmstate(s), s);
457 /* Restore the interrupt status bit. */
458 pci_update_irq_status(s);
459 }
460
461 int pci_device_load(PCIDevice *s, QEMUFile *f)
462 {
463 int ret;
464 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
465 /* Restore the interrupt status bit. */
466 pci_update_irq_status(s);
467 return ret;
468 }
469
470 static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
471 {
472 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
473 pci_default_sub_vendor_id);
474 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
475 pci_default_sub_device_id);
476 }
477
478 /*
479 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
480 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
481 */
482 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
483 unsigned int *slotp, unsigned int *funcp)
484 {
485 const char *p;
486 char *e;
487 unsigned long val;
488 unsigned long dom = 0, bus = 0;
489 unsigned int slot = 0;
490 unsigned int func = 0;
491
492 p = addr;
493 val = strtoul(p, &e, 16);
494 if (e == p)
495 return -1;
496 if (*e == ':') {
497 bus = val;
498 p = e + 1;
499 val = strtoul(p, &e, 16);
500 if (e == p)
501 return -1;
502 if (*e == ':') {
503 dom = bus;
504 bus = val;
505 p = e + 1;
506 val = strtoul(p, &e, 16);
507 if (e == p)
508 return -1;
509 }
510 }
511
512 slot = val;
513
514 if (funcp != NULL) {
515 if (*e != '.')
516 return -1;
517
518 p = e + 1;
519 val = strtoul(p, &e, 16);
520 if (e == p)
521 return -1;
522
523 func = val;
524 }
525
526 /* if funcp == NULL func is 0 */
527 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
528 return -1;
529
530 if (*e)
531 return -1;
532
533 /* Note: QEMU doesn't implement domains other than 0 */
534 if (!pci_find_bus(pci_find_root_bus(dom), bus))
535 return -1;
536
537 *domp = dom;
538 *busp = bus;
539 *slotp = slot;
540 if (funcp != NULL)
541 *funcp = func;
542 return 0;
543 }
544
545 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
546 unsigned *slotp)
547 {
548 /* strip legacy tag */
549 if (!strncmp(addr, "pci_addr=", 9)) {
550 addr += 9;
551 }
552 if (pci_parse_devaddr(addr, domp, busp, slotp, NULL)) {
553 monitor_printf(mon, "Invalid pci address\n");
554 return -1;
555 }
556 return 0;
557 }
558
559 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
560 {
561 int dom, bus;
562 unsigned slot;
563
564 if (!devaddr) {
565 *devfnp = -1;
566 return pci_find_bus(pci_find_root_bus(0), 0);
567 }
568
569 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
570 return NULL;
571 }
572
573 *devfnp = PCI_DEVFN(slot, 0);
574 return pci_find_bus(pci_find_root_bus(dom), bus);
575 }
576
577 static void pci_init_cmask(PCIDevice *dev)
578 {
579 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
580 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
581 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
582 dev->cmask[PCI_REVISION_ID] = 0xff;
583 dev->cmask[PCI_CLASS_PROG] = 0xff;
584 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
585 dev->cmask[PCI_HEADER_TYPE] = 0xff;
586 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
587 }
588
589 static void pci_init_wmask(PCIDevice *dev)
590 {
591 int config_size = pci_config_size(dev);
592
593 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
594 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
595 pci_set_word(dev->wmask + PCI_COMMAND,
596 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
597 PCI_COMMAND_INTX_DISABLE);
598 if (dev->cap_present & QEMU_PCI_CAP_SERR) {
599 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
600 }
601
602 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
603 config_size - PCI_CONFIG_HEADER_SIZE);
604 }
605
606 static void pci_init_w1cmask(PCIDevice *dev)
607 {
608 /*
609 * Note: It's okay to set w1cmask even for readonly bits as
610 * long as their value is hardwired to 0.
611 */
612 pci_set_word(dev->w1cmask + PCI_STATUS,
613 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
614 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
615 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
616 }
617
618 static void pci_init_wmask_bridge(PCIDevice *d)
619 {
620 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
621 PCI_SEC_LETENCY_TIMER */
622 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
623
624 /* base and limit */
625 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
626 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
627 pci_set_word(d->wmask + PCI_MEMORY_BASE,
628 PCI_MEMORY_RANGE_MASK & 0xffff);
629 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
630 PCI_MEMORY_RANGE_MASK & 0xffff);
631 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
632 PCI_PREF_RANGE_MASK & 0xffff);
633 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
634 PCI_PREF_RANGE_MASK & 0xffff);
635
636 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
637 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
638
639 /* TODO: add this define to pci_regs.h in linux and then in qemu. */
640 #define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */
641 #define PCI_BRIDGE_CTL_DISCARD 0x100 /* Primary discard timer */
642 #define PCI_BRIDGE_CTL_SEC_DISCARD 0x200 /* Secondary discard timer */
643 #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */
644 #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */
645 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
646 PCI_BRIDGE_CTL_PARITY |
647 PCI_BRIDGE_CTL_SERR |
648 PCI_BRIDGE_CTL_ISA |
649 PCI_BRIDGE_CTL_VGA |
650 PCI_BRIDGE_CTL_VGA_16BIT |
651 PCI_BRIDGE_CTL_MASTER_ABORT |
652 PCI_BRIDGE_CTL_BUS_RESET |
653 PCI_BRIDGE_CTL_FAST_BACK |
654 PCI_BRIDGE_CTL_DISCARD |
655 PCI_BRIDGE_CTL_SEC_DISCARD |
656 PCI_BRIDGE_CTL_DISCARD_SERR);
657 /* Below does not do anything as we never set this bit, put here for
658 * completeness. */
659 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
660 PCI_BRIDGE_CTL_DISCARD_STATUS);
661 }
662
663 static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
664 {
665 uint8_t slot = PCI_SLOT(dev->devfn);
666 uint8_t func;
667
668 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
669 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
670 }
671
672 /*
673 * multifunction bit is interpreted in two ways as follows.
674 * - all functions must set the bit to 1.
675 * Example: Intel X53
676 * - function 0 must set the bit, but the rest function (> 0)
677 * is allowed to leave the bit to 0.
678 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
679 *
680 * So OS (at least Linux) checks the bit of only function 0,
681 * and doesn't see the bit of function > 0.
682 *
683 * The below check allows both interpretation.
684 */
685 if (PCI_FUNC(dev->devfn)) {
686 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
687 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
688 /* function 0 should set multifunction bit */
689 error_report("PCI: single function device can't be populated "
690 "in function %x.%x", slot, PCI_FUNC(dev->devfn));
691 return -1;
692 }
693 return 0;
694 }
695
696 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
697 return 0;
698 }
699 /* function 0 indicates single function, so function > 0 must be NULL */
700 for (func = 1; func < PCI_FUNC_MAX; ++func) {
701 if (bus->devices[PCI_DEVFN(slot, func)]) {
702 error_report("PCI: %x.0 indicates single function, "
703 "but %x.%x is already populated.",
704 slot, slot, func);
705 return -1;
706 }
707 }
708 return 0;
709 }
710
711 static void pci_config_alloc(PCIDevice *pci_dev)
712 {
713 int config_size = pci_config_size(pci_dev);
714
715 pci_dev->config = g_malloc0(config_size);
716 pci_dev->cmask = g_malloc0(config_size);
717 pci_dev->wmask = g_malloc0(config_size);
718 pci_dev->w1cmask = g_malloc0(config_size);
719 pci_dev->used = g_malloc0(config_size);
720 }
721
722 static void pci_config_free(PCIDevice *pci_dev)
723 {
724 g_free(pci_dev->config);
725 g_free(pci_dev->cmask);
726 g_free(pci_dev->wmask);
727 g_free(pci_dev->w1cmask);
728 g_free(pci_dev->used);
729 }
730
731 /* -1 for devfn means auto assign */
732 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
733 const char *name, int devfn,
734 const PCIDeviceInfo *info)
735 {
736 PCIConfigReadFunc *config_read = info->config_read;
737 PCIConfigWriteFunc *config_write = info->config_write;
738
739 if (devfn < 0) {
740 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
741 devfn += PCI_FUNC_MAX) {
742 if (!bus->devices[devfn])
743 goto found;
744 }
745 error_report("PCI: no slot/function available for %s, all in use", name);
746 return NULL;
747 found: ;
748 } else if (bus->devices[devfn]) {
749 error_report("PCI: slot %d function %d not available for %s, in use by %s",
750 PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
751 return NULL;
752 }
753 pci_dev->bus = bus;
754 pci_dev->devfn = devfn;
755 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
756 pci_dev->irq_state = 0;
757 pci_config_alloc(pci_dev);
758
759 pci_config_set_vendor_id(pci_dev->config, info->vendor_id);
760 pci_config_set_device_id(pci_dev->config, info->device_id);
761 pci_config_set_revision(pci_dev->config, info->revision);
762 pci_config_set_class(pci_dev->config, info->class_id);
763
764 if (!info->is_bridge) {
765 if (info->subsystem_vendor_id || info->subsystem_id) {
766 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
767 info->subsystem_vendor_id);
768 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
769 info->subsystem_id);
770 } else {
771 pci_set_default_subsystem_id(pci_dev);
772 }
773 } else {
774 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
775 assert(!info->subsystem_vendor_id);
776 assert(!info->subsystem_id);
777 }
778 pci_init_cmask(pci_dev);
779 pci_init_wmask(pci_dev);
780 pci_init_w1cmask(pci_dev);
781 if (info->is_bridge) {
782 pci_init_wmask_bridge(pci_dev);
783 }
784 if (pci_init_multifunction(bus, pci_dev)) {
785 pci_config_free(pci_dev);
786 return NULL;
787 }
788
789 if (!config_read)
790 config_read = pci_default_read_config;
791 if (!config_write)
792 config_write = pci_default_write_config;
793 pci_dev->config_read = config_read;
794 pci_dev->config_write = config_write;
795 bus->devices[devfn] = pci_dev;
796 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
797 pci_dev->version_id = 2; /* Current pci device vmstate version */
798 return pci_dev;
799 }
800
801 static void do_pci_unregister_device(PCIDevice *pci_dev)
802 {
803 qemu_free_irqs(pci_dev->irq);
804 pci_dev->bus->devices[pci_dev->devfn] = NULL;
805 pci_config_free(pci_dev);
806 }
807
808 /* TODO: obsolete. eliminate this once all pci devices are qdevifed. */
809 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
810 int instance_size, int devfn,
811 PCIConfigReadFunc *config_read,
812 PCIConfigWriteFunc *config_write)
813 {
814 PCIDevice *pci_dev;
815 PCIDeviceInfo info = {
816 .config_read = config_read,
817 .config_write = config_write,
818 };
819
820 pci_dev = g_malloc0(instance_size);
821 pci_dev = do_pci_register_device(pci_dev, bus, name, devfn, &info);
822 if (pci_dev == NULL) {
823 hw_error("PCI: can't register device\n");
824 }
825 return pci_dev;
826 }
827
828 static void pci_unregister_io_regions(PCIDevice *pci_dev)
829 {
830 PCIIORegion *r;
831 int i;
832
833 for(i = 0; i < PCI_NUM_REGIONS; i++) {
834 r = &pci_dev->io_regions[i];
835 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
836 continue;
837 memory_region_del_subregion(r->address_space, r->memory);
838 }
839 }
840
841 static int pci_unregister_device(DeviceState *dev)
842 {
843 PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
844 PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, qdev_get_info(dev));
845 int ret = 0;
846
847 if (info->exit)
848 ret = info->exit(pci_dev);
849 if (ret)
850 return ret;
851
852 pci_unregister_io_regions(pci_dev);
853 pci_del_option_rom(pci_dev);
854 g_free(pci_dev->romfile);
855 do_pci_unregister_device(pci_dev);
856 return 0;
857 }
858
859 void pci_register_bar(PCIDevice *pci_dev, int region_num,
860 uint8_t type, MemoryRegion *memory)
861 {
862 PCIIORegion *r;
863 uint32_t addr;
864 uint64_t wmask;
865 pcibus_t size = memory_region_size(memory);
866
867 assert(region_num >= 0);
868 assert(region_num < PCI_NUM_REGIONS);
869 if (size & (size-1)) {
870 fprintf(stderr, "ERROR: PCI region size must be pow2 "
871 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
872 exit(1);
873 }
874
875 r = &pci_dev->io_regions[region_num];
876 r->addr = PCI_BAR_UNMAPPED;
877 r->size = size;
878 r->type = type;
879 r->memory = NULL;
880
881 wmask = ~(size - 1);
882 addr = pci_bar(pci_dev, region_num);
883 if (region_num == PCI_ROM_SLOT) {
884 /* ROM enable bit is writable */
885 wmask |= PCI_ROM_ADDRESS_ENABLE;
886 }
887 pci_set_long(pci_dev->config + addr, type);
888 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
889 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
890 pci_set_quad(pci_dev->wmask + addr, wmask);
891 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
892 } else {
893 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
894 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
895 }
896 pci_dev->io_regions[region_num].memory = memory;
897 pci_dev->io_regions[region_num].address_space
898 = type & PCI_BASE_ADDRESS_SPACE_IO
899 ? pci_dev->bus->address_space_io
900 : pci_dev->bus->address_space_mem;
901 }
902
903 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
904 {
905 return pci_dev->io_regions[region_num].addr;
906 }
907
908 static pcibus_t pci_bar_address(PCIDevice *d,
909 int reg, uint8_t type, pcibus_t size)
910 {
911 pcibus_t new_addr, last_addr;
912 int bar = pci_bar(d, reg);
913 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
914
915 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
916 if (!(cmd & PCI_COMMAND_IO)) {
917 return PCI_BAR_UNMAPPED;
918 }
919 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
920 last_addr = new_addr + size - 1;
921 /* NOTE: we have only 64K ioports on PC */
922 if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
923 return PCI_BAR_UNMAPPED;
924 }
925 return new_addr;
926 }
927
928 if (!(cmd & PCI_COMMAND_MEMORY)) {
929 return PCI_BAR_UNMAPPED;
930 }
931 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
932 new_addr = pci_get_quad(d->config + bar);
933 } else {
934 new_addr = pci_get_long(d->config + bar);
935 }
936 /* the ROM slot has a specific enable bit */
937 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
938 return PCI_BAR_UNMAPPED;
939 }
940 new_addr &= ~(size - 1);
941 last_addr = new_addr + size - 1;
942 /* NOTE: we do not support wrapping */
943 /* XXX: as we cannot support really dynamic
944 mappings, we handle specific values as invalid
945 mappings. */
946 if (last_addr <= new_addr || new_addr == 0 ||
947 last_addr == PCI_BAR_UNMAPPED) {
948 return PCI_BAR_UNMAPPED;
949 }
950
951 /* Now pcibus_t is 64bit.
952 * Check if 32 bit BAR wraps around explicitly.
953 * Without this, PC ide doesn't work well.
954 * TODO: remove this work around.
955 */
956 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
957 return PCI_BAR_UNMAPPED;
958 }
959
960 /*
961 * OS is allowed to set BAR beyond its addressable
962 * bits. For example, 32 bit OS can set 64bit bar
963 * to >4G. Check it. TODO: we might need to support
964 * it in the future for e.g. PAE.
965 */
966 if (last_addr >= TARGET_PHYS_ADDR_MAX) {
967 return PCI_BAR_UNMAPPED;
968 }
969
970 return new_addr;
971 }
972
973 static void pci_update_mappings(PCIDevice *d)
974 {
975 PCIIORegion *r;
976 int i;
977 pcibus_t new_addr;
978
979 for(i = 0; i < PCI_NUM_REGIONS; i++) {
980 r = &d->io_regions[i];
981
982 /* this region isn't registered */
983 if (!r->size)
984 continue;
985
986 new_addr = pci_bar_address(d, i, r->type, r->size);
987
988 /* This bar isn't changed */
989 if (new_addr == r->addr)
990 continue;
991
992 /* now do the real mapping */
993 if (r->addr != PCI_BAR_UNMAPPED) {
994 memory_region_del_subregion(r->address_space, r->memory);
995 }
996 r->addr = new_addr;
997 if (r->addr != PCI_BAR_UNMAPPED) {
998 memory_region_add_subregion_overlap(r->address_space,
999 r->addr, r->memory, 1);
1000 }
1001 }
1002 }
1003
1004 static inline int pci_irq_disabled(PCIDevice *d)
1005 {
1006 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1007 }
1008
1009 /* Called after interrupt disabled field update in config space,
1010 * assert/deassert interrupts if necessary.
1011 * Gets original interrupt disable bit value (before update). */
1012 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1013 {
1014 int i, disabled = pci_irq_disabled(d);
1015 if (disabled == was_irq_disabled)
1016 return;
1017 for (i = 0; i < PCI_NUM_PINS; ++i) {
1018 int state = pci_irq_state(d, i);
1019 pci_change_irq_level(d, i, disabled ? -state : state);
1020 }
1021 }
1022
1023 uint32_t pci_default_read_config(PCIDevice *d,
1024 uint32_t address, int len)
1025 {
1026 uint32_t val = 0;
1027
1028 memcpy(&val, d->config + address, len);
1029 return le32_to_cpu(val);
1030 }
1031
1032 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
1033 {
1034 int i, was_irq_disabled = pci_irq_disabled(d);
1035
1036 for (i = 0; i < l; val >>= 8, ++i) {
1037 uint8_t wmask = d->wmask[addr + i];
1038 uint8_t w1cmask = d->w1cmask[addr + i];
1039 assert(!(wmask & w1cmask));
1040 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1041 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
1042 }
1043 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1044 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1045 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1046 range_covers_byte(addr, l, PCI_COMMAND))
1047 pci_update_mappings(d);
1048
1049 if (range_covers_byte(addr, l, PCI_COMMAND))
1050 pci_update_irq_disabled(d, was_irq_disabled);
1051 }
1052
1053 /***********************************************************/
1054 /* generic PCI irq support */
1055
1056 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1057 static void pci_set_irq(void *opaque, int irq_num, int level)
1058 {
1059 PCIDevice *pci_dev = opaque;
1060 int change;
1061
1062 change = level - pci_irq_state(pci_dev, irq_num);
1063 if (!change)
1064 return;
1065
1066 pci_set_irq_state(pci_dev, irq_num, level);
1067 pci_update_irq_status(pci_dev);
1068 if (pci_irq_disabled(pci_dev))
1069 return;
1070 pci_change_irq_level(pci_dev, irq_num, change);
1071 }
1072
1073 /***********************************************************/
1074 /* monitor info on PCI */
1075
1076 typedef struct {
1077 uint16_t class;
1078 const char *desc;
1079 const char *fw_name;
1080 uint16_t fw_ign_bits;
1081 } pci_class_desc;
1082
1083 static const pci_class_desc pci_class_descriptions[] =
1084 {
1085 { 0x0001, "VGA controller", "display"},
1086 { 0x0100, "SCSI controller", "scsi"},
1087 { 0x0101, "IDE controller", "ide"},
1088 { 0x0102, "Floppy controller", "fdc"},
1089 { 0x0103, "IPI controller", "ipi"},
1090 { 0x0104, "RAID controller", "raid"},
1091 { 0x0106, "SATA controller"},
1092 { 0x0107, "SAS controller"},
1093 { 0x0180, "Storage controller"},
1094 { 0x0200, "Ethernet controller", "ethernet"},
1095 { 0x0201, "Token Ring controller", "token-ring"},
1096 { 0x0202, "FDDI controller", "fddi"},
1097 { 0x0203, "ATM controller", "atm"},
1098 { 0x0280, "Network controller"},
1099 { 0x0300, "VGA controller", "display", 0x00ff},
1100 { 0x0301, "XGA controller"},
1101 { 0x0302, "3D controller"},
1102 { 0x0380, "Display controller"},
1103 { 0x0400, "Video controller", "video"},
1104 { 0x0401, "Audio controller", "sound"},
1105 { 0x0402, "Phone"},
1106 { 0x0403, "Audio controller", "sound"},
1107 { 0x0480, "Multimedia controller"},
1108 { 0x0500, "RAM controller", "memory"},
1109 { 0x0501, "Flash controller", "flash"},
1110 { 0x0580, "Memory controller"},
1111 { 0x0600, "Host bridge", "host"},
1112 { 0x0601, "ISA bridge", "isa"},
1113 { 0x0602, "EISA bridge", "eisa"},
1114 { 0x0603, "MC bridge", "mca"},
1115 { 0x0604, "PCI bridge", "pci"},
1116 { 0x0605, "PCMCIA bridge", "pcmcia"},
1117 { 0x0606, "NUBUS bridge", "nubus"},
1118 { 0x0607, "CARDBUS bridge", "cardbus"},
1119 { 0x0608, "RACEWAY bridge"},
1120 { 0x0680, "Bridge"},
1121 { 0x0700, "Serial port", "serial"},
1122 { 0x0701, "Parallel port", "parallel"},
1123 { 0x0800, "Interrupt controller", "interrupt-controller"},
1124 { 0x0801, "DMA controller", "dma-controller"},
1125 { 0x0802, "Timer", "timer"},
1126 { 0x0803, "RTC", "rtc"},
1127 { 0x0900, "Keyboard", "keyboard"},
1128 { 0x0901, "Pen", "pen"},
1129 { 0x0902, "Mouse", "mouse"},
1130 { 0x0A00, "Dock station", "dock", 0x00ff},
1131 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1132 { 0x0c00, "Fireware contorller", "fireware"},
1133 { 0x0c01, "Access bus controller", "access-bus"},
1134 { 0x0c02, "SSA controller", "ssa"},
1135 { 0x0c03, "USB controller", "usb"},
1136 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1137 { 0, NULL}
1138 };
1139
1140 static void pci_for_each_device_under_bus(PCIBus *bus,
1141 void (*fn)(PCIBus *b, PCIDevice *d))
1142 {
1143 PCIDevice *d;
1144 int devfn;
1145
1146 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1147 d = bus->devices[devfn];
1148 if (d) {
1149 fn(bus, d);
1150 }
1151 }
1152 }
1153
1154 void pci_for_each_device(PCIBus *bus, int bus_num,
1155 void (*fn)(PCIBus *b, PCIDevice *d))
1156 {
1157 bus = pci_find_bus(bus, bus_num);
1158
1159 if (bus) {
1160 pci_for_each_device_under_bus(bus, fn);
1161 }
1162 }
1163
1164 static const pci_class_desc *get_class_desc(int class)
1165 {
1166 const pci_class_desc *desc;
1167
1168 desc = pci_class_descriptions;
1169 while (desc->desc && class != desc->class) {
1170 desc++;
1171 }
1172
1173 return desc;
1174 }
1175
1176 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num);
1177
1178 static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev)
1179 {
1180 PciMemoryRegionList *head = NULL, *cur_item = NULL;
1181 int i;
1182
1183 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1184 const PCIIORegion *r = &dev->io_regions[i];
1185 PciMemoryRegionList *region;
1186
1187 if (!r->size) {
1188 continue;
1189 }
1190
1191 region = g_malloc0(sizeof(*region));
1192 region->value = g_malloc0(sizeof(*region->value));
1193
1194 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1195 region->value->type = g_strdup("io");
1196 } else {
1197 region->value->type = g_strdup("memory");
1198 region->value->has_prefetch = true;
1199 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH);
1200 region->value->has_mem_type_64 = true;
1201 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
1202 }
1203
1204 region->value->bar = i;
1205 region->value->address = r->addr;
1206 region->value->size = r->size;
1207
1208 /* XXX: waiting for the qapi to support GSList */
1209 if (!cur_item) {
1210 head = cur_item = region;
1211 } else {
1212 cur_item->next = region;
1213 cur_item = region;
1214 }
1215 }
1216
1217 return head;
1218 }
1219
1220 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus,
1221 int bus_num)
1222 {
1223 PciBridgeInfo *info;
1224
1225 info = g_malloc0(sizeof(*info));
1226
1227 info->bus.number = dev->config[PCI_PRIMARY_BUS];
1228 info->bus.secondary = dev->config[PCI_SECONDARY_BUS];
1229 info->bus.subordinate = dev->config[PCI_SUBORDINATE_BUS];
1230
1231 info->bus.io_range = g_malloc0(sizeof(*info->bus.io_range));
1232 info->bus.io_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
1233 info->bus.io_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
1234
1235 info->bus.memory_range = g_malloc0(sizeof(*info->bus.memory_range));
1236 info->bus.memory_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1237 info->bus.memory_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1238
1239 info->bus.prefetchable_range = g_malloc0(sizeof(*info->bus.prefetchable_range));
1240 info->bus.prefetchable_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1241 info->bus.prefetchable_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1242
1243 if (dev->config[PCI_SECONDARY_BUS] != 0) {
1244 PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]);
1245 if (child_bus) {
1246 info->has_devices = true;
1247 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]);
1248 }
1249 }
1250
1251 return info;
1252 }
1253
1254 static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus,
1255 int bus_num)
1256 {
1257 const pci_class_desc *desc;
1258 PciDeviceInfo *info;
1259 uint8_t type;
1260 int class;
1261
1262 info = g_malloc0(sizeof(*info));
1263 info->bus = bus_num;
1264 info->slot = PCI_SLOT(dev->devfn);
1265 info->function = PCI_FUNC(dev->devfn);
1266
1267 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1268 info->class_info.class = class;
1269 desc = get_class_desc(class);
1270 if (desc->desc) {
1271 info->class_info.has_desc = true;
1272 info->class_info.desc = g_strdup(desc->desc);
1273 }
1274
1275 info->id.vendor = pci_get_word(dev->config + PCI_VENDOR_ID);
1276 info->id.device = pci_get_word(dev->config + PCI_DEVICE_ID);
1277 info->regions = qmp_query_pci_regions(dev);
1278 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : "");
1279
1280 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1281 info->has_irq = true;
1282 info->irq = dev->config[PCI_INTERRUPT_LINE];
1283 }
1284
1285 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1286 if (type == PCI_HEADER_TYPE_BRIDGE) {
1287 info->has_pci_bridge = true;
1288 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num);
1289 }
1290
1291 return info;
1292 }
1293
1294 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num)
1295 {
1296 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL;
1297 PCIDevice *dev;
1298 int devfn;
1299
1300 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1301 dev = bus->devices[devfn];
1302 if (dev) {
1303 info = g_malloc0(sizeof(*info));
1304 info->value = qmp_query_pci_device(dev, bus, bus_num);
1305
1306 /* XXX: waiting for the qapi to support GSList */
1307 if (!cur_item) {
1308 head = cur_item = info;
1309 } else {
1310 cur_item->next = info;
1311 cur_item = info;
1312 }
1313 }
1314 }
1315
1316 return head;
1317 }
1318
1319 static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num)
1320 {
1321 PciInfo *info = NULL;
1322
1323 bus = pci_find_bus(bus, bus_num);
1324 if (bus) {
1325 info = g_malloc0(sizeof(*info));
1326 info->bus = bus_num;
1327 info->devices = qmp_query_pci_devices(bus, bus_num);
1328 }
1329
1330 return info;
1331 }
1332
1333 PciInfoList *qmp_query_pci(Error **errp)
1334 {
1335 PciInfoList *info, *head = NULL, *cur_item = NULL;
1336 struct PCIHostBus *host;
1337
1338 QLIST_FOREACH(host, &host_buses, next) {
1339 info = g_malloc0(sizeof(*info));
1340 info->value = qmp_query_pci_bus(host->bus, 0);
1341
1342 /* XXX: waiting for the qapi to support GSList */
1343 if (!cur_item) {
1344 head = cur_item = info;
1345 } else {
1346 cur_item->next = info;
1347 cur_item = info;
1348 }
1349 }
1350
1351 return head;
1352 }
1353
1354 static const char * const pci_nic_models[] = {
1355 "ne2k_pci",
1356 "i82551",
1357 "i82557b",
1358 "i82559er",
1359 "rtl8139",
1360 "e1000",
1361 "pcnet",
1362 "virtio",
1363 NULL
1364 };
1365
1366 static const char * const pci_nic_names[] = {
1367 "ne2k_pci",
1368 "i82551",
1369 "i82557b",
1370 "i82559er",
1371 "rtl8139",
1372 "e1000",
1373 "pcnet",
1374 "virtio-net-pci",
1375 NULL
1376 };
1377
1378 /* Initialize a PCI NIC. */
1379 /* FIXME callers should check for failure, but don't */
1380 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1381 const char *default_devaddr)
1382 {
1383 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1384 PCIBus *bus;
1385 int devfn;
1386 PCIDevice *pci_dev;
1387 DeviceState *dev;
1388 int i;
1389
1390 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1391 if (i < 0)
1392 return NULL;
1393
1394 bus = pci_get_bus_devfn(&devfn, devaddr);
1395 if (!bus) {
1396 error_report("Invalid PCI device address %s for device %s",
1397 devaddr, pci_nic_names[i]);
1398 return NULL;
1399 }
1400
1401 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1402 dev = &pci_dev->qdev;
1403 qdev_set_nic_properties(dev, nd);
1404 if (qdev_init(dev) < 0)
1405 return NULL;
1406 return pci_dev;
1407 }
1408
1409 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1410 const char *default_devaddr)
1411 {
1412 PCIDevice *res;
1413
1414 if (qemu_show_nic_models(nd->model, pci_nic_models))
1415 exit(0);
1416
1417 res = pci_nic_init(nd, default_model, default_devaddr);
1418 if (!res)
1419 exit(1);
1420 return res;
1421 }
1422
1423 /* Whether a given bus number is in range of the secondary
1424 * bus of the given bridge device. */
1425 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1426 {
1427 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1428 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
1429 dev->config[PCI_SECONDARY_BUS] < bus_num &&
1430 bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1431 }
1432
1433 PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1434 {
1435 PCIBus *sec;
1436
1437 if (!bus) {
1438 return NULL;
1439 }
1440
1441 if (pci_bus_num(bus) == bus_num) {
1442 return bus;
1443 }
1444
1445 /* Consider all bus numbers in range for the host pci bridge. */
1446 if (bus->parent_dev &&
1447 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
1448 return NULL;
1449 }
1450
1451 /* try child bus */
1452 for (; bus; bus = sec) {
1453 QLIST_FOREACH(sec, &bus->child, sibling) {
1454 assert(sec->parent_dev);
1455 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
1456 return sec;
1457 }
1458 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
1459 break;
1460 }
1461 }
1462 }
1463
1464 return NULL;
1465 }
1466
1467 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
1468 {
1469 bus = pci_find_bus(bus, bus_num);
1470
1471 if (!bus)
1472 return NULL;
1473
1474 return bus->devices[devfn];
1475 }
1476
1477 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1478 {
1479 PCIDevice *pci_dev = (PCIDevice *)qdev;
1480 PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1481 PCIBus *bus;
1482 int rc;
1483 bool is_default_rom;
1484
1485 /* initialize cap_present for pci_is_express() and pci_config_size() */
1486 if (info->is_express) {
1487 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1488 }
1489
1490 bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1491 pci_dev = do_pci_register_device(pci_dev, bus, base->name,
1492 pci_dev->devfn, info);
1493 if (pci_dev == NULL)
1494 return -1;
1495 if (qdev->hotplugged && info->no_hotplug) {
1496 qerror_report(QERR_DEVICE_NO_HOTPLUG, object_get_typename(OBJECT(pci_dev)));
1497 do_pci_unregister_device(pci_dev);
1498 return -1;
1499 }
1500 if (info->init) {
1501 rc = info->init(pci_dev);
1502 if (rc != 0) {
1503 do_pci_unregister_device(pci_dev);
1504 return rc;
1505 }
1506 }
1507
1508 /* rom loading */
1509 is_default_rom = false;
1510 if (pci_dev->romfile == NULL && info->romfile != NULL) {
1511 pci_dev->romfile = g_strdup(info->romfile);
1512 is_default_rom = true;
1513 }
1514 pci_add_option_rom(pci_dev, is_default_rom);
1515
1516 if (bus->hotplug) {
1517 /* Let buses differentiate between hotplug and when device is
1518 * enabled during qemu machine creation. */
1519 rc = bus->hotplug(bus->hotplug_qdev, pci_dev,
1520 qdev->hotplugged ? PCI_HOTPLUG_ENABLED:
1521 PCI_COLDPLUG_ENABLED);
1522 if (rc != 0) {
1523 int r = pci_unregister_device(&pci_dev->qdev);
1524 assert(!r);
1525 return rc;
1526 }
1527 }
1528 return 0;
1529 }
1530
1531 static int pci_unplug_device(DeviceState *qdev)
1532 {
1533 PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1534 PCIDeviceInfo *info = container_of(qdev_get_info(qdev), PCIDeviceInfo, qdev);
1535
1536 if (info->no_hotplug) {
1537 qerror_report(QERR_DEVICE_NO_HOTPLUG, object_get_typename(OBJECT(dev)));
1538 return -1;
1539 }
1540 return dev->bus->hotplug(dev->bus->hotplug_qdev, dev,
1541 PCI_HOTPLUG_DISABLED);
1542 }
1543
1544 void pci_qdev_register(PCIDeviceInfo *info)
1545 {
1546 info->qdev.init = pci_qdev_init;
1547 if (!info->qdev.unplug) {
1548 info->qdev.unplug = pci_unplug_device;
1549 }
1550 info->qdev.exit = pci_unregister_device;
1551 info->qdev.bus_info = &pci_bus_info;
1552 qdev_register(&info->qdev);
1553 }
1554
1555 void pci_qdev_register_many(PCIDeviceInfo *info)
1556 {
1557 while (info->qdev.name) {
1558 pci_qdev_register(info);
1559 info++;
1560 }
1561 }
1562
1563 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
1564 const char *name)
1565 {
1566 DeviceState *dev;
1567
1568 dev = qdev_create(&bus->qbus, name);
1569 qdev_prop_set_uint32(dev, "addr", devfn);
1570 qdev_prop_set_bit(dev, "multifunction", multifunction);
1571 return DO_UPCAST(PCIDevice, qdev, dev);
1572 }
1573
1574 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
1575 bool multifunction,
1576 const char *name)
1577 {
1578 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
1579 qdev_init_nofail(&dev->qdev);
1580 return dev;
1581 }
1582
1583 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1584 {
1585 return pci_create_multifunction(bus, devfn, false, name);
1586 }
1587
1588 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1589 {
1590 return pci_create_simple_multifunction(bus, devfn, false, name);
1591 }
1592
1593 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1594 {
1595 int config_size = pci_config_size(pdev);
1596 int offset = PCI_CONFIG_HEADER_SIZE;
1597 int i;
1598 for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1599 if (pdev->used[i])
1600 offset = i + 1;
1601 else if (i - offset + 1 == size)
1602 return offset;
1603 return 0;
1604 }
1605
1606 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1607 uint8_t *prev_p)
1608 {
1609 uint8_t next, prev;
1610
1611 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1612 return 0;
1613
1614 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1615 prev = next + PCI_CAP_LIST_NEXT)
1616 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1617 break;
1618
1619 if (prev_p)
1620 *prev_p = prev;
1621 return next;
1622 }
1623
1624 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset)
1625 {
1626 uint8_t next, prev, found = 0;
1627
1628 if (!(pdev->used[offset])) {
1629 return 0;
1630 }
1631
1632 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST);
1633
1634 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1635 prev = next + PCI_CAP_LIST_NEXT) {
1636 if (next <= offset && next > found) {
1637 found = next;
1638 }
1639 }
1640 return found;
1641 }
1642
1643 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
1644 This is needed for an option rom which is used for more than one device. */
1645 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
1646 {
1647 uint16_t vendor_id;
1648 uint16_t device_id;
1649 uint16_t rom_vendor_id;
1650 uint16_t rom_device_id;
1651 uint16_t rom_magic;
1652 uint16_t pcir_offset;
1653 uint8_t checksum;
1654
1655 /* Words in rom data are little endian (like in PCI configuration),
1656 so they can be read / written with pci_get_word / pci_set_word. */
1657
1658 /* Only a valid rom will be patched. */
1659 rom_magic = pci_get_word(ptr);
1660 if (rom_magic != 0xaa55) {
1661 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
1662 return;
1663 }
1664 pcir_offset = pci_get_word(ptr + 0x18);
1665 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
1666 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
1667 return;
1668 }
1669
1670 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
1671 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
1672 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
1673 rom_device_id = pci_get_word(ptr + pcir_offset + 6);
1674
1675 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
1676 vendor_id, device_id, rom_vendor_id, rom_device_id);
1677
1678 checksum = ptr[6];
1679
1680 if (vendor_id != rom_vendor_id) {
1681 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
1682 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
1683 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
1684 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1685 ptr[6] = checksum;
1686 pci_set_word(ptr + pcir_offset + 4, vendor_id);
1687 }
1688
1689 if (device_id != rom_device_id) {
1690 /* Patch device id and checksum (at offset 6 for etherboot roms). */
1691 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
1692 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
1693 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1694 ptr[6] = checksum;
1695 pci_set_word(ptr + pcir_offset + 6, device_id);
1696 }
1697 }
1698
1699 /* Add an option rom for the device */
1700 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom)
1701 {
1702 int size;
1703 char *path;
1704 void *ptr;
1705 char name[32];
1706
1707 if (!pdev->romfile)
1708 return 0;
1709 if (strlen(pdev->romfile) == 0)
1710 return 0;
1711
1712 if (!pdev->rom_bar) {
1713 /*
1714 * Load rom via fw_cfg instead of creating a rom bar,
1715 * for 0.11 compatibility.
1716 */
1717 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
1718 if (class == 0x0300) {
1719 rom_add_vga(pdev->romfile);
1720 } else {
1721 rom_add_option(pdev->romfile, -1);
1722 }
1723 return 0;
1724 }
1725
1726 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
1727 if (path == NULL) {
1728 path = g_strdup(pdev->romfile);
1729 }
1730
1731 size = get_image_size(path);
1732 if (size < 0) {
1733 error_report("%s: failed to find romfile \"%s\"",
1734 __FUNCTION__, pdev->romfile);
1735 g_free(path);
1736 return -1;
1737 }
1738 if (size & (size - 1)) {
1739 size = 1 << qemu_fls(size);
1740 }
1741
1742 if (qdev_get_info(&pdev->qdev)->vmsd)
1743 snprintf(name, sizeof(name), "%s.rom", qdev_get_info(&pdev->qdev)->vmsd->name);
1744 else
1745 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev)));
1746 pdev->has_rom = true;
1747 memory_region_init_ram(&pdev->rom, name, size);
1748 vmstate_register_ram(&pdev->rom, &pdev->qdev);
1749 ptr = memory_region_get_ram_ptr(&pdev->rom);
1750 load_image(path, ptr);
1751 g_free(path);
1752
1753 if (is_default_rom) {
1754 /* Only the default rom images will be patched (if needed). */
1755 pci_patch_ids(pdev, ptr, size);
1756 }
1757
1758 qemu_put_ram_ptr(ptr);
1759
1760 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
1761
1762 return 0;
1763 }
1764
1765 static void pci_del_option_rom(PCIDevice *pdev)
1766 {
1767 if (!pdev->has_rom)
1768 return;
1769
1770 vmstate_unregister_ram(&pdev->rom, &pdev->qdev);
1771 memory_region_destroy(&pdev->rom);
1772 pdev->has_rom = false;
1773 }
1774
1775 /*
1776 * if !offset
1777 * Reserve space and add capability to the linked list in pci config space
1778 *
1779 * if offset = 0,
1780 * Find and reserve space and add capability to the linked list
1781 * in pci config space */
1782 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
1783 uint8_t offset, uint8_t size)
1784 {
1785 uint8_t *config;
1786 int i, overlapping_cap;
1787
1788 if (!offset) {
1789 offset = pci_find_space(pdev, size);
1790 if (!offset) {
1791 return -ENOSPC;
1792 }
1793 } else {
1794 /* Verify that capabilities don't overlap. Note: device assignment
1795 * depends on this check to verify that the device is not broken.
1796 * Should never trigger for emulated devices, but it's helpful
1797 * for debugging these. */
1798 for (i = offset; i < offset + size; i++) {
1799 overlapping_cap = pci_find_capability_at_offset(pdev, i);
1800 if (overlapping_cap) {
1801 fprintf(stderr, "ERROR: %04x:%02x:%02x.%x "
1802 "Attempt to add PCI capability %x at offset "
1803 "%x overlaps existing capability %x at offset %x\n",
1804 pci_find_domain(pdev->bus), pci_bus_num(pdev->bus),
1805 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1806 cap_id, offset, overlapping_cap, i);
1807 return -EINVAL;
1808 }
1809 }
1810 }
1811
1812 config = pdev->config + offset;
1813 config[PCI_CAP_LIST_ID] = cap_id;
1814 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1815 pdev->config[PCI_CAPABILITY_LIST] = offset;
1816 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1817 memset(pdev->used + offset, 0xFF, size);
1818 /* Make capability read-only by default */
1819 memset(pdev->wmask + offset, 0, size);
1820 /* Check capability by default */
1821 memset(pdev->cmask + offset, 0xFF, size);
1822 return offset;
1823 }
1824
1825 /* Unlink capability from the pci config space. */
1826 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1827 {
1828 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1829 if (!offset)
1830 return;
1831 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1832 /* Make capability writable again */
1833 memset(pdev->wmask + offset, 0xff, size);
1834 memset(pdev->w1cmask + offset, 0, size);
1835 /* Clear cmask as device-specific registers can't be checked */
1836 memset(pdev->cmask + offset, 0, size);
1837 memset(pdev->used + offset, 0, size);
1838
1839 if (!pdev->config[PCI_CAPABILITY_LIST])
1840 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1841 }
1842
1843 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1844 {
1845 return pci_find_capability_list(pdev, cap_id, NULL);
1846 }
1847
1848 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1849 {
1850 PCIDevice *d = (PCIDevice *)dev;
1851 const pci_class_desc *desc;
1852 char ctxt[64];
1853 PCIIORegion *r;
1854 int i, class;
1855
1856 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1857 desc = pci_class_descriptions;
1858 while (desc->desc && class != desc->class)
1859 desc++;
1860 if (desc->desc) {
1861 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1862 } else {
1863 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1864 }
1865
1866 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1867 "pci id %04x:%04x (sub %04x:%04x)\n",
1868 indent, "", ctxt, pci_bus_num(d->bus),
1869 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
1870 pci_get_word(d->config + PCI_VENDOR_ID),
1871 pci_get_word(d->config + PCI_DEVICE_ID),
1872 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
1873 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
1874 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1875 r = &d->io_regions[i];
1876 if (!r->size)
1877 continue;
1878 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1879 " [0x%"FMT_PCIBUS"]\n",
1880 indent, "",
1881 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
1882 r->addr, r->addr + r->size - 1);
1883 }
1884 }
1885
1886 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
1887 {
1888 PCIDevice *d = (PCIDevice *)dev;
1889 const char *name = NULL;
1890 const pci_class_desc *desc = pci_class_descriptions;
1891 int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1892
1893 while (desc->desc &&
1894 (class & ~desc->fw_ign_bits) !=
1895 (desc->class & ~desc->fw_ign_bits)) {
1896 desc++;
1897 }
1898
1899 if (desc->desc) {
1900 name = desc->fw_name;
1901 }
1902
1903 if (name) {
1904 pstrcpy(buf, len, name);
1905 } else {
1906 snprintf(buf, len, "pci%04x,%04x",
1907 pci_get_word(d->config + PCI_VENDOR_ID),
1908 pci_get_word(d->config + PCI_DEVICE_ID));
1909 }
1910
1911 return buf;
1912 }
1913
1914 static char *pcibus_get_fw_dev_path(DeviceState *dev)
1915 {
1916 PCIDevice *d = (PCIDevice *)dev;
1917 char path[50], name[33];
1918 int off;
1919
1920 off = snprintf(path, sizeof(path), "%s@%x",
1921 pci_dev_fw_name(dev, name, sizeof name),
1922 PCI_SLOT(d->devfn));
1923 if (PCI_FUNC(d->devfn))
1924 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
1925 return strdup(path);
1926 }
1927
1928 static char *pcibus_get_dev_path(DeviceState *dev)
1929 {
1930 PCIDevice *d = container_of(dev, PCIDevice, qdev);
1931 PCIDevice *t;
1932 int slot_depth;
1933 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
1934 * 00 is added here to make this format compatible with
1935 * domain:Bus:Slot.Func for systems without nested PCI bridges.
1936 * Slot.Function list specifies the slot and function numbers for all
1937 * devices on the path from root to the specific device. */
1938 char domain[] = "DDDD:00";
1939 char slot[] = ":SS.F";
1940 int domain_len = sizeof domain - 1 /* For '\0' */;
1941 int slot_len = sizeof slot - 1 /* For '\0' */;
1942 int path_len;
1943 char *path, *p;
1944 int s;
1945
1946 /* Calculate # of slots on path between device and root. */;
1947 slot_depth = 0;
1948 for (t = d; t; t = t->bus->parent_dev) {
1949 ++slot_depth;
1950 }
1951
1952 path_len = domain_len + slot_len * slot_depth;
1953
1954 /* Allocate memory, fill in the terminating null byte. */
1955 path = g_malloc(path_len + 1 /* For '\0' */);
1956 path[path_len] = '\0';
1957
1958 /* First field is the domain. */
1959 s = snprintf(domain, sizeof domain, "%04x:00", pci_find_domain(d->bus));
1960 assert(s == domain_len);
1961 memcpy(path, domain, domain_len);
1962
1963 /* Fill in slot numbers. We walk up from device to root, so need to print
1964 * them in the reverse order, last to first. */
1965 p = path + path_len;
1966 for (t = d; t; t = t->bus->parent_dev) {
1967 p -= slot_len;
1968 s = snprintf(slot, sizeof slot, ":%02x.%x",
1969 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn));
1970 assert(s == slot_len);
1971 memcpy(p, slot, slot_len);
1972 }
1973
1974 return path;
1975 }
1976
1977 static int pci_qdev_find_recursive(PCIBus *bus,
1978 const char *id, PCIDevice **pdev)
1979 {
1980 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
1981 if (!qdev) {
1982 return -ENODEV;
1983 }
1984
1985 /* roughly check if given qdev is pci device */
1986 if (qdev_get_info(qdev)->init == &pci_qdev_init &&
1987 qdev->parent_bus->info == &pci_bus_info) {
1988 *pdev = DO_UPCAST(PCIDevice, qdev, qdev);
1989 return 0;
1990 }
1991 return -EINVAL;
1992 }
1993
1994 int pci_qdev_find_device(const char *id, PCIDevice **pdev)
1995 {
1996 struct PCIHostBus *host;
1997 int rc = -ENODEV;
1998
1999 QLIST_FOREACH(host, &host_buses, next) {
2000 int tmp = pci_qdev_find_recursive(host->bus, id, pdev);
2001 if (!tmp) {
2002 rc = 0;
2003 break;
2004 }
2005 if (tmp != -ENODEV) {
2006 rc = tmp;
2007 }
2008 }
2009
2010 return rc;
2011 }
2012
2013 MemoryRegion *pci_address_space(PCIDevice *dev)
2014 {
2015 return dev->bus->address_space_mem;
2016 }
2017
2018 MemoryRegion *pci_address_space_io(PCIDevice *dev)
2019 {
2020 return dev->bus->address_space_io;
2021 }