linux-user: stack_base is now mandatory on all targets
[qemu.git] / hw / pci.h
1 #ifndef QEMU_PCI_H
2 #define QEMU_PCI_H
3
4 #include "qemu-common.h"
5
6 #include "qdev.h"
7 #include "memory.h"
8 #include "dma.h"
9
10 /* PCI includes legacy ISA access. */
11 #include "isa.h"
12
13 #include "pcie.h"
14
15 /* PCI bus */
16
17 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
18 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
19 #define PCI_FUNC(devfn) ((devfn) & 0x07)
20 #define PCI_SLOT_MAX 32
21 #define PCI_FUNC_MAX 8
22
23 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
24 #include "pci_ids.h"
25
26 /* QEMU-specific Vendor and Device ID definitions */
27
28 /* IBM (0x1014) */
29 #define PCI_DEVICE_ID_IBM_440GX 0x027f
30 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
31
32 /* Hitachi (0x1054) */
33 #define PCI_VENDOR_ID_HITACHI 0x1054
34 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e
35
36 /* Apple (0x106b) */
37 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010
38 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
39 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
40 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
41 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f
42
43 /* Realtek (0x10ec) */
44 #define PCI_DEVICE_ID_REALTEK_8029 0x8029
45
46 /* Xilinx (0x10ee) */
47 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300
48
49 /* Marvell (0x11ab) */
50 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620
51
52 /* QEMU/Bochs VGA (0x1234) */
53 #define PCI_VENDOR_ID_QEMU 0x1234
54 #define PCI_DEVICE_ID_QEMU_VGA 0x1111
55
56 /* VMWare (0x15ad) */
57 #define PCI_VENDOR_ID_VMWARE 0x15ad
58 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
59 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
60 #define PCI_DEVICE_ID_VMWARE_NET 0x0720
61 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
62 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729
63
64 /* Intel (0x8086) */
65 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209
66 #define PCI_DEVICE_ID_INTEL_82557 0x1229
67 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922
68
69 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
70 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
71 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
72 #define PCI_SUBDEVICE_ID_QEMU 0x1100
73
74 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000
75 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
76 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
77 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
78
79 #define FMT_PCIBUS PRIx64
80
81 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
82 uint32_t address, uint32_t data, int len);
83 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
84 uint32_t address, int len);
85 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
86 pcibus_t addr, pcibus_t size, int type);
87 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
88
89 typedef struct PCIIORegion {
90 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
91 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
92 pcibus_t size;
93 uint8_t type;
94 MemoryRegion *memory;
95 MemoryRegion *address_space;
96 } PCIIORegion;
97
98 #define PCI_ROM_SLOT 6
99 #define PCI_NUM_REGIONS 7
100
101 #include "pci_regs.h"
102
103 /* PCI HEADER_TYPE */
104 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
105
106 /* Size of the standard PCI config header */
107 #define PCI_CONFIG_HEADER_SIZE 0x40
108 /* Size of the standard PCI config space */
109 #define PCI_CONFIG_SPACE_SIZE 0x100
110 /* Size of the standart PCIe config space: 4KB */
111 #define PCIE_CONFIG_SPACE_SIZE 0x1000
112
113 #define PCI_NUM_PINS 4 /* A-D */
114
115 /* Bits in cap_present field. */
116 enum {
117 QEMU_PCI_CAP_MSI = 0x1,
118 QEMU_PCI_CAP_MSIX = 0x2,
119 QEMU_PCI_CAP_EXPRESS = 0x4,
120
121 /* multifunction capable device */
122 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3
123 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
124
125 /* command register SERR bit enabled */
126 #define QEMU_PCI_CAP_SERR_BITNR 4
127 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
128 };
129
130 #define TYPE_PCI_DEVICE "pci-device"
131 #define PCI_DEVICE(obj) \
132 OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE)
133 #define PCI_DEVICE_CLASS(klass) \
134 OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE)
135 #define PCI_DEVICE_GET_CLASS(obj) \
136 OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE)
137
138 typedef struct PCIDeviceClass {
139 DeviceClass parent_class;
140
141 int (*init)(PCIDevice *dev);
142 PCIUnregisterFunc *exit;
143 PCIConfigReadFunc *config_read;
144 PCIConfigWriteFunc *config_write;
145
146 uint16_t vendor_id;
147 uint16_t device_id;
148 uint8_t revision;
149 uint16_t class_id;
150 uint16_t subsystem_vendor_id; /* only for header type = 0 */
151 uint16_t subsystem_id; /* only for header type = 0 */
152
153 /*
154 * pci-to-pci bridge or normal device.
155 * This doesn't mean pci host switch.
156 * When card bus bridge is supported, this would be enhanced.
157 */
158 int is_bridge;
159
160 /* pcie stuff */
161 int is_express; /* is this device pci express? */
162
163 /* device isn't hot-pluggable */
164 int no_hotplug;
165
166 /* rom bar */
167 const char *romfile;
168 } PCIDeviceClass;
169
170 struct PCIDevice {
171 DeviceState qdev;
172 /* PCI config space */
173 uint8_t *config;
174
175 /* Used to enable config checks on load. Note that writable bits are
176 * never checked even if set in cmask. */
177 uint8_t *cmask;
178
179 /* Used to implement R/W bytes */
180 uint8_t *wmask;
181
182 /* Used to implement RW1C(Write 1 to Clear) bytes */
183 uint8_t *w1cmask;
184
185 /* Used to allocate config space for capabilities. */
186 uint8_t *used;
187
188 /* the following fields are read only */
189 PCIBus *bus;
190 uint32_t devfn;
191 char name[64];
192 PCIIORegion io_regions[PCI_NUM_REGIONS];
193
194 /* do not access the following fields */
195 PCIConfigReadFunc *config_read;
196 PCIConfigWriteFunc *config_write;
197
198 /* IRQ objects for the INTA-INTD pins. */
199 qemu_irq *irq;
200
201 /* Current IRQ levels. Used internally by the generic PCI code. */
202 uint8_t irq_state;
203
204 /* Capability bits */
205 uint32_t cap_present;
206
207 /* Offset of MSI-X capability in config space */
208 uint8_t msix_cap;
209
210 /* MSI-X entries */
211 int msix_entries_nr;
212
213 /* Space to store MSIX table */
214 uint8_t *msix_table_page;
215 /* MMIO index used to map MSIX table and pending bit entries. */
216 MemoryRegion msix_mmio;
217 /* Reference-count for entries actually in use by driver. */
218 unsigned *msix_entry_used;
219 /* Region including the MSI-X table */
220 uint32_t msix_bar_size;
221 /* MSIX function mask set or MSIX disabled */
222 bool msix_function_masked;
223 /* Version id needed for VMState */
224 int32_t version_id;
225
226 /* Offset of MSI capability in config space */
227 uint8_t msi_cap;
228
229 /* PCI Express */
230 PCIExpressDevice exp;
231
232 /* Location of option rom */
233 char *romfile;
234 bool has_rom;
235 MemoryRegion rom;
236 uint32_t rom_bar;
237 };
238
239 void pci_register_bar(PCIDevice *pci_dev, int region_num,
240 uint8_t attr, MemoryRegion *memory);
241 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
242
243 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
244 uint8_t offset, uint8_t size);
245
246 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
247
248 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
249
250
251 uint32_t pci_default_read_config(PCIDevice *d,
252 uint32_t address, int len);
253 void pci_default_write_config(PCIDevice *d,
254 uint32_t address, uint32_t val, int len);
255 void pci_device_save(PCIDevice *s, QEMUFile *f);
256 int pci_device_load(PCIDevice *s, QEMUFile *f);
257 MemoryRegion *pci_address_space(PCIDevice *dev);
258 MemoryRegion *pci_address_space_io(PCIDevice *dev);
259
260 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
261 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
262
263 typedef enum {
264 PCI_HOTPLUG_DISABLED,
265 PCI_HOTPLUG_ENABLED,
266 PCI_COLDPLUG_ENABLED,
267 } PCIHotplugState;
268
269 typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev,
270 PCIHotplugState state);
271 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
272 const char *name,
273 MemoryRegion *address_space_mem,
274 MemoryRegion *address_space_io,
275 uint8_t devfn_min);
276 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
277 MemoryRegion *address_space_mem,
278 MemoryRegion *address_space_io,
279 uint8_t devfn_min);
280 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
281 void *irq_opaque, int nirq);
282 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
283 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
284 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
285 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
286 void *irq_opaque,
287 MemoryRegion *address_space_mem,
288 MemoryRegion *address_space_io,
289 uint8_t devfn_min, int nirq);
290 void pci_device_reset(PCIDevice *dev);
291 void pci_bus_reset(PCIBus *bus);
292
293 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
294 const char *default_devaddr);
295 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
296 const char *default_devaddr);
297 int pci_bus_num(PCIBus *s);
298 void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d));
299 PCIBus *pci_find_root_bus(int domain);
300 int pci_find_domain(const PCIBus *bus);
301 PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
302 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
303 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
304 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
305
306 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
307 unsigned int *slotp, unsigned int *funcp);
308 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
309 unsigned *slotp);
310
311 void pci_device_deassert_intx(PCIDevice *dev);
312
313 static inline void
314 pci_set_byte(uint8_t *config, uint8_t val)
315 {
316 *config = val;
317 }
318
319 static inline uint8_t
320 pci_get_byte(const uint8_t *config)
321 {
322 return *config;
323 }
324
325 static inline void
326 pci_set_word(uint8_t *config, uint16_t val)
327 {
328 cpu_to_le16wu((uint16_t *)config, val);
329 }
330
331 static inline uint16_t
332 pci_get_word(const uint8_t *config)
333 {
334 return le16_to_cpupu((const uint16_t *)config);
335 }
336
337 static inline void
338 pci_set_long(uint8_t *config, uint32_t val)
339 {
340 cpu_to_le32wu((uint32_t *)config, val);
341 }
342
343 static inline uint32_t
344 pci_get_long(const uint8_t *config)
345 {
346 return le32_to_cpupu((const uint32_t *)config);
347 }
348
349 static inline void
350 pci_set_quad(uint8_t *config, uint64_t val)
351 {
352 cpu_to_le64w((uint64_t *)config, val);
353 }
354
355 static inline uint64_t
356 pci_get_quad(const uint8_t *config)
357 {
358 return le64_to_cpup((const uint64_t *)config);
359 }
360
361 static inline void
362 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
363 {
364 pci_set_word(&pci_config[PCI_VENDOR_ID], val);
365 }
366
367 static inline void
368 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
369 {
370 pci_set_word(&pci_config[PCI_DEVICE_ID], val);
371 }
372
373 static inline void
374 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
375 {
376 pci_set_byte(&pci_config[PCI_REVISION_ID], val);
377 }
378
379 static inline void
380 pci_config_set_class(uint8_t *pci_config, uint16_t val)
381 {
382 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
383 }
384
385 static inline void
386 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
387 {
388 pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
389 }
390
391 static inline void
392 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
393 {
394 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
395 }
396
397 /*
398 * helper functions to do bit mask operation on configuration space.
399 * Just to set bit, use test-and-set and discard returned value.
400 * Just to clear bit, use test-and-clear and discard returned value.
401 * NOTE: They aren't atomic.
402 */
403 static inline uint8_t
404 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
405 {
406 uint8_t val = pci_get_byte(config);
407 pci_set_byte(config, val & ~mask);
408 return val & mask;
409 }
410
411 static inline uint8_t
412 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
413 {
414 uint8_t val = pci_get_byte(config);
415 pci_set_byte(config, val | mask);
416 return val & mask;
417 }
418
419 static inline uint16_t
420 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
421 {
422 uint16_t val = pci_get_word(config);
423 pci_set_word(config, val & ~mask);
424 return val & mask;
425 }
426
427 static inline uint16_t
428 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
429 {
430 uint16_t val = pci_get_word(config);
431 pci_set_word(config, val | mask);
432 return val & mask;
433 }
434
435 static inline uint32_t
436 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
437 {
438 uint32_t val = pci_get_long(config);
439 pci_set_long(config, val & ~mask);
440 return val & mask;
441 }
442
443 static inline uint32_t
444 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
445 {
446 uint32_t val = pci_get_long(config);
447 pci_set_long(config, val | mask);
448 return val & mask;
449 }
450
451 static inline uint64_t
452 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
453 {
454 uint64_t val = pci_get_quad(config);
455 pci_set_quad(config, val & ~mask);
456 return val & mask;
457 }
458
459 static inline uint64_t
460 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
461 {
462 uint64_t val = pci_get_quad(config);
463 pci_set_quad(config, val | mask);
464 return val & mask;
465 }
466
467 void pci_qdev_register(DeviceInfo *info);
468
469 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
470 const char *name);
471 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
472 bool multifunction,
473 const char *name);
474 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
475 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
476
477 static inline int pci_is_express(const PCIDevice *d)
478 {
479 return d->cap_present & QEMU_PCI_CAP_EXPRESS;
480 }
481
482 static inline uint32_t pci_config_size(const PCIDevice *d)
483 {
484 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
485 }
486
487 /* DMA access functions */
488 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
489 void *buf, dma_addr_t len, DMADirection dir)
490 {
491 cpu_physical_memory_rw(addr, buf, len, dir == DMA_DIRECTION_FROM_DEVICE);
492 return 0;
493 }
494
495 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr,
496 void *buf, dma_addr_t len)
497 {
498 return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
499 }
500
501 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr,
502 const void *buf, dma_addr_t len)
503 {
504 return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE);
505 }
506
507 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
508 static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \
509 dma_addr_t addr) \
510 { \
511 return ld##_l##_phys(addr); \
512 } \
513 static inline void st##_s##_pci_dma(PCIDevice *dev, \
514 dma_addr_t addr, uint##_bits##_t val) \
515 { \
516 st##_s##_phys(addr, val); \
517 }
518
519 PCI_DMA_DEFINE_LDST(ub, b, 8);
520 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
521 PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
522 PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
523 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
524 PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
525 PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
526
527 #undef PCI_DMA_DEFINE_LDST
528
529 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
530 dma_addr_t *plen, DMADirection dir)
531 {
532 target_phys_addr_t len = *plen;
533 void *buf;
534
535 buf = cpu_physical_memory_map(addr, &len, dir == DMA_DIRECTION_FROM_DEVICE);
536 *plen = len;
537 return buf;
538 }
539
540 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
541 DMADirection dir, dma_addr_t access_len)
542 {
543 cpu_physical_memory_unmap(buffer, len, dir == DMA_DIRECTION_FROM_DEVICE,
544 access_len);
545 }
546
547 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
548 int alloc_hint)
549 {
550 qemu_sglist_init(qsg, alloc_hint);
551 }
552
553 extern const VMStateDescription vmstate_pci_device;
554
555 #define VMSTATE_PCI_DEVICE(_field, _state) { \
556 .name = (stringify(_field)), \
557 .size = sizeof(PCIDevice), \
558 .vmsd = &vmstate_pci_device, \
559 .flags = VMS_STRUCT, \
560 .offset = vmstate_offset_value(_state, _field, PCIDevice), \
561 }
562
563 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \
564 .name = (stringify(_field)), \
565 .size = sizeof(PCIDevice), \
566 .vmsd = &vmstate_pci_device, \
567 .flags = VMS_STRUCT|VMS_POINTER, \
568 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \
569 }
570
571 #endif