qdev: don't access name through info
[qemu.git] / hw / pci.h
1 #ifndef QEMU_PCI_H
2 #define QEMU_PCI_H
3
4 #include "qemu-common.h"
5
6 #include "qdev.h"
7 #include "memory.h"
8 #include "dma.h"
9
10 /* PCI includes legacy ISA access. */
11 #include "isa.h"
12
13 #include "pcie.h"
14
15 /* PCI bus */
16
17 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
18 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
19 #define PCI_FUNC(devfn) ((devfn) & 0x07)
20 #define PCI_SLOT_MAX 32
21 #define PCI_FUNC_MAX 8
22
23 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
24 #include "pci_ids.h"
25
26 /* QEMU-specific Vendor and Device ID definitions */
27
28 /* IBM (0x1014) */
29 #define PCI_DEVICE_ID_IBM_440GX 0x027f
30 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
31
32 /* Hitachi (0x1054) */
33 #define PCI_VENDOR_ID_HITACHI 0x1054
34 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e
35
36 /* Apple (0x106b) */
37 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010
38 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
39 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
40 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
41 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f
42
43 /* Realtek (0x10ec) */
44 #define PCI_DEVICE_ID_REALTEK_8029 0x8029
45
46 /* Xilinx (0x10ee) */
47 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300
48
49 /* Marvell (0x11ab) */
50 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620
51
52 /* QEMU/Bochs VGA (0x1234) */
53 #define PCI_VENDOR_ID_QEMU 0x1234
54 #define PCI_DEVICE_ID_QEMU_VGA 0x1111
55
56 /* VMWare (0x15ad) */
57 #define PCI_VENDOR_ID_VMWARE 0x15ad
58 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
59 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
60 #define PCI_DEVICE_ID_VMWARE_NET 0x0720
61 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
62 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729
63
64 /* Intel (0x8086) */
65 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209
66 #define PCI_DEVICE_ID_INTEL_82557 0x1229
67 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922
68
69 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
70 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
71 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
72 #define PCI_SUBDEVICE_ID_QEMU 0x1100
73
74 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000
75 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
76 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
77 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
78
79 #define FMT_PCIBUS PRIx64
80
81 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
82 uint32_t address, uint32_t data, int len);
83 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
84 uint32_t address, int len);
85 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
86 pcibus_t addr, pcibus_t size, int type);
87 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
88
89 typedef struct PCIIORegion {
90 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
91 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
92 pcibus_t size;
93 uint8_t type;
94 MemoryRegion *memory;
95 MemoryRegion *address_space;
96 } PCIIORegion;
97
98 #define PCI_ROM_SLOT 6
99 #define PCI_NUM_REGIONS 7
100
101 #include "pci_regs.h"
102
103 /* PCI HEADER_TYPE */
104 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
105
106 /* Size of the standard PCI config header */
107 #define PCI_CONFIG_HEADER_SIZE 0x40
108 /* Size of the standard PCI config space */
109 #define PCI_CONFIG_SPACE_SIZE 0x100
110 /* Size of the standart PCIe config space: 4KB */
111 #define PCIE_CONFIG_SPACE_SIZE 0x1000
112
113 #define PCI_NUM_PINS 4 /* A-D */
114
115 /* Bits in cap_present field. */
116 enum {
117 QEMU_PCI_CAP_MSI = 0x1,
118 QEMU_PCI_CAP_MSIX = 0x2,
119 QEMU_PCI_CAP_EXPRESS = 0x4,
120
121 /* multifunction capable device */
122 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3
123 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
124
125 /* command register SERR bit enabled */
126 #define QEMU_PCI_CAP_SERR_BITNR 4
127 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
128 };
129
130 struct PCIDevice {
131 DeviceState qdev;
132 /* PCI config space */
133 uint8_t *config;
134
135 /* Used to enable config checks on load. Note that writable bits are
136 * never checked even if set in cmask. */
137 uint8_t *cmask;
138
139 /* Used to implement R/W bytes */
140 uint8_t *wmask;
141
142 /* Used to implement RW1C(Write 1 to Clear) bytes */
143 uint8_t *w1cmask;
144
145 /* Used to allocate config space for capabilities. */
146 uint8_t *used;
147
148 /* the following fields are read only */
149 PCIBus *bus;
150 uint32_t devfn;
151 char name[64];
152 PCIIORegion io_regions[PCI_NUM_REGIONS];
153
154 /* do not access the following fields */
155 PCIConfigReadFunc *config_read;
156 PCIConfigWriteFunc *config_write;
157
158 /* IRQ objects for the INTA-INTD pins. */
159 qemu_irq *irq;
160
161 /* Current IRQ levels. Used internally by the generic PCI code. */
162 uint8_t irq_state;
163
164 /* Capability bits */
165 uint32_t cap_present;
166
167 /* Offset of MSI-X capability in config space */
168 uint8_t msix_cap;
169
170 /* MSI-X entries */
171 int msix_entries_nr;
172
173 /* Space to store MSIX table */
174 uint8_t *msix_table_page;
175 /* MMIO index used to map MSIX table and pending bit entries. */
176 MemoryRegion msix_mmio;
177 /* Reference-count for entries actually in use by driver. */
178 unsigned *msix_entry_used;
179 /* Region including the MSI-X table */
180 uint32_t msix_bar_size;
181 /* MSIX function mask set or MSIX disabled */
182 bool msix_function_masked;
183 /* Version id needed for VMState */
184 int32_t version_id;
185
186 /* Offset of MSI capability in config space */
187 uint8_t msi_cap;
188
189 /* PCI Express */
190 PCIExpressDevice exp;
191
192 /* Location of option rom */
193 char *romfile;
194 bool has_rom;
195 MemoryRegion rom;
196 uint32_t rom_bar;
197 };
198
199 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
200 int instance_size, int devfn,
201 PCIConfigReadFunc *config_read,
202 PCIConfigWriteFunc *config_write);
203
204 void pci_register_bar(PCIDevice *pci_dev, int region_num,
205 uint8_t attr, MemoryRegion *memory);
206 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
207
208 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
209 uint8_t offset, uint8_t size);
210
211 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
212
213 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
214
215
216 uint32_t pci_default_read_config(PCIDevice *d,
217 uint32_t address, int len);
218 void pci_default_write_config(PCIDevice *d,
219 uint32_t address, uint32_t val, int len);
220 void pci_device_save(PCIDevice *s, QEMUFile *f);
221 int pci_device_load(PCIDevice *s, QEMUFile *f);
222 MemoryRegion *pci_address_space(PCIDevice *dev);
223 MemoryRegion *pci_address_space_io(PCIDevice *dev);
224
225 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
226 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
227
228 typedef enum {
229 PCI_HOTPLUG_DISABLED,
230 PCI_HOTPLUG_ENABLED,
231 PCI_COLDPLUG_ENABLED,
232 } PCIHotplugState;
233
234 typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev,
235 PCIHotplugState state);
236 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
237 const char *name,
238 MemoryRegion *address_space_mem,
239 MemoryRegion *address_space_io,
240 uint8_t devfn_min);
241 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
242 MemoryRegion *address_space_mem,
243 MemoryRegion *address_space_io,
244 uint8_t devfn_min);
245 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
246 void *irq_opaque, int nirq);
247 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
248 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
249 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
250 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
251 void *irq_opaque,
252 MemoryRegion *address_space_mem,
253 MemoryRegion *address_space_io,
254 uint8_t devfn_min, int nirq);
255 void pci_device_reset(PCIDevice *dev);
256 void pci_bus_reset(PCIBus *bus);
257
258 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
259 const char *default_devaddr);
260 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
261 const char *default_devaddr);
262 int pci_bus_num(PCIBus *s);
263 void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d));
264 PCIBus *pci_find_root_bus(int domain);
265 int pci_find_domain(const PCIBus *bus);
266 PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
267 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
268 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
269 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
270
271 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
272 unsigned int *slotp, unsigned int *funcp);
273 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
274 unsigned *slotp);
275
276 void pci_device_deassert_intx(PCIDevice *dev);
277
278 static inline void
279 pci_set_byte(uint8_t *config, uint8_t val)
280 {
281 *config = val;
282 }
283
284 static inline uint8_t
285 pci_get_byte(const uint8_t *config)
286 {
287 return *config;
288 }
289
290 static inline void
291 pci_set_word(uint8_t *config, uint16_t val)
292 {
293 cpu_to_le16wu((uint16_t *)config, val);
294 }
295
296 static inline uint16_t
297 pci_get_word(const uint8_t *config)
298 {
299 return le16_to_cpupu((const uint16_t *)config);
300 }
301
302 static inline void
303 pci_set_long(uint8_t *config, uint32_t val)
304 {
305 cpu_to_le32wu((uint32_t *)config, val);
306 }
307
308 static inline uint32_t
309 pci_get_long(const uint8_t *config)
310 {
311 return le32_to_cpupu((const uint32_t *)config);
312 }
313
314 static inline void
315 pci_set_quad(uint8_t *config, uint64_t val)
316 {
317 cpu_to_le64w((uint64_t *)config, val);
318 }
319
320 static inline uint64_t
321 pci_get_quad(const uint8_t *config)
322 {
323 return le64_to_cpup((const uint64_t *)config);
324 }
325
326 static inline void
327 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
328 {
329 pci_set_word(&pci_config[PCI_VENDOR_ID], val);
330 }
331
332 static inline void
333 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
334 {
335 pci_set_word(&pci_config[PCI_DEVICE_ID], val);
336 }
337
338 static inline void
339 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
340 {
341 pci_set_byte(&pci_config[PCI_REVISION_ID], val);
342 }
343
344 static inline void
345 pci_config_set_class(uint8_t *pci_config, uint16_t val)
346 {
347 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
348 }
349
350 static inline void
351 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
352 {
353 pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
354 }
355
356 static inline void
357 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
358 {
359 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
360 }
361
362 /*
363 * helper functions to do bit mask operation on configuration space.
364 * Just to set bit, use test-and-set and discard returned value.
365 * Just to clear bit, use test-and-clear and discard returned value.
366 * NOTE: They aren't atomic.
367 */
368 static inline uint8_t
369 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
370 {
371 uint8_t val = pci_get_byte(config);
372 pci_set_byte(config, val & ~mask);
373 return val & mask;
374 }
375
376 static inline uint8_t
377 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
378 {
379 uint8_t val = pci_get_byte(config);
380 pci_set_byte(config, val | mask);
381 return val & mask;
382 }
383
384 static inline uint16_t
385 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
386 {
387 uint16_t val = pci_get_word(config);
388 pci_set_word(config, val & ~mask);
389 return val & mask;
390 }
391
392 static inline uint16_t
393 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
394 {
395 uint16_t val = pci_get_word(config);
396 pci_set_word(config, val | mask);
397 return val & mask;
398 }
399
400 static inline uint32_t
401 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
402 {
403 uint32_t val = pci_get_long(config);
404 pci_set_long(config, val & ~mask);
405 return val & mask;
406 }
407
408 static inline uint32_t
409 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
410 {
411 uint32_t val = pci_get_long(config);
412 pci_set_long(config, val | mask);
413 return val & mask;
414 }
415
416 static inline uint64_t
417 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
418 {
419 uint64_t val = pci_get_quad(config);
420 pci_set_quad(config, val & ~mask);
421 return val & mask;
422 }
423
424 static inline uint64_t
425 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
426 {
427 uint64_t val = pci_get_quad(config);
428 pci_set_quad(config, val | mask);
429 return val & mask;
430 }
431
432 typedef int (*pci_qdev_initfn)(PCIDevice *dev);
433 typedef struct {
434 DeviceInfo qdev;
435 pci_qdev_initfn init;
436 PCIUnregisterFunc *exit;
437 PCIConfigReadFunc *config_read;
438 PCIConfigWriteFunc *config_write;
439
440 uint16_t vendor_id;
441 uint16_t device_id;
442 uint8_t revision;
443 uint16_t class_id;
444 uint16_t subsystem_vendor_id; /* only for header type = 0 */
445 uint16_t subsystem_id; /* only for header type = 0 */
446
447 /*
448 * pci-to-pci bridge or normal device.
449 * This doesn't mean pci host switch.
450 * When card bus bridge is supported, this would be enhanced.
451 */
452 int is_bridge;
453
454 /* pcie stuff */
455 int is_express; /* is this device pci express? */
456
457 /* device isn't hot-pluggable */
458 int no_hotplug;
459
460 /* rom bar */
461 const char *romfile;
462 } PCIDeviceInfo;
463
464 void pci_qdev_register(PCIDeviceInfo *info);
465 void pci_qdev_register_many(PCIDeviceInfo *info);
466
467 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
468 const char *name);
469 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
470 bool multifunction,
471 const char *name);
472 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
473 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
474
475 static inline int pci_is_express(const PCIDevice *d)
476 {
477 return d->cap_present & QEMU_PCI_CAP_EXPRESS;
478 }
479
480 static inline uint32_t pci_config_size(const PCIDevice *d)
481 {
482 return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
483 }
484
485 /* DMA access functions */
486 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
487 void *buf, dma_addr_t len, DMADirection dir)
488 {
489 cpu_physical_memory_rw(addr, buf, len, dir == DMA_DIRECTION_FROM_DEVICE);
490 return 0;
491 }
492
493 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr,
494 void *buf, dma_addr_t len)
495 {
496 return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
497 }
498
499 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr,
500 const void *buf, dma_addr_t len)
501 {
502 return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE);
503 }
504
505 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits) \
506 static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev, \
507 dma_addr_t addr) \
508 { \
509 return ld##_l##_phys(addr); \
510 } \
511 static inline void st##_s##_pci_dma(PCIDevice *dev, \
512 dma_addr_t addr, uint##_bits##_t val) \
513 { \
514 st##_s##_phys(addr, val); \
515 }
516
517 PCI_DMA_DEFINE_LDST(ub, b, 8);
518 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
519 PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
520 PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
521 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
522 PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
523 PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
524
525 #undef PCI_DMA_DEFINE_LDST
526
527 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
528 dma_addr_t *plen, DMADirection dir)
529 {
530 target_phys_addr_t len = *plen;
531 void *buf;
532
533 buf = cpu_physical_memory_map(addr, &len, dir == DMA_DIRECTION_FROM_DEVICE);
534 *plen = len;
535 return buf;
536 }
537
538 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
539 DMADirection dir, dma_addr_t access_len)
540 {
541 cpu_physical_memory_unmap(buffer, len, dir == DMA_DIRECTION_FROM_DEVICE,
542 access_len);
543 }
544
545 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
546 int alloc_hint)
547 {
548 qemu_sglist_init(qsg, alloc_hint);
549 }
550
551 extern const VMStateDescription vmstate_pci_device;
552
553 #define VMSTATE_PCI_DEVICE(_field, _state) { \
554 .name = (stringify(_field)), \
555 .size = sizeof(PCIDevice), \
556 .vmsd = &vmstate_pci_device, \
557 .flags = VMS_STRUCT, \
558 .offset = vmstate_offset_value(_state, _field, PCIDevice), \
559 }
560
561 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) { \
562 .name = (stringify(_field)), \
563 .size = sizeof(PCIDevice), \
564 .vmsd = &vmstate_pci_device, \
565 .flags = VMS_STRUCT|VMS_POINTER, \
566 .offset = vmstate_offset_pointer(_state, _field, PCIDevice), \
567 }
568
569 #endif