PPC: e500: msync is 440 only, e500 has real sync
[qemu.git] / hw / piix4.c
1 /*
2 * QEMU PIIX4 PCI Bridge Emulation
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "hw.h"
26 #include "pc.h"
27 #include "pci.h"
28 #include "isa.h"
29 #include "sysbus.h"
30
31 PCIDevice *piix4_dev;
32
33 typedef struct PIIX4State {
34 PCIDevice dev;
35 } PIIX4State;
36
37 static void piix4_reset(void *opaque)
38 {
39 PIIX4State *d = opaque;
40 uint8_t *pci_conf = d->dev.config;
41
42 pci_conf[0x04] = 0x07; // master, memory and I/O
43 pci_conf[0x05] = 0x00;
44 pci_conf[0x06] = 0x00;
45 pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
46 pci_conf[0x4c] = 0x4d;
47 pci_conf[0x4e] = 0x03;
48 pci_conf[0x4f] = 0x00;
49 pci_conf[0x60] = 0x0a; // PCI A -> IRQ 10
50 pci_conf[0x61] = 0x0a; // PCI B -> IRQ 10
51 pci_conf[0x62] = 0x0b; // PCI C -> IRQ 11
52 pci_conf[0x63] = 0x0b; // PCI D -> IRQ 11
53 pci_conf[0x69] = 0x02;
54 pci_conf[0x70] = 0x80;
55 pci_conf[0x76] = 0x0c;
56 pci_conf[0x77] = 0x0c;
57 pci_conf[0x78] = 0x02;
58 pci_conf[0x79] = 0x00;
59 pci_conf[0x80] = 0x00;
60 pci_conf[0x82] = 0x00;
61 pci_conf[0xa0] = 0x08;
62 pci_conf[0xa2] = 0x00;
63 pci_conf[0xa3] = 0x00;
64 pci_conf[0xa4] = 0x00;
65 pci_conf[0xa5] = 0x00;
66 pci_conf[0xa6] = 0x00;
67 pci_conf[0xa7] = 0x00;
68 pci_conf[0xa8] = 0x0f;
69 pci_conf[0xaa] = 0x00;
70 pci_conf[0xab] = 0x00;
71 pci_conf[0xac] = 0x00;
72 pci_conf[0xae] = 0x00;
73 }
74
75 static const VMStateDescription vmstate_piix4 = {
76 .name = "PIIX4",
77 .version_id = 2,
78 .minimum_version_id = 2,
79 .minimum_version_id_old = 2,
80 .fields = (VMStateField[]) {
81 VMSTATE_PCI_DEVICE(dev, PIIX4State),
82 VMSTATE_END_OF_LIST()
83 }
84 };
85
86 static int piix4_initfn(PCIDevice *dev)
87 {
88 PIIX4State *d = DO_UPCAST(PIIX4State, dev, dev);
89
90 isa_bus_new(&d->dev.qdev, pci_address_space_io(dev));
91 piix4_dev = &d->dev;
92 qemu_register_reset(piix4_reset, d);
93 return 0;
94 }
95
96 int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
97 {
98 PCIDevice *d;
99
100 d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4");
101 *isa_bus = DO_UPCAST(ISABus, qbus, qdev_get_child_bus(&d->qdev, "isa.0"));
102 return d->devfn;
103 }
104
105 static void piix4_class_init(ObjectClass *klass, void *data)
106 {
107 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
108
109 k->no_hotplug = 1;
110 k->init = piix4_initfn;
111 k->vendor_id = PCI_VENDOR_ID_INTEL;
112 k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0;
113 k->class_id = PCI_CLASS_BRIDGE_ISA;
114 }
115
116 static DeviceInfo piix4_info = {
117 .name = "PIIX4",
118 .desc = "ISA bridge",
119 .size = sizeof(PIIX4State),
120 .vmsd = &vmstate_piix4,
121 .no_user = 1,
122 .class_init = piix4_class_init,
123 };
124
125 static void piix4_register(void)
126 {
127 pci_qdev_register(&piix4_info);
128 }
129 device_init(piix4_register);