Add access control support to qemu bridge helper
[qemu.git] / hw / pl190.c
1 /*
2 * Arm PrimeCell PL190 Vector Interrupt Controller
3 *
4 * Copyright (c) 2006 CodeSourcery.
5 * Written by Paul Brook
6 *
7 * This code is licensed under the GPL.
8 */
9
10 #include "sysbus.h"
11
12 /* The number of virtual priority levels. 16 user vectors plus the
13 unvectored IRQ. Chained interrupts would require an additional level
14 if implemented. */
15
16 #define PL190_NUM_PRIO 17
17
18 typedef struct {
19 SysBusDevice busdev;
20 MemoryRegion iomem;
21 uint32_t level;
22 uint32_t soft_level;
23 uint32_t irq_enable;
24 uint32_t fiq_select;
25 uint8_t vect_control[16];
26 uint32_t vect_addr[PL190_NUM_PRIO];
27 /* Mask containing interrupts with higher priority than this one. */
28 uint32_t prio_mask[PL190_NUM_PRIO + 1];
29 int protected;
30 /* Current priority level. */
31 int priority;
32 int prev_prio[PL190_NUM_PRIO];
33 qemu_irq irq;
34 qemu_irq fiq;
35 } pl190_state;
36
37 static const unsigned char pl190_id[] =
38 { 0x90, 0x11, 0x04, 0x00, 0x0D, 0xf0, 0x05, 0xb1 };
39
40 static inline uint32_t pl190_irq_level(pl190_state *s)
41 {
42 return (s->level | s->soft_level) & s->irq_enable & ~s->fiq_select;
43 }
44
45 /* Update interrupts. */
46 static void pl190_update(pl190_state *s)
47 {
48 uint32_t level = pl190_irq_level(s);
49 int set;
50
51 set = (level & s->prio_mask[s->priority]) != 0;
52 qemu_set_irq(s->irq, set);
53 set = ((s->level | s->soft_level) & s->fiq_select) != 0;
54 qemu_set_irq(s->fiq, set);
55 }
56
57 static void pl190_set_irq(void *opaque, int irq, int level)
58 {
59 pl190_state *s = (pl190_state *)opaque;
60
61 if (level)
62 s->level |= 1u << irq;
63 else
64 s->level &= ~(1u << irq);
65 pl190_update(s);
66 }
67
68 static void pl190_update_vectors(pl190_state *s)
69 {
70 uint32_t mask;
71 int i;
72 int n;
73
74 mask = 0;
75 for (i = 0; i < 16; i++)
76 {
77 s->prio_mask[i] = mask;
78 if (s->vect_control[i] & 0x20)
79 {
80 n = s->vect_control[i] & 0x1f;
81 mask |= 1 << n;
82 }
83 }
84 s->prio_mask[16] = mask;
85 pl190_update(s);
86 }
87
88 static uint64_t pl190_read(void *opaque, target_phys_addr_t offset,
89 unsigned size)
90 {
91 pl190_state *s = (pl190_state *)opaque;
92 int i;
93
94 if (offset >= 0xfe0 && offset < 0x1000) {
95 return pl190_id[(offset - 0xfe0) >> 2];
96 }
97 if (offset >= 0x100 && offset < 0x140) {
98 return s->vect_addr[(offset - 0x100) >> 2];
99 }
100 if (offset >= 0x200 && offset < 0x240) {
101 return s->vect_control[(offset - 0x200) >> 2];
102 }
103 switch (offset >> 2) {
104 case 0: /* IRQSTATUS */
105 return pl190_irq_level(s);
106 case 1: /* FIQSATUS */
107 return (s->level | s->soft_level) & s->fiq_select;
108 case 2: /* RAWINTR */
109 return s->level | s->soft_level;
110 case 3: /* INTSELECT */
111 return s->fiq_select;
112 case 4: /* INTENABLE */
113 return s->irq_enable;
114 case 6: /* SOFTINT */
115 return s->soft_level;
116 case 8: /* PROTECTION */
117 return s->protected;
118 case 12: /* VECTADDR */
119 /* Read vector address at the start of an ISR. Increases the
120 current priority level to that of the current interrupt. */
121 for (i = 0; i < s->priority; i++)
122 {
123 if ((s->level | s->soft_level) & s->prio_mask[i])
124 break;
125 }
126 /* Reading this value with no pending interrupts is undefined.
127 We return the default address. */
128 if (i == PL190_NUM_PRIO)
129 return s->vect_addr[16];
130 if (i < s->priority)
131 {
132 s->prev_prio[i] = s->priority;
133 s->priority = i;
134 pl190_update(s);
135 }
136 return s->vect_addr[s->priority];
137 case 13: /* DEFVECTADDR */
138 return s->vect_addr[16];
139 default:
140 hw_error("pl190_read: Bad offset %x\n", (int)offset);
141 return 0;
142 }
143 }
144
145 static void pl190_write(void *opaque, target_phys_addr_t offset,
146 uint64_t val, unsigned size)
147 {
148 pl190_state *s = (pl190_state *)opaque;
149
150 if (offset >= 0x100 && offset < 0x140) {
151 s->vect_addr[(offset - 0x100) >> 2] = val;
152 pl190_update_vectors(s);
153 return;
154 }
155 if (offset >= 0x200 && offset < 0x240) {
156 s->vect_control[(offset - 0x200) >> 2] = val;
157 pl190_update_vectors(s);
158 return;
159 }
160 switch (offset >> 2) {
161 case 0: /* SELECT */
162 /* This is a readonly register, but linux tries to write to it
163 anyway. Ignore the write. */
164 break;
165 case 3: /* INTSELECT */
166 s->fiq_select = val;
167 break;
168 case 4: /* INTENABLE */
169 s->irq_enable |= val;
170 break;
171 case 5: /* INTENCLEAR */
172 s->irq_enable &= ~val;
173 break;
174 case 6: /* SOFTINT */
175 s->soft_level |= val;
176 break;
177 case 7: /* SOFTINTCLEAR */
178 s->soft_level &= ~val;
179 break;
180 case 8: /* PROTECTION */
181 /* TODO: Protection (supervisor only access) is not implemented. */
182 s->protected = val & 1;
183 break;
184 case 12: /* VECTADDR */
185 /* Restore the previous priority level. The value written is
186 ignored. */
187 if (s->priority < PL190_NUM_PRIO)
188 s->priority = s->prev_prio[s->priority];
189 break;
190 case 13: /* DEFVECTADDR */
191 s->vect_addr[16] = val;
192 break;
193 case 0xc0: /* ITCR */
194 if (val) {
195 hw_error("pl190: Test mode not implemented\n");
196 }
197 break;
198 default:
199 hw_error("pl190_write: Bad offset %x\n", (int)offset);
200 return;
201 }
202 pl190_update(s);
203 }
204
205 static const MemoryRegionOps pl190_ops = {
206 .read = pl190_read,
207 .write = pl190_write,
208 .endianness = DEVICE_NATIVE_ENDIAN,
209 };
210
211 static void pl190_reset(DeviceState *d)
212 {
213 pl190_state *s = DO_UPCAST(pl190_state, busdev.qdev, d);
214 int i;
215
216 for (i = 0; i < 16; i++)
217 {
218 s->vect_addr[i] = 0;
219 s->vect_control[i] = 0;
220 }
221 s->vect_addr[16] = 0;
222 s->prio_mask[17] = 0xffffffff;
223 s->priority = PL190_NUM_PRIO;
224 pl190_update_vectors(s);
225 }
226
227 static int pl190_init(SysBusDevice *dev)
228 {
229 pl190_state *s = FROM_SYSBUS(pl190_state, dev);
230
231 memory_region_init_io(&s->iomem, &pl190_ops, s, "pl190", 0x1000);
232 sysbus_init_mmio(dev, &s->iomem);
233 qdev_init_gpio_in(&dev->qdev, pl190_set_irq, 32);
234 sysbus_init_irq(dev, &s->irq);
235 sysbus_init_irq(dev, &s->fiq);
236 return 0;
237 }
238
239 static const VMStateDescription vmstate_pl190 = {
240 .name = "pl190",
241 .version_id = 1,
242 .minimum_version_id = 1,
243 .fields = (VMStateField[]) {
244 VMSTATE_UINT32(level, pl190_state),
245 VMSTATE_UINT32(soft_level, pl190_state),
246 VMSTATE_UINT32(irq_enable, pl190_state),
247 VMSTATE_UINT32(fiq_select, pl190_state),
248 VMSTATE_UINT8_ARRAY(vect_control, pl190_state, 16),
249 VMSTATE_UINT32_ARRAY(vect_addr, pl190_state, PL190_NUM_PRIO),
250 VMSTATE_UINT32_ARRAY(prio_mask, pl190_state, PL190_NUM_PRIO+1),
251 VMSTATE_INT32(protected, pl190_state),
252 VMSTATE_INT32(priority, pl190_state),
253 VMSTATE_INT32_ARRAY(prev_prio, pl190_state, PL190_NUM_PRIO),
254 VMSTATE_END_OF_LIST()
255 }
256 };
257
258 static void pl190_class_init(ObjectClass *klass, void *data)
259 {
260 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
261
262 k->init = pl190_init;
263 }
264
265 static DeviceInfo pl190_info = {
266 .name = "pl190",
267 .size = sizeof(pl190_state),
268 .vmsd = &vmstate_pl190,
269 .reset = pl190_reset,
270 .no_user = 1,
271 .class_init = pl190_class_init,
272 };
273
274 static void pl190_register_devices(void)
275 {
276 sysbus_register_withprop(&pl190_info);
277 }
278
279 device_init(pl190_register_devices)