Update version for v7.1.0-rc3 release
[qemu.git] / hw / ppc / mac_newworld.c
1 /*
2 * QEMU PowerPC CHRP (currently NewWorld PowerMac) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 *
25 * PCI bus layout on a real G5 (U3 based):
26 *
27 * 0000:f0:0b.0 Host bridge [0600]: Apple Computer Inc. U3 AGP [106b:004b]
28 * 0000:f0:10.0 VGA compatible controller [0300]: ATI Technologies Inc RV350 AP [Radeon 9600] [1002:4150]
29 * 0001:00:00.0 Host bridge [0600]: Apple Computer Inc. CPC945 HT Bridge [106b:004a]
30 * 0001:00:01.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12)
31 * 0001:00:02.0 PCI bridge [0604]: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge [1022:7450] (rev 12)
32 * 0001:00:03.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0045]
33 * 0001:00:04.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0046]
34 * 0001:00:05.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0047]
35 * 0001:00:06.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0048]
36 * 0001:00:07.0 PCI bridge [0604]: Apple Computer Inc. K2 HT-PCI Bridge [106b:0049]
37 * 0001:01:07.0 Class [ff00]: Apple Computer Inc. K2 KeyLargo Mac/IO [106b:0041] (rev 20)
38 * 0001:01:08.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040]
39 * 0001:01:09.0 USB Controller [0c03]: Apple Computer Inc. K2 KeyLargo USB [106b:0040]
40 * 0001:02:0b.0 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43)
41 * 0001:02:0b.1 USB Controller [0c03]: NEC Corporation USB [1033:0035] (rev 43)
42 * 0001:02:0b.2 USB Controller [0c03]: NEC Corporation USB 2.0 [1033:00e0] (rev 04)
43 * 0001:03:0d.0 Class [ff00]: Apple Computer Inc. K2 ATA/100 [106b:0043]
44 * 0001:03:0e.0 FireWire (IEEE 1394) [0c00]: Apple Computer Inc. K2 FireWire [106b:0042]
45 * 0001:04:0f.0 Ethernet controller [0200]: Apple Computer Inc. K2 GMAC (Sun GEM) [106b:004c]
46 * 0001:05:0c.0 IDE interface [0101]: Broadcom K2 SATA [1166:0240]
47 */
48
49 #include "qemu/osdep.h"
50 #include "qemu/datadir.h"
51 #include "qapi/error.h"
52 #include "hw/ppc/ppc.h"
53 #include "hw/qdev-properties.h"
54 #include "hw/ppc/mac.h"
55 #include "hw/input/adb.h"
56 #include "hw/ppc/mac_dbdma.h"
57 #include "hw/pci/pci.h"
58 #include "net/net.h"
59 #include "sysemu/sysemu.h"
60 #include "hw/nvram/fw_cfg.h"
61 #include "hw/char/escc.h"
62 #include "hw/misc/macio/macio.h"
63 #include "hw/ppc/openpic.h"
64 #include "hw/loader.h"
65 #include "hw/fw-path-provider.h"
66 #include "elf.h"
67 #include "qemu/error-report.h"
68 #include "sysemu/kvm.h"
69 #include "sysemu/reset.h"
70 #include "kvm_ppc.h"
71 #include "hw/usb.h"
72 #include "hw/sysbus.h"
73 #include "trace.h"
74
75 #define MAX_IDE_BUS 2
76 #define CFG_ADDR 0xf0000510
77 #define TBFREQ (100UL * 1000UL * 1000UL)
78 #define CLOCKFREQ (900UL * 1000UL * 1000UL)
79 #define BUSFREQ (100UL * 1000UL * 1000UL)
80
81 #define NDRV_VGA_FILENAME "qemu_vga.ndrv"
82
83 #define PROM_BASE 0xfff00000
84 #define PROM_SIZE (1 * MiB)
85
86 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
87 Error **errp)
88 {
89 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
90 }
91
92 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
93 {
94 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
95 }
96
97 static void ppc_core99_reset(void *opaque)
98 {
99 PowerPCCPU *cpu = opaque;
100
101 cpu_reset(CPU(cpu));
102 /* 970 CPUs want to get their initial IP as part of their boot protocol */
103 cpu->env.nip = PROM_BASE + 0x100;
104 }
105
106 /* PowerPC Mac99 hardware initialisation */
107 static void ppc_core99_init(MachineState *machine)
108 {
109 ram_addr_t ram_size = machine->ram_size;
110 const char *bios_name = machine->firmware ?: PROM_FILENAME;
111 const char *kernel_filename = machine->kernel_filename;
112 const char *kernel_cmdline = machine->kernel_cmdline;
113 const char *initrd_filename = machine->initrd_filename;
114 const char *boot_device = machine->boot_config.order;
115 Core99MachineState *core99_machine = CORE99_MACHINE(machine);
116 PowerPCCPU *cpu = NULL;
117 CPUPPCState *env = NULL;
118 char *filename;
119 IrqLines *openpic_irqs;
120 int linux_boot, i, j, k;
121 MemoryRegion *bios = g_new(MemoryRegion, 1);
122 hwaddr kernel_base, initrd_base, cmdline_base = 0;
123 long kernel_size, initrd_size;
124 UNINHostState *uninorth_pci;
125 PCIBus *pci_bus;
126 PCIDevice *macio;
127 ESCCState *escc;
128 bool has_pmu, has_adb;
129 MACIOIDEState *macio_ide;
130 BusState *adb_bus;
131 MacIONVRAMState *nvr;
132 int bios_size;
133 int ppc_boot_device;
134 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
135 void *fw_cfg;
136 int machine_arch;
137 SysBusDevice *s;
138 DeviceState *dev, *pic_dev;
139 DeviceState *uninorth_internal_dev = NULL, *uninorth_agp_dev = NULL;
140 hwaddr nvram_addr = 0xFFF04000;
141 uint64_t tbfreq;
142 unsigned int smp_cpus = machine->smp.cpus;
143
144 linux_boot = (kernel_filename != NULL);
145
146 /* init CPUs */
147 for (i = 0; i < smp_cpus; i++) {
148 cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
149 env = &cpu->env;
150
151 /* Set time-base frequency to 100 Mhz */
152 cpu_ppc_tb_init(env, TBFREQ);
153 qemu_register_reset(ppc_core99_reset, cpu);
154 }
155
156 /* allocate RAM */
157 if (machine->ram_size > 2 * GiB) {
158 error_report("RAM size more than 2 GiB is not supported");
159 exit(1);
160 }
161 memory_region_add_subregion(get_system_memory(), 0, machine->ram);
162
163 /* allocate and load firmware ROM */
164 memory_region_init_rom(bios, NULL, "ppc_core99.bios", PROM_SIZE,
165 &error_fatal);
166 memory_region_add_subregion(get_system_memory(), PROM_BASE, bios);
167
168 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
169 if (filename) {
170 /* Load OpenBIOS (ELF) */
171 bios_size = load_elf(filename, NULL, NULL, NULL, NULL,
172 NULL, NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0);
173
174 if (bios_size <= 0) {
175 /* or load binary ROM image */
176 bios_size = load_image_targphys(filename, PROM_BASE, PROM_SIZE);
177 }
178 g_free(filename);
179 } else {
180 bios_size = -1;
181 }
182 if (bios_size < 0 || bios_size > PROM_SIZE) {
183 error_report("could not load PowerPC bios '%s'", bios_name);
184 exit(1);
185 }
186
187 if (linux_boot) {
188 int bswap_needed;
189
190 #ifdef BSWAP_NEEDED
191 bswap_needed = 1;
192 #else
193 bswap_needed = 0;
194 #endif
195 kernel_base = KERNEL_LOAD_ADDR;
196
197 kernel_size = load_elf(kernel_filename, NULL,
198 translate_kernel_address, NULL, NULL, NULL,
199 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0);
200 if (kernel_size < 0)
201 kernel_size = load_aout(kernel_filename, kernel_base,
202 ram_size - kernel_base, bswap_needed,
203 TARGET_PAGE_SIZE);
204 if (kernel_size < 0)
205 kernel_size = load_image_targphys(kernel_filename,
206 kernel_base,
207 ram_size - kernel_base);
208 if (kernel_size < 0) {
209 error_report("could not load kernel '%s'", kernel_filename);
210 exit(1);
211 }
212 /* load initrd */
213 if (initrd_filename) {
214 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP);
215 initrd_size = load_image_targphys(initrd_filename, initrd_base,
216 ram_size - initrd_base);
217 if (initrd_size < 0) {
218 error_report("could not load initial ram disk '%s'",
219 initrd_filename);
220 exit(1);
221 }
222 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size);
223 } else {
224 initrd_base = 0;
225 initrd_size = 0;
226 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP);
227 }
228 ppc_boot_device = 'm';
229 } else {
230 kernel_base = 0;
231 kernel_size = 0;
232 initrd_base = 0;
233 initrd_size = 0;
234 ppc_boot_device = '\0';
235 /* We consider that NewWorld PowerMac never have any floppy drive
236 * For now, OHW cannot boot from the network.
237 */
238 for (i = 0; boot_device[i] != '\0'; i++) {
239 if (boot_device[i] >= 'c' && boot_device[i] <= 'f') {
240 ppc_boot_device = boot_device[i];
241 break;
242 }
243 }
244 if (ppc_boot_device == '\0') {
245 error_report("No valid boot device for Mac99 machine");
246 exit(1);
247 }
248 }
249
250 /* UniN init */
251 dev = qdev_new(TYPE_UNI_NORTH);
252 s = SYS_BUS_DEVICE(dev);
253 sysbus_realize_and_unref(s, &error_fatal);
254 memory_region_add_subregion(get_system_memory(), 0xf8000000,
255 sysbus_mmio_get_region(s, 0));
256
257 openpic_irqs = g_new0(IrqLines, smp_cpus);
258 for (i = 0; i < smp_cpus; i++) {
259 /* Mac99 IRQ connection between OpenPIC outputs pins
260 * and PowerPC input pins
261 */
262 switch (PPC_INPUT(env)) {
263 case PPC_FLAGS_INPUT_6xx:
264 openpic_irqs[i].irq[OPENPIC_OUTPUT_INT] =
265 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
266 openpic_irqs[i].irq[OPENPIC_OUTPUT_CINT] =
267 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
268 openpic_irqs[i].irq[OPENPIC_OUTPUT_MCK] =
269 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP];
270 /* Not connected ? */
271 openpic_irqs[i].irq[OPENPIC_OUTPUT_DEBUG] = NULL;
272 /* Check this */
273 openpic_irqs[i].irq[OPENPIC_OUTPUT_RESET] =
274 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET];
275 break;
276 #if defined(TARGET_PPC64)
277 case PPC_FLAGS_INPUT_970:
278 openpic_irqs[i].irq[OPENPIC_OUTPUT_INT] =
279 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
280 openpic_irqs[i].irq[OPENPIC_OUTPUT_CINT] =
281 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
282 openpic_irqs[i].irq[OPENPIC_OUTPUT_MCK] =
283 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP];
284 /* Not connected ? */
285 openpic_irqs[i].irq[OPENPIC_OUTPUT_DEBUG] = NULL;
286 /* Check this */
287 openpic_irqs[i].irq[OPENPIC_OUTPUT_RESET] =
288 ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];
289 break;
290 #endif /* defined(TARGET_PPC64) */
291 default:
292 error_report("Bus model not supported on mac99 machine");
293 exit(1);
294 }
295 }
296
297 if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) {
298 /* 970 gets a U3 bus */
299 /* Uninorth AGP bus */
300 dev = qdev_new(TYPE_U3_AGP_HOST_BRIDGE);
301 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
302 uninorth_pci = U3_AGP_HOST_BRIDGE(dev);
303 s = SYS_BUS_DEVICE(dev);
304 /* PCI hole */
305 memory_region_add_subregion(get_system_memory(), 0x80000000ULL,
306 sysbus_mmio_get_region(s, 2));
307 /* Register 8 MB of ISA IO space */
308 memory_region_add_subregion(get_system_memory(), 0xf2000000,
309 sysbus_mmio_get_region(s, 3));
310 sysbus_mmio_map(s, 0, 0xf0800000);
311 sysbus_mmio_map(s, 1, 0xf0c00000);
312
313 machine_arch = ARCH_MAC99_U3;
314 } else {
315 /* Use values found on a real PowerMac */
316 /* Uninorth AGP bus */
317 uninorth_agp_dev = qdev_new(TYPE_UNI_NORTH_AGP_HOST_BRIDGE);
318 s = SYS_BUS_DEVICE(uninorth_agp_dev);
319 sysbus_realize_and_unref(s, &error_fatal);
320 sysbus_mmio_map(s, 0, 0xf0800000);
321 sysbus_mmio_map(s, 1, 0xf0c00000);
322
323 /* Uninorth internal bus */
324 uninorth_internal_dev = qdev_new(
325 TYPE_UNI_NORTH_INTERNAL_PCI_HOST_BRIDGE);
326 s = SYS_BUS_DEVICE(uninorth_internal_dev);
327 sysbus_realize_and_unref(s, &error_fatal);
328 sysbus_mmio_map(s, 0, 0xf4800000);
329 sysbus_mmio_map(s, 1, 0xf4c00000);
330
331 /* Uninorth main bus */
332 dev = qdev_new(TYPE_UNI_NORTH_PCI_HOST_BRIDGE);
333 qdev_prop_set_uint32(dev, "ofw-addr", 0xf2000000);
334 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
335 uninorth_pci = UNI_NORTH_PCI_HOST_BRIDGE(dev);
336 s = SYS_BUS_DEVICE(dev);
337 /* PCI hole */
338 memory_region_add_subregion(get_system_memory(), 0x80000000ULL,
339 sysbus_mmio_get_region(s, 2));
340 /* Register 8 MB of ISA IO space */
341 memory_region_add_subregion(get_system_memory(), 0xf2000000,
342 sysbus_mmio_get_region(s, 3));
343 sysbus_mmio_map(s, 0, 0xf2800000);
344 sysbus_mmio_map(s, 1, 0xf2c00000);
345
346 machine_arch = ARCH_MAC99;
347 }
348
349 machine->usb |= defaults_enabled() && !machine->usb_disabled;
350 has_pmu = (core99_machine->via_config != CORE99_VIA_CONFIG_CUDA);
351 has_adb = (core99_machine->via_config == CORE99_VIA_CONFIG_CUDA ||
352 core99_machine->via_config == CORE99_VIA_CONFIG_PMU_ADB);
353
354 /* Timebase Frequency */
355 if (kvm_enabled()) {
356 tbfreq = kvmppc_get_tbfreq();
357 } else {
358 tbfreq = TBFREQ;
359 }
360
361 /* init basic PC hardware */
362 pci_bus = PCI_HOST_BRIDGE(uninorth_pci)->bus;
363
364 /* MacIO */
365 macio = pci_new(-1, TYPE_NEWWORLD_MACIO);
366 dev = DEVICE(macio);
367 qdev_prop_set_uint64(dev, "frequency", tbfreq);
368 qdev_prop_set_bit(dev, "has-pmu", has_pmu);
369 qdev_prop_set_bit(dev, "has-adb", has_adb);
370
371 escc = ESCC(object_resolve_path_component(OBJECT(macio), "escc"));
372 qdev_prop_set_chr(DEVICE(escc), "chrA", serial_hd(0));
373 qdev_prop_set_chr(DEVICE(escc), "chrB", serial_hd(1));
374
375 pci_realize_and_unref(macio, pci_bus, &error_fatal);
376
377 pic_dev = DEVICE(object_resolve_path_component(OBJECT(macio), "pic"));
378 for (i = 0; i < 4; i++) {
379 qdev_connect_gpio_out(DEVICE(uninorth_pci), i,
380 qdev_get_gpio_in(pic_dev, 0x1b + i));
381 }
382
383 /* TODO: additional PCI buses only wired up for 32-bit machines */
384 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_970) {
385 /* Uninorth AGP bus */
386 for (i = 0; i < 4; i++) {
387 qdev_connect_gpio_out(uninorth_agp_dev, i,
388 qdev_get_gpio_in(pic_dev, 0x1b + i));
389 }
390
391 /* Uninorth internal bus */
392 for (i = 0; i < 4; i++) {
393 qdev_connect_gpio_out(uninorth_internal_dev, i,
394 qdev_get_gpio_in(pic_dev, 0x1b + i));
395 }
396 }
397
398 /* OpenPIC */
399 s = SYS_BUS_DEVICE(pic_dev);
400 k = 0;
401 for (i = 0; i < smp_cpus; i++) {
402 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
403 sysbus_connect_irq(s, k++, openpic_irqs[i].irq[j]);
404 }
405 }
406 g_free(openpic_irqs);
407
408 /* We only emulate 2 out of 3 IDE controllers for now */
409 ide_drive_get(hd, ARRAY_SIZE(hd));
410
411 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
412 "ide[0]"));
413 macio_ide_init_drives(macio_ide, hd);
414
415 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
416 "ide[1]"));
417 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]);
418
419 if (has_adb) {
420 if (has_pmu) {
421 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "pmu"));
422 } else {
423 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
424 }
425
426 adb_bus = qdev_get_child_bus(dev, "adb.0");
427 dev = qdev_new(TYPE_ADB_KEYBOARD);
428 qdev_realize_and_unref(dev, adb_bus, &error_fatal);
429
430 dev = qdev_new(TYPE_ADB_MOUSE);
431 qdev_realize_and_unref(dev, adb_bus, &error_fatal);
432 }
433
434 if (machine->usb) {
435 pci_create_simple(pci_bus, -1, "pci-ohci");
436
437 /* U3 needs to use USB for input because Linux doesn't support via-cuda
438 on PPC64 */
439 if (!has_adb || machine_arch == ARCH_MAC99_U3) {
440 USBBus *usb_bus = usb_bus_find(-1);
441
442 usb_create_simple(usb_bus, "usb-kbd");
443 usb_create_simple(usb_bus, "usb-mouse");
444 }
445 }
446
447 pci_vga_init(pci_bus);
448
449 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8) {
450 graphic_depth = 15;
451 }
452
453 for (i = 0; i < nb_nics; i++) {
454 pci_nic_init_nofail(&nd_table[i], pci_bus, "sungem", NULL);
455 }
456
457 /* The NewWorld NVRAM is not located in the MacIO device */
458 if (kvm_enabled() && qemu_real_host_page_size() > 4096) {
459 /* We can't combine read-write and read-only in a single page, so
460 move the NVRAM out of ROM again for KVM */
461 nvram_addr = 0xFFE00000;
462 }
463 dev = qdev_new(TYPE_MACIO_NVRAM);
464 qdev_prop_set_uint32(dev, "size", 0x2000);
465 qdev_prop_set_uint32(dev, "it_shift", 1);
466 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
467 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, nvram_addr);
468 nvr = MACIO_NVRAM(dev);
469 pmac_format_nvram_partition(nvr, 0x2000);
470 /* No PCI init: the BIOS will do it */
471
472 dev = qdev_new(TYPE_FW_CFG_MEM);
473 fw_cfg = FW_CFG(dev);
474 qdev_prop_set_uint32(dev, "data_width", 1);
475 qdev_prop_set_bit(dev, "dma_enabled", false);
476 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
477 OBJECT(fw_cfg));
478 s = SYS_BUS_DEVICE(dev);
479 sysbus_realize_and_unref(s, &error_fatal);
480 sysbus_mmio_map(s, 0, CFG_ADDR);
481 sysbus_mmio_map(s, 1, CFG_ADDR + 2);
482
483 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
484 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
485 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
486 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch);
487 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
488 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
489 if (kernel_cmdline) {
490 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
491 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE, kernel_cmdline);
492 } else {
493 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
494 }
495 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
496 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
497 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
498
499 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
500 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
501 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
502
503 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_VIACONFIG, core99_machine->via_config);
504
505 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
506 if (kvm_enabled()) {
507 uint8_t *hypercall;
508
509 hypercall = g_malloc(16);
510 kvmppc_get_hypercall(env, hypercall, 16);
511 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
512 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
513 }
514 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq);
515 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */
516 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ);
517 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ);
518 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_NVRAM_ADDR, nvram_addr);
519
520 /* MacOS NDRV VGA driver */
521 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME);
522 if (filename) {
523 gchar *ndrv_file;
524 gsize ndrv_size;
525
526 if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) {
527 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size);
528 }
529 g_free(filename);
530 }
531
532 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
533 }
534
535 /*
536 * Implementation of an interface to adjust firmware path
537 * for the bootindex property handling.
538 */
539 static char *core99_fw_dev_path(FWPathProvider *p, BusState *bus,
540 DeviceState *dev)
541 {
542 PCIDevice *pci;
543 MACIOIDEState *macio_ide;
544
545 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-newworld")) {
546 pci = PCI_DEVICE(dev);
547 return g_strdup_printf("mac-io@%x", PCI_SLOT(pci->devfn));
548 }
549
550 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-ide")) {
551 macio_ide = MACIO_IDE(dev);
552 return g_strdup_printf("ata-3@%x", macio_ide->addr);
553 }
554
555 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) {
556 return g_strdup("disk");
557 }
558
559 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) {
560 return g_strdup("cdrom");
561 }
562
563 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) {
564 return g_strdup("disk");
565 }
566
567 return NULL;
568 }
569 static int core99_kvm_type(MachineState *machine, const char *arg)
570 {
571 /* Always force PR KVM */
572 return 2;
573 }
574
575 static void core99_machine_class_init(ObjectClass *oc, void *data)
576 {
577 MachineClass *mc = MACHINE_CLASS(oc);
578 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
579
580 mc->desc = "Mac99 based PowerMAC";
581 mc->init = ppc_core99_init;
582 mc->block_default_type = IF_IDE;
583 /* SMP is not supported currently */
584 mc->max_cpus = 1;
585 mc->default_boot_order = "cd";
586 mc->default_display = "std";
587 mc->kvm_type = core99_kvm_type;
588 #ifdef TARGET_PPC64
589 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("970fx_v3.1");
590 #else
591 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("7400_v2.9");
592 #endif
593 mc->default_ram_id = "ppc_core99.ram";
594 mc->ignore_boot_device_suffixes = true;
595 fwc->get_dev_path = core99_fw_dev_path;
596 }
597
598 static char *core99_get_via_config(Object *obj, Error **errp)
599 {
600 Core99MachineState *cms = CORE99_MACHINE(obj);
601
602 switch (cms->via_config) {
603 default:
604 case CORE99_VIA_CONFIG_CUDA:
605 return g_strdup("cuda");
606
607 case CORE99_VIA_CONFIG_PMU:
608 return g_strdup("pmu");
609
610 case CORE99_VIA_CONFIG_PMU_ADB:
611 return g_strdup("pmu-adb");
612 }
613 }
614
615 static void core99_set_via_config(Object *obj, const char *value, Error **errp)
616 {
617 Core99MachineState *cms = CORE99_MACHINE(obj);
618
619 if (!strcmp(value, "cuda")) {
620 cms->via_config = CORE99_VIA_CONFIG_CUDA;
621 } else if (!strcmp(value, "pmu")) {
622 cms->via_config = CORE99_VIA_CONFIG_PMU;
623 } else if (!strcmp(value, "pmu-adb")) {
624 cms->via_config = CORE99_VIA_CONFIG_PMU_ADB;
625 } else {
626 error_setg(errp, "Invalid via value");
627 error_append_hint(errp, "Valid values are cuda, pmu, pmu-adb.\n");
628 }
629 }
630
631 static void core99_instance_init(Object *obj)
632 {
633 Core99MachineState *cms = CORE99_MACHINE(obj);
634
635 /* Default via_config is CORE99_VIA_CONFIG_CUDA */
636 cms->via_config = CORE99_VIA_CONFIG_CUDA;
637 object_property_add_str(obj, "via", core99_get_via_config,
638 core99_set_via_config);
639 object_property_set_description(obj, "via",
640 "Set VIA configuration. "
641 "Valid values are cuda, pmu and pmu-adb");
642
643 return;
644 }
645
646 static const TypeInfo core99_machine_info = {
647 .name = MACHINE_TYPE_NAME("mac99"),
648 .parent = TYPE_MACHINE,
649 .class_init = core99_machine_class_init,
650 .instance_init = core99_instance_init,
651 .instance_size = sizeof(Core99MachineState),
652 .interfaces = (InterfaceInfo[]) {
653 { TYPE_FW_PATH_PROVIDER },
654 { }
655 },
656 };
657
658 static void mac_machine_register_types(void)
659 {
660 type_register_static(&core99_machine_info);
661 }
662
663 type_init(mac_machine_register_types)