Merge tag 'pull-target-arm-20211129' of https://git.linaro.org/people/pmaydell/qemu...
[qemu.git] / hw / ppc / mac_oldworld.c
1
2 /*
3 * QEMU OldWorld PowerMac (currently ~G3 Beige) hardware System Emulator
4 *
5 * Copyright (c) 2004-2007 Fabrice Bellard
6 * Copyright (c) 2007 Jocelyn Mayer
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27 #include "qemu/osdep.h"
28 #include "qemu-common.h"
29 #include "qemu/datadir.h"
30 #include "qemu/units.h"
31 #include "qapi/error.h"
32 #include "hw/ppc/ppc.h"
33 #include "hw/qdev-properties.h"
34 #include "mac.h"
35 #include "hw/input/adb.h"
36 #include "sysemu/sysemu.h"
37 #include "net/net.h"
38 #include "hw/isa/isa.h"
39 #include "hw/pci/pci.h"
40 #include "hw/pci/pci_host.h"
41 #include "hw/nvram/fw_cfg.h"
42 #include "hw/char/escc.h"
43 #include "hw/misc/macio/macio.h"
44 #include "hw/loader.h"
45 #include "hw/fw-path-provider.h"
46 #include "elf.h"
47 #include "qemu/error-report.h"
48 #include "sysemu/kvm.h"
49 #include "sysemu/reset.h"
50 #include "kvm_ppc.h"
51
52 #define MAX_IDE_BUS 2
53 #define CFG_ADDR 0xf0000510
54 #define TBFREQ 16600000UL
55 #define CLOCKFREQ 266000000UL
56 #define BUSFREQ 66000000UL
57
58 #define NDRV_VGA_FILENAME "qemu_vga.ndrv"
59
60 #define GRACKLE_BASE 0xfec00000
61 #define PROM_BASE 0xffc00000
62 #define PROM_SIZE (4 * MiB)
63
64 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
65 Error **errp)
66 {
67 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
68 }
69
70 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
71 {
72 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
73 }
74
75 static void ppc_heathrow_reset(void *opaque)
76 {
77 PowerPCCPU *cpu = opaque;
78
79 cpu_reset(CPU(cpu));
80 }
81
82 static void ppc_heathrow_init(MachineState *machine)
83 {
84 ram_addr_t ram_size = machine->ram_size;
85 const char *bios_name = machine->firmware ?: PROM_FILENAME;
86 const char *boot_device = machine->boot_order;
87 PowerPCCPU *cpu = NULL;
88 CPUPPCState *env = NULL;
89 char *filename;
90 int i;
91 MemoryRegion *bios = g_new(MemoryRegion, 1);
92 uint32_t kernel_base, initrd_base, cmdline_base = 0;
93 int32_t kernel_size, initrd_size;
94 PCIBus *pci_bus;
95 PCIDevice *macio;
96 MACIOIDEState *macio_ide;
97 ESCCState *escc;
98 SysBusDevice *s;
99 DeviceState *dev, *pic_dev, *grackle_dev;
100 BusState *adb_bus;
101 uint64_t bios_addr;
102 int bios_size;
103 unsigned int smp_cpus = machine->smp.cpus;
104 uint16_t ppc_boot_device;
105 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
106 void *fw_cfg;
107 uint64_t tbfreq;
108
109 /* init CPUs */
110 for (i = 0; i < smp_cpus; i++) {
111 cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
112 env = &cpu->env;
113
114 /* Set time-base frequency to 16.6 Mhz */
115 cpu_ppc_tb_init(env, TBFREQ);
116 qemu_register_reset(ppc_heathrow_reset, cpu);
117 }
118
119 /* allocate RAM */
120 if (ram_size > 2047 * MiB) {
121 error_report("Too much memory for this machine: %" PRId64 " MB, "
122 "maximum 2047 MB", ram_size / MiB);
123 exit(1);
124 }
125
126 memory_region_add_subregion(get_system_memory(), 0, machine->ram);
127
128 /* allocate and load firmware ROM */
129 memory_region_init_rom(bios, NULL, "ppc_heathrow.bios", PROM_SIZE,
130 &error_fatal);
131 memory_region_add_subregion(get_system_memory(), PROM_BASE, bios);
132
133 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
134 if (filename) {
135 /* Load OpenBIOS (ELF) */
136 bios_size = load_elf(filename, NULL, NULL, NULL, NULL, &bios_addr,
137 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0);
138 /* Unfortunately, load_elf sign-extends reading elf32 */
139 bios_addr = (uint32_t)bios_addr;
140
141 if (bios_size <= 0) {
142 /* or if could not load ELF try loading a binary ROM image */
143 bios_size = load_image_targphys(filename, PROM_BASE, PROM_SIZE);
144 bios_addr = PROM_BASE;
145 }
146 g_free(filename);
147 } else {
148 bios_size = -1;
149 }
150 if (bios_size < 0 || bios_addr - PROM_BASE + bios_size > PROM_SIZE) {
151 error_report("could not load PowerPC bios '%s'", bios_name);
152 exit(1);
153 }
154
155 if (machine->kernel_filename) {
156 int bswap_needed;
157
158 #ifdef BSWAP_NEEDED
159 bswap_needed = 1;
160 #else
161 bswap_needed = 0;
162 #endif
163 kernel_base = KERNEL_LOAD_ADDR;
164 kernel_size = load_elf(machine->kernel_filename, NULL,
165 translate_kernel_address, NULL, NULL, NULL,
166 NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0);
167 if (kernel_size < 0)
168 kernel_size = load_aout(machine->kernel_filename, kernel_base,
169 ram_size - kernel_base, bswap_needed,
170 TARGET_PAGE_SIZE);
171 if (kernel_size < 0)
172 kernel_size = load_image_targphys(machine->kernel_filename,
173 kernel_base,
174 ram_size - kernel_base);
175 if (kernel_size < 0) {
176 error_report("could not load kernel '%s'",
177 machine->kernel_filename);
178 exit(1);
179 }
180 /* load initrd */
181 if (machine->initrd_filename) {
182 initrd_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size +
183 KERNEL_GAP);
184 initrd_size = load_image_targphys(machine->initrd_filename,
185 initrd_base,
186 ram_size - initrd_base);
187 if (initrd_size < 0) {
188 error_report("could not load initial ram disk '%s'",
189 machine->initrd_filename);
190 exit(1);
191 }
192 cmdline_base = TARGET_PAGE_ALIGN(initrd_base + initrd_size);
193 } else {
194 initrd_base = 0;
195 initrd_size = 0;
196 cmdline_base = TARGET_PAGE_ALIGN(kernel_base + kernel_size + KERNEL_GAP);
197 }
198 ppc_boot_device = 'm';
199 } else {
200 kernel_base = 0;
201 kernel_size = 0;
202 initrd_base = 0;
203 initrd_size = 0;
204 ppc_boot_device = '\0';
205 for (i = 0; boot_device[i] != '\0'; i++) {
206 /* TOFIX: for now, the second IDE channel is not properly
207 * used by OHW. The Mac floppy disk are not emulated.
208 * For now, OHW cannot boot from the network.
209 */
210 #if 0
211 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
212 ppc_boot_device = boot_device[i];
213 break;
214 }
215 #else
216 if (boot_device[i] >= 'c' && boot_device[i] <= 'd') {
217 ppc_boot_device = boot_device[i];
218 break;
219 }
220 #endif
221 }
222 if (ppc_boot_device == '\0') {
223 error_report("No valid boot device for G3 Beige machine");
224 exit(1);
225 }
226 }
227
228 /* Timebase Frequency */
229 if (kvm_enabled()) {
230 tbfreq = kvmppc_get_tbfreq();
231 } else {
232 tbfreq = TBFREQ;
233 }
234
235 /* Grackle PCI host bridge */
236 grackle_dev = qdev_new(TYPE_GRACKLE_PCI_HOST_BRIDGE);
237 qdev_prop_set_uint32(grackle_dev, "ofw-addr", 0x80000000);
238 s = SYS_BUS_DEVICE(grackle_dev);
239 sysbus_realize_and_unref(s, &error_fatal);
240
241 sysbus_mmio_map(s, 0, GRACKLE_BASE);
242 sysbus_mmio_map(s, 1, GRACKLE_BASE + 0x200000);
243 /* PCI hole */
244 memory_region_add_subregion(get_system_memory(), 0x80000000ULL,
245 sysbus_mmio_get_region(s, 2));
246 /* Register 2 MB of ISA IO space */
247 memory_region_add_subregion(get_system_memory(), 0xfe000000,
248 sysbus_mmio_get_region(s, 3));
249
250 pci_bus = PCI_HOST_BRIDGE(grackle_dev)->bus;
251
252 /* MacIO */
253 macio = pci_new(PCI_DEVFN(16, 0), TYPE_OLDWORLD_MACIO);
254 dev = DEVICE(macio);
255 qdev_prop_set_uint64(dev, "frequency", tbfreq);
256
257 escc = ESCC(object_resolve_path_component(OBJECT(macio), "escc"));
258 qdev_prop_set_chr(DEVICE(escc), "chrA", serial_hd(0));
259 qdev_prop_set_chr(DEVICE(escc), "chrB", serial_hd(1));
260
261 pci_realize_and_unref(macio, pci_bus, &error_fatal);
262
263 pic_dev = DEVICE(object_resolve_path_component(OBJECT(macio), "pic"));
264 for (i = 0; i < 4; i++) {
265 qdev_connect_gpio_out(grackle_dev, i,
266 qdev_get_gpio_in(pic_dev, 0x15 + i));
267 }
268
269 /* Connect the heathrow PIC outputs to the 6xx bus */
270 for (i = 0; i < smp_cpus; i++) {
271 switch (PPC_INPUT(env)) {
272 case PPC_FLAGS_INPUT_6xx:
273 /* XXX: we register only 1 output pin for heathrow PIC */
274 qdev_connect_gpio_out(pic_dev, 0,
275 ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT]);
276 break;
277 default:
278 error_report("Bus model not supported on OldWorld Mac machine");
279 exit(1);
280 }
281 }
282
283 pci_vga_init(pci_bus);
284
285 for (i = 0; i < nb_nics; i++) {
286 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
287 }
288
289 /* MacIO IDE */
290 ide_drive_get(hd, ARRAY_SIZE(hd));
291 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
292 "ide[0]"));
293 macio_ide_init_drives(macio_ide, hd);
294
295 macio_ide = MACIO_IDE(object_resolve_path_component(OBJECT(macio),
296 "ide[1]"));
297 macio_ide_init_drives(macio_ide, &hd[MAX_IDE_DEVS]);
298
299 /* MacIO CUDA/ADB */
300 dev = DEVICE(object_resolve_path_component(OBJECT(macio), "cuda"));
301 adb_bus = qdev_get_child_bus(dev, "adb.0");
302 dev = qdev_new(TYPE_ADB_KEYBOARD);
303 qdev_realize_and_unref(dev, adb_bus, &error_fatal);
304 dev = qdev_new(TYPE_ADB_MOUSE);
305 qdev_realize_and_unref(dev, adb_bus, &error_fatal);
306
307 if (machine_usb(machine)) {
308 pci_create_simple(pci_bus, -1, "pci-ohci");
309 }
310
311 if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
312 graphic_depth = 15;
313
314 /* No PCI init: the BIOS will do it */
315
316 dev = qdev_new(TYPE_FW_CFG_MEM);
317 fw_cfg = FW_CFG(dev);
318 qdev_prop_set_uint32(dev, "data_width", 1);
319 qdev_prop_set_bit(dev, "dma_enabled", false);
320 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
321 OBJECT(fw_cfg));
322 s = SYS_BUS_DEVICE(dev);
323 sysbus_realize_and_unref(s, &error_fatal);
324 sysbus_mmio_map(s, 0, CFG_ADDR);
325 sysbus_mmio_map(s, 1, CFG_ADDR + 2);
326
327 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
328 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
329 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
330 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_HEATHROW);
331 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
332 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
333 if (machine->kernel_cmdline) {
334 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, cmdline_base);
335 pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
336 machine->kernel_cmdline);
337 } else {
338 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
339 }
340 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
341 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
342 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, ppc_boot_device);
343
344 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
345 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
346 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
347
348 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
349 if (kvm_enabled()) {
350 uint8_t *hypercall;
351
352 hypercall = g_malloc(16);
353 kvmppc_get_hypercall(env, hypercall, 16);
354 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
355 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
356 }
357 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, tbfreq);
358 /* Mac OS X requires a "known good" clock-frequency value; pass it one. */
359 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_CLOCKFREQ, CLOCKFREQ);
360 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_BUSFREQ, BUSFREQ);
361
362 /* MacOS NDRV VGA driver */
363 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, NDRV_VGA_FILENAME);
364 if (filename) {
365 gchar *ndrv_file;
366 gsize ndrv_size;
367
368 if (g_file_get_contents(filename, &ndrv_file, &ndrv_size, NULL)) {
369 fw_cfg_add_file(fw_cfg, "ndrv/qemu_vga.ndrv", ndrv_file, ndrv_size);
370 }
371 g_free(filename);
372 }
373
374 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
375 }
376
377 /*
378 * Implementation of an interface to adjust firmware path
379 * for the bootindex property handling.
380 */
381 static char *heathrow_fw_dev_path(FWPathProvider *p, BusState *bus,
382 DeviceState *dev)
383 {
384 PCIDevice *pci;
385 MACIOIDEState *macio_ide;
386
387 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-oldworld")) {
388 pci = PCI_DEVICE(dev);
389 return g_strdup_printf("mac-io@%x", PCI_SLOT(pci->devfn));
390 }
391
392 if (!strcmp(object_get_typename(OBJECT(dev)), "macio-ide")) {
393 macio_ide = MACIO_IDE(dev);
394 return g_strdup_printf("ata-3@%x", macio_ide->addr);
395 }
396
397 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) {
398 return g_strdup("disk");
399 }
400
401 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) {
402 return g_strdup("cdrom");
403 }
404
405 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) {
406 return g_strdup("disk");
407 }
408
409 return NULL;
410 }
411
412 static int heathrow_kvm_type(MachineState *machine, const char *arg)
413 {
414 /* Always force PR KVM */
415 return 2;
416 }
417
418 static void heathrow_class_init(ObjectClass *oc, void *data)
419 {
420 MachineClass *mc = MACHINE_CLASS(oc);
421 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
422
423 mc->desc = "Heathrow based PowerMAC";
424 mc->init = ppc_heathrow_init;
425 mc->block_default_type = IF_IDE;
426 mc->max_cpus = MAX_CPUS;
427 #ifndef TARGET_PPC64
428 mc->is_default = true;
429 #endif
430 /* TOFIX "cad" when Mac floppy is implemented */
431 mc->default_boot_order = "cd";
432 mc->kvm_type = heathrow_kvm_type;
433 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("750_v3.1");
434 mc->default_display = "std";
435 mc->ignore_boot_device_suffixes = true;
436 mc->default_ram_id = "ppc_heathrow.ram";
437 fwc->get_dev_path = heathrow_fw_dev_path;
438 }
439
440 static const TypeInfo ppc_heathrow_machine_info = {
441 .name = MACHINE_TYPE_NAME("g3beige"),
442 .parent = TYPE_MACHINE,
443 .class_init = heathrow_class_init,
444 .interfaces = (InterfaceInfo[]) {
445 { TYPE_FW_PATH_PROVIDER },
446 { }
447 },
448 };
449
450 static void ppc_heathrow_register_types(void)
451 {
452 type_register_static(&ppc_heathrow_machine_info);
453 }
454
455 type_init(ppc_heathrow_register_types);