ppc/pnv: add memory regions for the ICP registers
[qemu.git] / hw / ppc / pnv.c
1 /*
2 * QEMU PowerPC PowerNV machine model
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "sysemu/sysemu.h"
23 #include "sysemu/numa.h"
24 #include "sysemu/cpus.h"
25 #include "hw/hw.h"
26 #include "target/ppc/cpu.h"
27 #include "qemu/log.h"
28 #include "hw/ppc/fdt.h"
29 #include "hw/ppc/ppc.h"
30 #include "hw/ppc/pnv.h"
31 #include "hw/ppc/pnv_core.h"
32 #include "hw/loader.h"
33 #include "exec/address-spaces.h"
34 #include "qemu/cutils.h"
35 #include "qapi/visitor.h"
36 #include "monitor/monitor.h"
37 #include "hw/intc/intc.h"
38
39 #include "hw/ppc/xics.h"
40 #include "hw/ppc/pnv_xscom.h"
41
42 #include "hw/isa/isa.h"
43 #include "hw/char/serial.h"
44 #include "hw/timer/mc146818rtc.h"
45
46 #include <libfdt.h>
47
48 #define FDT_MAX_SIZE 0x00100000
49
50 #define FW_FILE_NAME "skiboot.lid"
51 #define FW_LOAD_ADDR 0x0
52 #define FW_MAX_SIZE 0x00400000
53
54 #define KERNEL_LOAD_ADDR 0x20000000
55 #define INITRD_LOAD_ADDR 0x40000000
56
57 /*
58 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
59 * 4 * 4 sockets * 12 cores * 8 threads = 1536
60 * Let's make it 2^11
61 */
62 #define MAX_CPUS 2048
63
64 /*
65 * Memory nodes are created by hostboot, one for each range of memory
66 * that has a different "affinity". In practice, it means one range
67 * per chip.
68 */
69 static void powernv_populate_memory_node(void *fdt, int chip_id, hwaddr start,
70 hwaddr size)
71 {
72 char *mem_name;
73 uint64_t mem_reg_property[2];
74 int off;
75
76 mem_reg_property[0] = cpu_to_be64(start);
77 mem_reg_property[1] = cpu_to_be64(size);
78
79 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
80 off = fdt_add_subnode(fdt, 0, mem_name);
81 g_free(mem_name);
82
83 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
84 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
85 sizeof(mem_reg_property))));
86 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
87 }
88
89 static int get_cpus_node(void *fdt)
90 {
91 int cpus_offset = fdt_path_offset(fdt, "/cpus");
92
93 if (cpus_offset < 0) {
94 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
95 "cpus");
96 if (cpus_offset) {
97 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
98 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
99 }
100 }
101 _FDT(cpus_offset);
102 return cpus_offset;
103 }
104
105 /*
106 * The PowerNV cores (and threads) need to use real HW ids and not an
107 * incremental index like it has been done on other platforms. This HW
108 * id is stored in the CPU PIR, it is used to create cpu nodes in the
109 * device tree, used in XSCOM to address cores and in interrupt
110 * servers.
111 */
112 static void powernv_create_core_node(PnvChip *chip, PnvCore *pc, void *fdt)
113 {
114 CPUState *cs = CPU(DEVICE(pc->threads));
115 DeviceClass *dc = DEVICE_GET_CLASS(cs);
116 PowerPCCPU *cpu = POWERPC_CPU(cs);
117 int smt_threads = CPU_CORE(pc)->nr_threads;
118 CPUPPCState *env = &cpu->env;
119 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
120 uint32_t servers_prop[smt_threads];
121 int i;
122 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
123 0xffffffff, 0xffffffff};
124 uint32_t tbfreq = PNV_TIMEBASE_FREQ;
125 uint32_t cpufreq = 1000000000;
126 uint32_t page_sizes_prop[64];
127 size_t page_sizes_prop_size;
128 const uint8_t pa_features[] = { 24, 0,
129 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
130 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
131 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
132 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
133 int offset;
134 char *nodename;
135 int cpus_offset = get_cpus_node(fdt);
136
137 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
138 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
139 _FDT(offset);
140 g_free(nodename);
141
142 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
143
144 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
145 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
146 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
147
148 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
149 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
150 env->dcache_line_size)));
151 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
152 env->dcache_line_size)));
153 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
154 env->icache_line_size)));
155 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
156 env->icache_line_size)));
157
158 if (pcc->l1_dcache_size) {
159 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
160 pcc->l1_dcache_size)));
161 } else {
162 error_report("Warning: Unknown L1 dcache size for cpu");
163 }
164 if (pcc->l1_icache_size) {
165 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
166 pcc->l1_icache_size)));
167 } else {
168 error_report("Warning: Unknown L1 icache size for cpu");
169 }
170
171 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
172 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
173 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
174 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
175 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
176
177 if (env->spr_cb[SPR_PURR].oea_read) {
178 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
179 }
180
181 if (env->mmu_model & POWERPC_MMU_1TSEG) {
182 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
183 segs, sizeof(segs))));
184 }
185
186 /* Advertise VMX/VSX (vector extensions) if available
187 * 0 / no property == no vector extensions
188 * 1 == VMX / Altivec available
189 * 2 == VSX available */
190 if (env->insns_flags & PPC_ALTIVEC) {
191 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
192
193 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
194 }
195
196 /* Advertise DFP (Decimal Floating Point) if available
197 * 0 / no property == no DFP
198 * 1 == DFP available */
199 if (env->insns_flags2 & PPC2_DFP) {
200 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
201 }
202
203 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
204 sizeof(page_sizes_prop));
205 if (page_sizes_prop_size) {
206 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
207 page_sizes_prop, page_sizes_prop_size)));
208 }
209
210 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
211 pa_features, sizeof(pa_features))));
212
213 /* Build interrupt servers properties */
214 for (i = 0; i < smt_threads; i++) {
215 servers_prop[i] = cpu_to_be32(pc->pir + i);
216 }
217 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
218 servers_prop, sizeof(servers_prop))));
219 }
220
221 static void powernv_populate_icp(PnvChip *chip, void *fdt, uint32_t pir,
222 uint32_t nr_threads)
223 {
224 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
225 char *name;
226 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
227 uint32_t irange[2], i, rsize;
228 uint64_t *reg;
229 int offset;
230
231 irange[0] = cpu_to_be32(pir);
232 irange[1] = cpu_to_be32(nr_threads);
233
234 rsize = sizeof(uint64_t) * 2 * nr_threads;
235 reg = g_malloc(rsize);
236 for (i = 0; i < nr_threads; i++) {
237 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
238 reg[i * 2 + 1] = cpu_to_be64(0x1000);
239 }
240
241 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
242 offset = fdt_add_subnode(fdt, 0, name);
243 _FDT(offset);
244 g_free(name);
245
246 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
247 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
248 _FDT((fdt_setprop_string(fdt, offset, "device_type",
249 "PowerPC-External-Interrupt-Presentation")));
250 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
251 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
252 irange, sizeof(irange))));
253 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
254 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
255 g_free(reg);
256 }
257
258 static void powernv_populate_chip(PnvChip *chip, void *fdt)
259 {
260 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
261 char *typename = pnv_core_typename(pcc->cpu_model);
262 size_t typesize = object_type_get_instance_size(typename);
263 int i;
264
265 pnv_xscom_populate(chip, fdt, 0);
266
267 for (i = 0; i < chip->nr_cores; i++) {
268 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
269
270 powernv_create_core_node(chip, pnv_core, fdt);
271
272 /* Interrupt Control Presenters (ICP). One per core. */
273 powernv_populate_icp(chip, fdt, pnv_core->pir,
274 CPU_CORE(pnv_core)->nr_threads);
275 }
276
277 if (chip->ram_size) {
278 powernv_populate_memory_node(fdt, chip->chip_id, chip->ram_start,
279 chip->ram_size);
280 }
281 g_free(typename);
282 }
283
284 static void *powernv_create_fdt(MachineState *machine)
285 {
286 const char plat_compat[] = "qemu,powernv\0ibm,powernv";
287 PnvMachineState *pnv = POWERNV_MACHINE(machine);
288 void *fdt;
289 char *buf;
290 int off;
291 int i;
292
293 fdt = g_malloc0(FDT_MAX_SIZE);
294 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
295
296 /* Root node */
297 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
298 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
299 _FDT((fdt_setprop_string(fdt, 0, "model",
300 "IBM PowerNV (emulated by qemu)")));
301 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat,
302 sizeof(plat_compat))));
303
304 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
305 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
306 if (qemu_uuid_set) {
307 _FDT((fdt_property_string(fdt, "system-id", buf)));
308 }
309 g_free(buf);
310
311 off = fdt_add_subnode(fdt, 0, "chosen");
312 if (machine->kernel_cmdline) {
313 _FDT((fdt_setprop_string(fdt, off, "bootargs",
314 machine->kernel_cmdline)));
315 }
316
317 if (pnv->initrd_size) {
318 uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
319 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
320
321 _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
322 &start_prop, sizeof(start_prop))));
323 _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
324 &end_prop, sizeof(end_prop))));
325 }
326
327 /* Populate device tree for each chip */
328 for (i = 0; i < pnv->num_chips; i++) {
329 powernv_populate_chip(pnv->chips[i], fdt);
330 }
331 return fdt;
332 }
333
334 static void ppc_powernv_reset(void)
335 {
336 MachineState *machine = MACHINE(qdev_get_machine());
337 void *fdt;
338
339 qemu_devices_reset();
340
341 fdt = powernv_create_fdt(machine);
342
343 /* Pack resulting tree */
344 _FDT((fdt_pack(fdt)));
345
346 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
347 }
348
349 /* If we don't use the built-in LPC interrupt deserializer, we need
350 * to provide a set of qirqs for the ISA bus or things will go bad.
351 *
352 * Most machines using pre-Naples chips (without said deserializer)
353 * have a CPLD that will collect the SerIRQ and shoot them as a
354 * single level interrupt to the P8 chip. So let's setup a hook
355 * for doing just that.
356 *
357 * Note: The actual interrupt input isn't emulated yet, this will
358 * come with the PSI bridge model.
359 */
360 static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level)
361 {
362 /* We don't yet emulate the PSI bridge which provides the external
363 * interrupt, so just drop interrupts on the floor
364 */
365 }
366
367 static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level)
368 {
369 /* XXX TODO */
370 }
371
372 static ISABus *pnv_isa_create(PnvChip *chip)
373 {
374 PnvLpcController *lpc = &chip->lpc;
375 ISABus *isa_bus;
376 qemu_irq *irqs;
377 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
378
379 /* let isa_bus_new() create its own bridge on SysBus otherwise
380 * devices speficied on the command line won't find the bus and
381 * will fail to create.
382 */
383 isa_bus = isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io,
384 &error_fatal);
385
386 /* Not all variants have a working serial irq decoder. If not,
387 * handling of LPC interrupts becomes a platform issue (some
388 * platforms have a CPLD to do it).
389 */
390 if (pcc->chip_type == PNV_CHIP_POWER8NVL) {
391 irqs = qemu_allocate_irqs(pnv_lpc_isa_irq_handler, chip, ISA_NUM_IRQS);
392 } else {
393 irqs = qemu_allocate_irqs(pnv_lpc_isa_irq_handler_cpld, chip,
394 ISA_NUM_IRQS);
395 }
396
397 isa_bus_irqs(isa_bus, irqs);
398 return isa_bus;
399 }
400
401 static void ppc_powernv_init(MachineState *machine)
402 {
403 PnvMachineState *pnv = POWERNV_MACHINE(machine);
404 MemoryRegion *ram;
405 char *fw_filename;
406 long fw_size;
407 int i;
408 char *chip_typename;
409
410 /* allocate RAM */
411 if (machine->ram_size < (1 * G_BYTE)) {
412 error_report("Warning: skiboot may not work with < 1GB of RAM");
413 }
414
415 ram = g_new(MemoryRegion, 1);
416 memory_region_allocate_system_memory(ram, NULL, "ppc_powernv.ram",
417 machine->ram_size);
418 memory_region_add_subregion(get_system_memory(), 0, ram);
419
420 /* load skiboot firmware */
421 if (bios_name == NULL) {
422 bios_name = FW_FILE_NAME;
423 }
424
425 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
426
427 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE);
428 if (fw_size < 0) {
429 error_report("Could not load OPAL '%s'", fw_filename);
430 exit(1);
431 }
432 g_free(fw_filename);
433
434 /* load kernel */
435 if (machine->kernel_filename) {
436 long kernel_size;
437
438 kernel_size = load_image_targphys(machine->kernel_filename,
439 KERNEL_LOAD_ADDR, 0x2000000);
440 if (kernel_size < 0) {
441 error_report("Could not load kernel '%s'",
442 machine->kernel_filename);
443 exit(1);
444 }
445 }
446
447 /* load initrd */
448 if (machine->initrd_filename) {
449 pnv->initrd_base = INITRD_LOAD_ADDR;
450 pnv->initrd_size = load_image_targphys(machine->initrd_filename,
451 pnv->initrd_base, 0x10000000); /* 128MB max */
452 if (pnv->initrd_size < 0) {
453 error_report("Could not load initial ram disk '%s'",
454 machine->initrd_filename);
455 exit(1);
456 }
457 }
458
459 /* We need some cpu model to instantiate the PnvChip class */
460 if (machine->cpu_model == NULL) {
461 machine->cpu_model = "POWER8";
462 }
463
464 /* Create the processor chips */
465 chip_typename = g_strdup_printf(TYPE_PNV_CHIP "-%s", machine->cpu_model);
466 if (!object_class_by_name(chip_typename)) {
467 error_report("qemu: invalid CPU model '%s' for %s machine",
468 machine->cpu_model, MACHINE_GET_CLASS(machine)->name);
469 exit(1);
470 }
471
472 pnv->chips = g_new0(PnvChip *, pnv->num_chips);
473 for (i = 0; i < pnv->num_chips; i++) {
474 char chip_name[32];
475 Object *chip = object_new(chip_typename);
476
477 pnv->chips[i] = PNV_CHIP(chip);
478
479 /* TODO: put all the memory in one node on chip 0 until we find a
480 * way to specify different ranges for each chip
481 */
482 if (i == 0) {
483 object_property_set_int(chip, machine->ram_size, "ram-size",
484 &error_fatal);
485 }
486
487 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i));
488 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal);
489 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id",
490 &error_fatal);
491 object_property_set_int(chip, smp_cores, "nr-cores", &error_fatal);
492 object_property_set_bool(chip, true, "realized", &error_fatal);
493 }
494 g_free(chip_typename);
495
496 /* Instantiate ISA bus on chip 0 */
497 pnv->isa_bus = pnv_isa_create(pnv->chips[0]);
498
499 /* Create serial port */
500 serial_hds_isa_init(pnv->isa_bus, 0, MAX_SERIAL_PORTS);
501
502 /* Create an RTC ISA device too */
503 rtc_init(pnv->isa_bus, 2000, NULL);
504 }
505
506 /*
507 * 0:21 Reserved - Read as zeros
508 * 22:24 Chip ID
509 * 25:28 Core number
510 * 29:31 Thread ID
511 */
512 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
513 {
514 return (chip->chip_id << 7) | (core_id << 3);
515 }
516
517 /*
518 * 0:48 Reserved - Read as zeroes
519 * 49:52 Node ID
520 * 53:55 Chip ID
521 * 56 Reserved - Read as zero
522 * 57:61 Core number
523 * 62:63 Thread ID
524 *
525 * We only care about the lower bits. uint32_t is fine for the moment.
526 */
527 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
528 {
529 return (chip->chip_id << 8) | (core_id << 2);
530 }
531
532 /* Allowed core identifiers on a POWER8 Processor Chip :
533 *
534 * <EX0 reserved>
535 * EX1 - Venice only
536 * EX2 - Venice only
537 * EX3 - Venice only
538 * EX4
539 * EX5
540 * EX6
541 * <EX7,8 reserved> <reserved>
542 * EX9 - Venice only
543 * EX10 - Venice only
544 * EX11 - Venice only
545 * EX12
546 * EX13
547 * EX14
548 * <EX15 reserved>
549 */
550 #define POWER8E_CORE_MASK (0x7070ull)
551 #define POWER8_CORE_MASK (0x7e7eull)
552
553 /*
554 * POWER9 has 24 cores, ids starting at 0x20
555 */
556 #define POWER9_CORE_MASK (0xffffff00000000ull)
557
558 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
559 {
560 DeviceClass *dc = DEVICE_CLASS(klass);
561 PnvChipClass *k = PNV_CHIP_CLASS(klass);
562
563 k->cpu_model = "POWER8E";
564 k->chip_type = PNV_CHIP_POWER8E;
565 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
566 k->cores_mask = POWER8E_CORE_MASK;
567 k->core_pir = pnv_chip_core_pir_p8;
568 k->xscom_base = 0x003fc0000000000ull;
569 k->xscom_core_base = 0x10000000ull;
570 dc->desc = "PowerNV Chip POWER8E";
571 }
572
573 static const TypeInfo pnv_chip_power8e_info = {
574 .name = TYPE_PNV_CHIP_POWER8E,
575 .parent = TYPE_PNV_CHIP,
576 .instance_size = sizeof(PnvChip),
577 .class_init = pnv_chip_power8e_class_init,
578 };
579
580 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
581 {
582 DeviceClass *dc = DEVICE_CLASS(klass);
583 PnvChipClass *k = PNV_CHIP_CLASS(klass);
584
585 k->cpu_model = "POWER8";
586 k->chip_type = PNV_CHIP_POWER8;
587 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
588 k->cores_mask = POWER8_CORE_MASK;
589 k->core_pir = pnv_chip_core_pir_p8;
590 k->xscom_base = 0x003fc0000000000ull;
591 k->xscom_core_base = 0x10000000ull;
592 dc->desc = "PowerNV Chip POWER8";
593 }
594
595 static const TypeInfo pnv_chip_power8_info = {
596 .name = TYPE_PNV_CHIP_POWER8,
597 .parent = TYPE_PNV_CHIP,
598 .instance_size = sizeof(PnvChip),
599 .class_init = pnv_chip_power8_class_init,
600 };
601
602 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
603 {
604 DeviceClass *dc = DEVICE_CLASS(klass);
605 PnvChipClass *k = PNV_CHIP_CLASS(klass);
606
607 k->cpu_model = "POWER8NVL";
608 k->chip_type = PNV_CHIP_POWER8NVL;
609 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
610 k->cores_mask = POWER8_CORE_MASK;
611 k->core_pir = pnv_chip_core_pir_p8;
612 k->xscom_base = 0x003fc0000000000ull;
613 k->xscom_core_base = 0x10000000ull;
614 dc->desc = "PowerNV Chip POWER8NVL";
615 }
616
617 static const TypeInfo pnv_chip_power8nvl_info = {
618 .name = TYPE_PNV_CHIP_POWER8NVL,
619 .parent = TYPE_PNV_CHIP,
620 .instance_size = sizeof(PnvChip),
621 .class_init = pnv_chip_power8nvl_class_init,
622 };
623
624 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
625 {
626 DeviceClass *dc = DEVICE_CLASS(klass);
627 PnvChipClass *k = PNV_CHIP_CLASS(klass);
628
629 k->cpu_model = "POWER9";
630 k->chip_type = PNV_CHIP_POWER9;
631 k->chip_cfam_id = 0x100d104980000000ull; /* P9 Nimbus DD1.0 */
632 k->cores_mask = POWER9_CORE_MASK;
633 k->core_pir = pnv_chip_core_pir_p9;
634 k->xscom_base = 0x00603fc00000000ull;
635 k->xscom_core_base = 0x0ull;
636 dc->desc = "PowerNV Chip POWER9";
637 }
638
639 static const TypeInfo pnv_chip_power9_info = {
640 .name = TYPE_PNV_CHIP_POWER9,
641 .parent = TYPE_PNV_CHIP,
642 .instance_size = sizeof(PnvChip),
643 .class_init = pnv_chip_power9_class_init,
644 };
645
646 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
647 {
648 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
649 int cores_max;
650
651 /*
652 * No custom mask for this chip, let's use the default one from *
653 * the chip class
654 */
655 if (!chip->cores_mask) {
656 chip->cores_mask = pcc->cores_mask;
657 }
658
659 /* filter alien core ids ! some are reserved */
660 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
661 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
662 chip->cores_mask);
663 return;
664 }
665 chip->cores_mask &= pcc->cores_mask;
666
667 /* now that we have a sane layout, let check the number of cores */
668 cores_max = ctpop64(chip->cores_mask);
669 if (chip->nr_cores > cores_max) {
670 error_setg(errp, "warning: too many cores for chip ! Limit is %d",
671 cores_max);
672 return;
673 }
674 }
675
676 static void pnv_chip_init(Object *obj)
677 {
678 PnvChip *chip = PNV_CHIP(obj);
679 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
680
681 chip->xscom_base = pcc->xscom_base;
682
683 object_initialize(&chip->lpc, sizeof(chip->lpc), TYPE_PNV_LPC);
684 object_property_add_child(obj, "lpc", OBJECT(&chip->lpc), NULL);
685 }
686
687 static void pnv_chip_icp_realize(PnvChip *chip, Error **errp)
688 {
689 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
690 char *typename = pnv_core_typename(pcc->cpu_model);
691 size_t typesize = object_type_get_instance_size(typename);
692 int i, j;
693 char *name;
694 XICSFabric *xi = XICS_FABRIC(qdev_get_machine());
695
696 name = g_strdup_printf("icp-%x", chip->chip_id);
697 memory_region_init(&chip->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
698 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip->icp_mmio);
699 g_free(name);
700
701 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip));
702
703 /* Map the ICP registers for each thread */
704 for (i = 0; i < chip->nr_cores; i++) {
705 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
706 int core_hwid = CPU_CORE(pnv_core)->core_id;
707
708 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
709 uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
710 PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir));
711
712 memory_region_add_subregion(&chip->icp_mmio, pir << 12, &icp->mmio);
713 }
714 }
715
716 g_free(typename);
717 }
718
719 static void pnv_chip_realize(DeviceState *dev, Error **errp)
720 {
721 PnvChip *chip = PNV_CHIP(dev);
722 Error *error = NULL;
723 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
724 char *typename = pnv_core_typename(pcc->cpu_model);
725 size_t typesize = object_type_get_instance_size(typename);
726 int i, core_hwid;
727
728 if (!object_class_by_name(typename)) {
729 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
730 return;
731 }
732
733 /* XSCOM bridge */
734 pnv_xscom_realize(chip, &error);
735 if (error) {
736 error_propagate(errp, error);
737 return;
738 }
739 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
740
741 /* Cores */
742 pnv_chip_core_sanitize(chip, &error);
743 if (error) {
744 error_propagate(errp, error);
745 return;
746 }
747
748 chip->cores = g_malloc0(typesize * chip->nr_cores);
749
750 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
751 && (i < chip->nr_cores); core_hwid++) {
752 char core_name[32];
753 void *pnv_core = chip->cores + i * typesize;
754
755 if (!(chip->cores_mask & (1ull << core_hwid))) {
756 continue;
757 }
758
759 object_initialize(pnv_core, typesize, typename);
760 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
761 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core),
762 &error_fatal);
763 object_property_set_int(OBJECT(pnv_core), smp_threads, "nr-threads",
764 &error_fatal);
765 object_property_set_int(OBJECT(pnv_core), core_hwid,
766 CPU_CORE_PROP_CORE_ID, &error_fatal);
767 object_property_set_int(OBJECT(pnv_core),
768 pcc->core_pir(chip, core_hwid),
769 "pir", &error_fatal);
770 object_property_add_const_link(OBJECT(pnv_core), "xics",
771 qdev_get_machine(), &error_fatal);
772 object_property_set_bool(OBJECT(pnv_core), true, "realized",
773 &error_fatal);
774 object_unref(OBJECT(pnv_core));
775
776 /* Each core has an XSCOM MMIO region */
777 pnv_xscom_add_subregion(chip,
778 PNV_XSCOM_EX_CORE_BASE(pcc->xscom_core_base,
779 core_hwid),
780 &PNV_CORE(pnv_core)->xscom_regs);
781 i++;
782 }
783 g_free(typename);
784
785 /* Create LPC controller */
786 object_property_set_bool(OBJECT(&chip->lpc), true, "realized",
787 &error_fatal);
788 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip->lpc.xscom_regs);
789
790 /* Interrupt Management Area. This is the memory region holding
791 * all the Interrupt Control Presenter (ICP) registers */
792 pnv_chip_icp_realize(chip, &error);
793 if (error) {
794 error_propagate(errp, error);
795 return;
796 }
797 }
798
799 static Property pnv_chip_properties[] = {
800 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
801 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
802 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
803 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
804 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
805 DEFINE_PROP_END_OF_LIST(),
806 };
807
808 static void pnv_chip_class_init(ObjectClass *klass, void *data)
809 {
810 DeviceClass *dc = DEVICE_CLASS(klass);
811
812 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
813 dc->realize = pnv_chip_realize;
814 dc->props = pnv_chip_properties;
815 dc->desc = "PowerNV Chip";
816 }
817
818 static const TypeInfo pnv_chip_info = {
819 .name = TYPE_PNV_CHIP,
820 .parent = TYPE_SYS_BUS_DEVICE,
821 .class_init = pnv_chip_class_init,
822 .instance_init = pnv_chip_init,
823 .class_size = sizeof(PnvChipClass),
824 .abstract = true,
825 };
826
827 static PowerPCCPU *ppc_get_vcpu_by_pir(int pir)
828 {
829 CPUState *cs;
830
831 CPU_FOREACH(cs) {
832 PowerPCCPU *cpu = POWERPC_CPU(cs);
833 CPUPPCState *env = &cpu->env;
834
835 if (env->spr_cb[SPR_PIR].default_value == pir) {
836 return cpu;
837 }
838 }
839
840 return NULL;
841 }
842
843 static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
844 {
845 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
846
847 return cpu ? ICP(cpu->intc) : NULL;
848 }
849
850 static void pnv_pic_print_info(InterruptStatsProvider *obj,
851 Monitor *mon)
852 {
853 CPUState *cs;
854
855 CPU_FOREACH(cs) {
856 PowerPCCPU *cpu = POWERPC_CPU(cs);
857
858 icp_pic_print_info(ICP(cpu->intc), mon);
859 }
860 }
861
862 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name,
863 void *opaque, Error **errp)
864 {
865 visit_type_uint32(v, name, &POWERNV_MACHINE(obj)->num_chips, errp);
866 }
867
868 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name,
869 void *opaque, Error **errp)
870 {
871 PnvMachineState *pnv = POWERNV_MACHINE(obj);
872 uint32_t num_chips;
873 Error *local_err = NULL;
874
875 visit_type_uint32(v, name, &num_chips, &local_err);
876 if (local_err) {
877 error_propagate(errp, local_err);
878 return;
879 }
880
881 /*
882 * TODO: should we decide on how many chips we can create based
883 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
884 */
885 if (!is_power_of_2(num_chips) || num_chips > 4) {
886 error_setg(errp, "invalid number of chips: '%d'", num_chips);
887 return;
888 }
889
890 pnv->num_chips = num_chips;
891 }
892
893 static void powernv_machine_initfn(Object *obj)
894 {
895 PnvMachineState *pnv = POWERNV_MACHINE(obj);
896 pnv->num_chips = 1;
897 }
898
899 static void powernv_machine_class_props_init(ObjectClass *oc)
900 {
901 object_class_property_add(oc, "num-chips", "uint32_t",
902 pnv_get_num_chips, pnv_set_num_chips,
903 NULL, NULL, NULL);
904 object_class_property_set_description(oc, "num-chips",
905 "Specifies the number of processor chips",
906 NULL);
907 }
908
909 static void powernv_machine_class_init(ObjectClass *oc, void *data)
910 {
911 MachineClass *mc = MACHINE_CLASS(oc);
912 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
913 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
914
915 mc->desc = "IBM PowerNV (Non-Virtualized)";
916 mc->init = ppc_powernv_init;
917 mc->reset = ppc_powernv_reset;
918 mc->max_cpus = MAX_CPUS;
919 mc->block_default_type = IF_IDE; /* Pnv provides a AHCI device for
920 * storage */
921 mc->no_parallel = 1;
922 mc->default_boot_order = NULL;
923 mc->default_ram_size = 1 * G_BYTE;
924 xic->icp_get = pnv_icp_get;
925 ispc->print_info = pnv_pic_print_info;
926
927 powernv_machine_class_props_init(oc);
928 }
929
930 static const TypeInfo powernv_machine_info = {
931 .name = TYPE_POWERNV_MACHINE,
932 .parent = TYPE_MACHINE,
933 .instance_size = sizeof(PnvMachineState),
934 .instance_init = powernv_machine_initfn,
935 .class_init = powernv_machine_class_init,
936 .interfaces = (InterfaceInfo[]) {
937 { TYPE_XICS_FABRIC },
938 { TYPE_INTERRUPT_STATS_PROVIDER },
939 { },
940 },
941 };
942
943 static void powernv_machine_register_types(void)
944 {
945 type_register_static(&powernv_machine_info);
946 type_register_static(&pnv_chip_info);
947 type_register_static(&pnv_chip_power8e_info);
948 type_register_static(&pnv_chip_power8_info);
949 type_register_static(&pnv_chip_power8nvl_info);
950 type_register_static(&pnv_chip_power9_info);
951 }
952
953 type_init(powernv_machine_register_types)