ppc/pnv: add initial IPMI sensors for the BMC simulator
[qemu.git] / hw / ppc / pnv.c
1 /*
2 * QEMU PowerPC PowerNV machine model
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "sysemu/sysemu.h"
23 #include "sysemu/numa.h"
24 #include "sysemu/cpus.h"
25 #include "hw/hw.h"
26 #include "target/ppc/cpu.h"
27 #include "qemu/log.h"
28 #include "hw/ppc/fdt.h"
29 #include "hw/ppc/ppc.h"
30 #include "hw/ppc/pnv.h"
31 #include "hw/ppc/pnv_core.h"
32 #include "hw/loader.h"
33 #include "exec/address-spaces.h"
34 #include "qemu/cutils.h"
35 #include "qapi/visitor.h"
36 #include "monitor/monitor.h"
37 #include "hw/intc/intc.h"
38 #include "hw/ipmi/ipmi.h"
39
40 #include "hw/ppc/xics.h"
41 #include "hw/ppc/pnv_xscom.h"
42
43 #include "hw/isa/isa.h"
44 #include "hw/char/serial.h"
45 #include "hw/timer/mc146818rtc.h"
46
47 #include <libfdt.h>
48
49 #define FDT_MAX_SIZE 0x00100000
50
51 #define FW_FILE_NAME "skiboot.lid"
52 #define FW_LOAD_ADDR 0x0
53 #define FW_MAX_SIZE 0x00400000
54
55 #define KERNEL_LOAD_ADDR 0x20000000
56 #define INITRD_LOAD_ADDR 0x40000000
57
58 /*
59 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
60 * 4 * 4 sockets * 12 cores * 8 threads = 1536
61 * Let's make it 2^11
62 */
63 #define MAX_CPUS 2048
64
65 /*
66 * Memory nodes are created by hostboot, one for each range of memory
67 * that has a different "affinity". In practice, it means one range
68 * per chip.
69 */
70 static void powernv_populate_memory_node(void *fdt, int chip_id, hwaddr start,
71 hwaddr size)
72 {
73 char *mem_name;
74 uint64_t mem_reg_property[2];
75 int off;
76
77 mem_reg_property[0] = cpu_to_be64(start);
78 mem_reg_property[1] = cpu_to_be64(size);
79
80 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
81 off = fdt_add_subnode(fdt, 0, mem_name);
82 g_free(mem_name);
83
84 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
85 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
86 sizeof(mem_reg_property))));
87 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
88 }
89
90 static int get_cpus_node(void *fdt)
91 {
92 int cpus_offset = fdt_path_offset(fdt, "/cpus");
93
94 if (cpus_offset < 0) {
95 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
96 "cpus");
97 if (cpus_offset) {
98 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
99 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
100 }
101 }
102 _FDT(cpus_offset);
103 return cpus_offset;
104 }
105
106 /*
107 * The PowerNV cores (and threads) need to use real HW ids and not an
108 * incremental index like it has been done on other platforms. This HW
109 * id is stored in the CPU PIR, it is used to create cpu nodes in the
110 * device tree, used in XSCOM to address cores and in interrupt
111 * servers.
112 */
113 static void powernv_create_core_node(PnvChip *chip, PnvCore *pc, void *fdt)
114 {
115 CPUState *cs = CPU(DEVICE(pc->threads));
116 DeviceClass *dc = DEVICE_GET_CLASS(cs);
117 PowerPCCPU *cpu = POWERPC_CPU(cs);
118 int smt_threads = CPU_CORE(pc)->nr_threads;
119 CPUPPCState *env = &cpu->env;
120 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
121 uint32_t servers_prop[smt_threads];
122 int i;
123 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
124 0xffffffff, 0xffffffff};
125 uint32_t tbfreq = PNV_TIMEBASE_FREQ;
126 uint32_t cpufreq = 1000000000;
127 uint32_t page_sizes_prop[64];
128 size_t page_sizes_prop_size;
129 const uint8_t pa_features[] = { 24, 0,
130 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
131 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
132 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
133 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
134 int offset;
135 char *nodename;
136 int cpus_offset = get_cpus_node(fdt);
137
138 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
139 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
140 _FDT(offset);
141 g_free(nodename);
142
143 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
144
145 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
146 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
147 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
148
149 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
150 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
151 env->dcache_line_size)));
152 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
153 env->dcache_line_size)));
154 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
155 env->icache_line_size)));
156 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
157 env->icache_line_size)));
158
159 if (pcc->l1_dcache_size) {
160 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
161 pcc->l1_dcache_size)));
162 } else {
163 error_report("Warning: Unknown L1 dcache size for cpu");
164 }
165 if (pcc->l1_icache_size) {
166 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
167 pcc->l1_icache_size)));
168 } else {
169 error_report("Warning: Unknown L1 icache size for cpu");
170 }
171
172 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
173 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
174 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
175 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
176 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
177
178 if (env->spr_cb[SPR_PURR].oea_read) {
179 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
180 }
181
182 if (env->mmu_model & POWERPC_MMU_1TSEG) {
183 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
184 segs, sizeof(segs))));
185 }
186
187 /* Advertise VMX/VSX (vector extensions) if available
188 * 0 / no property == no vector extensions
189 * 1 == VMX / Altivec available
190 * 2 == VSX available */
191 if (env->insns_flags & PPC_ALTIVEC) {
192 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
193
194 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
195 }
196
197 /* Advertise DFP (Decimal Floating Point) if available
198 * 0 / no property == no DFP
199 * 1 == DFP available */
200 if (env->insns_flags2 & PPC2_DFP) {
201 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
202 }
203
204 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
205 sizeof(page_sizes_prop));
206 if (page_sizes_prop_size) {
207 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
208 page_sizes_prop, page_sizes_prop_size)));
209 }
210
211 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
212 pa_features, sizeof(pa_features))));
213
214 /* Build interrupt servers properties */
215 for (i = 0; i < smt_threads; i++) {
216 servers_prop[i] = cpu_to_be32(pc->pir + i);
217 }
218 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
219 servers_prop, sizeof(servers_prop))));
220 }
221
222 static void powernv_populate_icp(PnvChip *chip, void *fdt, uint32_t pir,
223 uint32_t nr_threads)
224 {
225 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
226 char *name;
227 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
228 uint32_t irange[2], i, rsize;
229 uint64_t *reg;
230 int offset;
231
232 irange[0] = cpu_to_be32(pir);
233 irange[1] = cpu_to_be32(nr_threads);
234
235 rsize = sizeof(uint64_t) * 2 * nr_threads;
236 reg = g_malloc(rsize);
237 for (i = 0; i < nr_threads; i++) {
238 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
239 reg[i * 2 + 1] = cpu_to_be64(0x1000);
240 }
241
242 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
243 offset = fdt_add_subnode(fdt, 0, name);
244 _FDT(offset);
245 g_free(name);
246
247 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
248 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
249 _FDT((fdt_setprop_string(fdt, offset, "device_type",
250 "PowerPC-External-Interrupt-Presentation")));
251 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
252 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
253 irange, sizeof(irange))));
254 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
255 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
256 g_free(reg);
257 }
258
259 static int pnv_chip_lpc_offset(PnvChip *chip, void *fdt)
260 {
261 char *name;
262 int offset;
263
264 name = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
265 (uint64_t) PNV_XSCOM_BASE(chip), PNV_XSCOM_LPC_BASE);
266 offset = fdt_path_offset(fdt, name);
267 g_free(name);
268 return offset;
269 }
270
271 static void powernv_populate_chip(PnvChip *chip, void *fdt)
272 {
273 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
274 char *typename = pnv_core_typename(pcc->cpu_model);
275 size_t typesize = object_type_get_instance_size(typename);
276 int i;
277
278 pnv_xscom_populate(chip, fdt, 0);
279
280 /* The default LPC bus of a multichip system is on chip 0. It's
281 * recognized by the firmware (skiboot) using a "primary"
282 * property.
283 */
284 if (chip->chip_id == 0x0) {
285 int lpc_offset = pnv_chip_lpc_offset(chip, fdt);
286
287 _FDT((fdt_setprop(fdt, lpc_offset, "primary", NULL, 0)));
288 }
289
290 for (i = 0; i < chip->nr_cores; i++) {
291 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
292
293 powernv_create_core_node(chip, pnv_core, fdt);
294
295 /* Interrupt Control Presenters (ICP). One per core. */
296 powernv_populate_icp(chip, fdt, pnv_core->pir,
297 CPU_CORE(pnv_core)->nr_threads);
298 }
299
300 if (chip->ram_size) {
301 powernv_populate_memory_node(fdt, chip->chip_id, chip->ram_start,
302 chip->ram_size);
303 }
304 g_free(typename);
305 }
306
307 static void powernv_populate_rtc(ISADevice *d, void *fdt, int lpc_off)
308 {
309 uint32_t io_base = d->ioport_id;
310 uint32_t io_regs[] = {
311 cpu_to_be32(1),
312 cpu_to_be32(io_base),
313 cpu_to_be32(2)
314 };
315 char *name;
316 int node;
317
318 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
319 node = fdt_add_subnode(fdt, lpc_off, name);
320 _FDT(node);
321 g_free(name);
322
323 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
324 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
325 }
326
327 static void powernv_populate_serial(ISADevice *d, void *fdt, int lpc_off)
328 {
329 const char compatible[] = "ns16550\0pnpPNP,501";
330 uint32_t io_base = d->ioport_id;
331 uint32_t io_regs[] = {
332 cpu_to_be32(1),
333 cpu_to_be32(io_base),
334 cpu_to_be32(8)
335 };
336 char *name;
337 int node;
338
339 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
340 node = fdt_add_subnode(fdt, lpc_off, name);
341 _FDT(node);
342 g_free(name);
343
344 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
345 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
346 sizeof(compatible))));
347
348 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
349 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
350 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0])));
351 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
352 fdt_get_phandle(fdt, lpc_off))));
353
354 /* This is needed by Linux */
355 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
356 }
357
358 static void powernv_populate_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
359 {
360 const char compatible[] = "bt\0ipmi-bt";
361 uint32_t io_base;
362 uint32_t io_regs[] = {
363 cpu_to_be32(1),
364 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
365 cpu_to_be32(3)
366 };
367 uint32_t irq;
368 char *name;
369 int node;
370
371 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal);
372 io_regs[1] = cpu_to_be32(io_base);
373
374 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal);
375
376 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
377 node = fdt_add_subnode(fdt, lpc_off, name);
378 _FDT(node);
379 g_free(name);
380
381 fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs));
382 fdt_setprop(fdt, node, "compatible", compatible, sizeof(compatible));
383
384 /* Mark it as reserved to avoid Linux trying to claim it */
385 _FDT((fdt_setprop_string(fdt, node, "status", "reserved")));
386 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
387 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
388 fdt_get_phandle(fdt, lpc_off))));
389 }
390
391 typedef struct ForeachPopulateArgs {
392 void *fdt;
393 int offset;
394 } ForeachPopulateArgs;
395
396 static int powernv_populate_isa_device(DeviceState *dev, void *opaque)
397 {
398 ForeachPopulateArgs *args = opaque;
399 ISADevice *d = ISA_DEVICE(dev);
400
401 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
402 powernv_populate_rtc(d, args->fdt, args->offset);
403 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
404 powernv_populate_serial(d, args->fdt, args->offset);
405 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) {
406 powernv_populate_ipmi_bt(d, args->fdt, args->offset);
407 } else {
408 error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
409 d->ioport_id);
410 }
411
412 return 0;
413 }
414
415 static void powernv_populate_isa(ISABus *bus, void *fdt, int lpc_offset)
416 {
417 ForeachPopulateArgs args = {
418 .fdt = fdt,
419 .offset = lpc_offset,
420 };
421
422 /* ISA devices are not necessarily parented to the ISA bus so we
423 * can not use object_child_foreach() */
424 qbus_walk_children(BUS(bus), powernv_populate_isa_device,
425 NULL, NULL, NULL, &args);
426 }
427
428 static void *powernv_create_fdt(MachineState *machine)
429 {
430 const char plat_compat[] = "qemu,powernv\0ibm,powernv";
431 PnvMachineState *pnv = POWERNV_MACHINE(machine);
432 void *fdt;
433 char *buf;
434 int off;
435 int i;
436 int lpc_offset;
437
438 fdt = g_malloc0(FDT_MAX_SIZE);
439 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
440
441 /* Root node */
442 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
443 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
444 _FDT((fdt_setprop_string(fdt, 0, "model",
445 "IBM PowerNV (emulated by qemu)")));
446 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat,
447 sizeof(plat_compat))));
448
449 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
450 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
451 if (qemu_uuid_set) {
452 _FDT((fdt_property_string(fdt, "system-id", buf)));
453 }
454 g_free(buf);
455
456 off = fdt_add_subnode(fdt, 0, "chosen");
457 if (machine->kernel_cmdline) {
458 _FDT((fdt_setprop_string(fdt, off, "bootargs",
459 machine->kernel_cmdline)));
460 }
461
462 if (pnv->initrd_size) {
463 uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
464 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
465
466 _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
467 &start_prop, sizeof(start_prop))));
468 _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
469 &end_prop, sizeof(end_prop))));
470 }
471
472 /* Populate device tree for each chip */
473 for (i = 0; i < pnv->num_chips; i++) {
474 powernv_populate_chip(pnv->chips[i], fdt);
475 }
476
477 /* Populate ISA devices on chip 0 */
478 lpc_offset = pnv_chip_lpc_offset(pnv->chips[0], fdt);
479 powernv_populate_isa(pnv->isa_bus, fdt, lpc_offset);
480
481 if (pnv->bmc) {
482 pnv_bmc_populate_sensors(pnv->bmc, fdt);
483 }
484
485 return fdt;
486 }
487
488 static void ppc_powernv_reset(void)
489 {
490 MachineState *machine = MACHINE(qdev_get_machine());
491 PnvMachineState *pnv = POWERNV_MACHINE(machine);
492 void *fdt;
493 Object *obj;
494
495 qemu_devices_reset();
496
497 /* OpenPOWER systems have a BMC, which can be defined on the
498 * command line with:
499 *
500 * -device ipmi-bmc-sim,id=bmc0
501 *
502 * This is the internal simulator but it could also be an external
503 * BMC.
504 */
505 obj = object_resolve_path_type("", TYPE_IPMI_BMC, NULL);
506 if (obj) {
507 pnv->bmc = IPMI_BMC(obj);
508 }
509
510 fdt = powernv_create_fdt(machine);
511
512 /* Pack resulting tree */
513 _FDT((fdt_pack(fdt)));
514
515 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
516 }
517
518 static ISABus *pnv_isa_create(PnvChip *chip)
519 {
520 PnvLpcController *lpc = &chip->lpc;
521 ISABus *isa_bus;
522 qemu_irq *irqs;
523 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
524
525 /* let isa_bus_new() create its own bridge on SysBus otherwise
526 * devices speficied on the command line won't find the bus and
527 * will fail to create.
528 */
529 isa_bus = isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io,
530 &error_fatal);
531
532 irqs = pnv_lpc_isa_irq_create(lpc, pcc->chip_type, ISA_NUM_IRQS);
533
534 isa_bus_irqs(isa_bus, irqs);
535 return isa_bus;
536 }
537
538 static void ppc_powernv_init(MachineState *machine)
539 {
540 PnvMachineState *pnv = POWERNV_MACHINE(machine);
541 MemoryRegion *ram;
542 char *fw_filename;
543 long fw_size;
544 int i;
545 char *chip_typename;
546
547 /* allocate RAM */
548 if (machine->ram_size < (1 * G_BYTE)) {
549 error_report("Warning: skiboot may not work with < 1GB of RAM");
550 }
551
552 ram = g_new(MemoryRegion, 1);
553 memory_region_allocate_system_memory(ram, NULL, "ppc_powernv.ram",
554 machine->ram_size);
555 memory_region_add_subregion(get_system_memory(), 0, ram);
556
557 /* load skiboot firmware */
558 if (bios_name == NULL) {
559 bios_name = FW_FILE_NAME;
560 }
561
562 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
563
564 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE);
565 if (fw_size < 0) {
566 error_report("Could not load OPAL '%s'", fw_filename);
567 exit(1);
568 }
569 g_free(fw_filename);
570
571 /* load kernel */
572 if (machine->kernel_filename) {
573 long kernel_size;
574
575 kernel_size = load_image_targphys(machine->kernel_filename,
576 KERNEL_LOAD_ADDR, 0x2000000);
577 if (kernel_size < 0) {
578 error_report("Could not load kernel '%s'",
579 machine->kernel_filename);
580 exit(1);
581 }
582 }
583
584 /* load initrd */
585 if (machine->initrd_filename) {
586 pnv->initrd_base = INITRD_LOAD_ADDR;
587 pnv->initrd_size = load_image_targphys(machine->initrd_filename,
588 pnv->initrd_base, 0x10000000); /* 128MB max */
589 if (pnv->initrd_size < 0) {
590 error_report("Could not load initial ram disk '%s'",
591 machine->initrd_filename);
592 exit(1);
593 }
594 }
595
596 /* We need some cpu model to instantiate the PnvChip class */
597 if (machine->cpu_model == NULL) {
598 machine->cpu_model = "POWER8";
599 }
600
601 /* Create the processor chips */
602 chip_typename = g_strdup_printf(TYPE_PNV_CHIP "-%s", machine->cpu_model);
603 if (!object_class_by_name(chip_typename)) {
604 error_report("qemu: invalid CPU model '%s' for %s machine",
605 machine->cpu_model, MACHINE_GET_CLASS(machine)->name);
606 exit(1);
607 }
608
609 pnv->chips = g_new0(PnvChip *, pnv->num_chips);
610 for (i = 0; i < pnv->num_chips; i++) {
611 char chip_name[32];
612 Object *chip = object_new(chip_typename);
613
614 pnv->chips[i] = PNV_CHIP(chip);
615
616 /* TODO: put all the memory in one node on chip 0 until we find a
617 * way to specify different ranges for each chip
618 */
619 if (i == 0) {
620 object_property_set_int(chip, machine->ram_size, "ram-size",
621 &error_fatal);
622 }
623
624 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i));
625 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal);
626 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id",
627 &error_fatal);
628 object_property_set_int(chip, smp_cores, "nr-cores", &error_fatal);
629 object_property_set_bool(chip, true, "realized", &error_fatal);
630 }
631 g_free(chip_typename);
632
633 /* Instantiate ISA bus on chip 0 */
634 pnv->isa_bus = pnv_isa_create(pnv->chips[0]);
635
636 /* Create serial port */
637 serial_hds_isa_init(pnv->isa_bus, 0, MAX_SERIAL_PORTS);
638
639 /* Create an RTC ISA device too */
640 rtc_init(pnv->isa_bus, 2000, NULL);
641 }
642
643 /*
644 * 0:21 Reserved - Read as zeros
645 * 22:24 Chip ID
646 * 25:28 Core number
647 * 29:31 Thread ID
648 */
649 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
650 {
651 return (chip->chip_id << 7) | (core_id << 3);
652 }
653
654 /*
655 * 0:48 Reserved - Read as zeroes
656 * 49:52 Node ID
657 * 53:55 Chip ID
658 * 56 Reserved - Read as zero
659 * 57:61 Core number
660 * 62:63 Thread ID
661 *
662 * We only care about the lower bits. uint32_t is fine for the moment.
663 */
664 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
665 {
666 return (chip->chip_id << 8) | (core_id << 2);
667 }
668
669 /* Allowed core identifiers on a POWER8 Processor Chip :
670 *
671 * <EX0 reserved>
672 * EX1 - Venice only
673 * EX2 - Venice only
674 * EX3 - Venice only
675 * EX4
676 * EX5
677 * EX6
678 * <EX7,8 reserved> <reserved>
679 * EX9 - Venice only
680 * EX10 - Venice only
681 * EX11 - Venice only
682 * EX12
683 * EX13
684 * EX14
685 * <EX15 reserved>
686 */
687 #define POWER8E_CORE_MASK (0x7070ull)
688 #define POWER8_CORE_MASK (0x7e7eull)
689
690 /*
691 * POWER9 has 24 cores, ids starting at 0x20
692 */
693 #define POWER9_CORE_MASK (0xffffff00000000ull)
694
695 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
696 {
697 DeviceClass *dc = DEVICE_CLASS(klass);
698 PnvChipClass *k = PNV_CHIP_CLASS(klass);
699
700 k->cpu_model = "POWER8E";
701 k->chip_type = PNV_CHIP_POWER8E;
702 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
703 k->cores_mask = POWER8E_CORE_MASK;
704 k->core_pir = pnv_chip_core_pir_p8;
705 k->xscom_base = 0x003fc0000000000ull;
706 k->xscom_core_base = 0x10000000ull;
707 dc->desc = "PowerNV Chip POWER8E";
708 }
709
710 static const TypeInfo pnv_chip_power8e_info = {
711 .name = TYPE_PNV_CHIP_POWER8E,
712 .parent = TYPE_PNV_CHIP,
713 .instance_size = sizeof(PnvChip),
714 .class_init = pnv_chip_power8e_class_init,
715 };
716
717 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
718 {
719 DeviceClass *dc = DEVICE_CLASS(klass);
720 PnvChipClass *k = PNV_CHIP_CLASS(klass);
721
722 k->cpu_model = "POWER8";
723 k->chip_type = PNV_CHIP_POWER8;
724 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
725 k->cores_mask = POWER8_CORE_MASK;
726 k->core_pir = pnv_chip_core_pir_p8;
727 k->xscom_base = 0x003fc0000000000ull;
728 k->xscom_core_base = 0x10000000ull;
729 dc->desc = "PowerNV Chip POWER8";
730 }
731
732 static const TypeInfo pnv_chip_power8_info = {
733 .name = TYPE_PNV_CHIP_POWER8,
734 .parent = TYPE_PNV_CHIP,
735 .instance_size = sizeof(PnvChip),
736 .class_init = pnv_chip_power8_class_init,
737 };
738
739 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
740 {
741 DeviceClass *dc = DEVICE_CLASS(klass);
742 PnvChipClass *k = PNV_CHIP_CLASS(klass);
743
744 k->cpu_model = "POWER8NVL";
745 k->chip_type = PNV_CHIP_POWER8NVL;
746 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
747 k->cores_mask = POWER8_CORE_MASK;
748 k->core_pir = pnv_chip_core_pir_p8;
749 k->xscom_base = 0x003fc0000000000ull;
750 k->xscom_core_base = 0x10000000ull;
751 dc->desc = "PowerNV Chip POWER8NVL";
752 }
753
754 static const TypeInfo pnv_chip_power8nvl_info = {
755 .name = TYPE_PNV_CHIP_POWER8NVL,
756 .parent = TYPE_PNV_CHIP,
757 .instance_size = sizeof(PnvChip),
758 .class_init = pnv_chip_power8nvl_class_init,
759 };
760
761 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
762 {
763 DeviceClass *dc = DEVICE_CLASS(klass);
764 PnvChipClass *k = PNV_CHIP_CLASS(klass);
765
766 k->cpu_model = "POWER9";
767 k->chip_type = PNV_CHIP_POWER9;
768 k->chip_cfam_id = 0x100d104980000000ull; /* P9 Nimbus DD1.0 */
769 k->cores_mask = POWER9_CORE_MASK;
770 k->core_pir = pnv_chip_core_pir_p9;
771 k->xscom_base = 0x00603fc00000000ull;
772 k->xscom_core_base = 0x0ull;
773 dc->desc = "PowerNV Chip POWER9";
774 }
775
776 static const TypeInfo pnv_chip_power9_info = {
777 .name = TYPE_PNV_CHIP_POWER9,
778 .parent = TYPE_PNV_CHIP,
779 .instance_size = sizeof(PnvChip),
780 .class_init = pnv_chip_power9_class_init,
781 };
782
783 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
784 {
785 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
786 int cores_max;
787
788 /*
789 * No custom mask for this chip, let's use the default one from *
790 * the chip class
791 */
792 if (!chip->cores_mask) {
793 chip->cores_mask = pcc->cores_mask;
794 }
795
796 /* filter alien core ids ! some are reserved */
797 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
798 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
799 chip->cores_mask);
800 return;
801 }
802 chip->cores_mask &= pcc->cores_mask;
803
804 /* now that we have a sane layout, let check the number of cores */
805 cores_max = ctpop64(chip->cores_mask);
806 if (chip->nr_cores > cores_max) {
807 error_setg(errp, "warning: too many cores for chip ! Limit is %d",
808 cores_max);
809 return;
810 }
811 }
812
813 static void pnv_chip_init(Object *obj)
814 {
815 PnvChip *chip = PNV_CHIP(obj);
816 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
817
818 chip->xscom_base = pcc->xscom_base;
819
820 object_initialize(&chip->lpc, sizeof(chip->lpc), TYPE_PNV_LPC);
821 object_property_add_child(obj, "lpc", OBJECT(&chip->lpc), NULL);
822
823 object_initialize(&chip->psi, sizeof(chip->psi), TYPE_PNV_PSI);
824 object_property_add_child(obj, "psi", OBJECT(&chip->psi), NULL);
825 object_property_add_const_link(OBJECT(&chip->psi), "xics",
826 OBJECT(qdev_get_machine()), &error_abort);
827
828 object_initialize(&chip->occ, sizeof(chip->occ), TYPE_PNV_OCC);
829 object_property_add_child(obj, "occ", OBJECT(&chip->occ), NULL);
830 object_property_add_const_link(OBJECT(&chip->occ), "psi",
831 OBJECT(&chip->psi), &error_abort);
832
833 /* The LPC controller needs PSI to generate interrupts */
834 object_property_add_const_link(OBJECT(&chip->lpc), "psi",
835 OBJECT(&chip->psi), &error_abort);
836 }
837
838 static void pnv_chip_icp_realize(PnvChip *chip, Error **errp)
839 {
840 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
841 char *typename = pnv_core_typename(pcc->cpu_model);
842 size_t typesize = object_type_get_instance_size(typename);
843 int i, j;
844 char *name;
845 XICSFabric *xi = XICS_FABRIC(qdev_get_machine());
846
847 name = g_strdup_printf("icp-%x", chip->chip_id);
848 memory_region_init(&chip->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
849 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip->icp_mmio);
850 g_free(name);
851
852 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip));
853
854 /* Map the ICP registers for each thread */
855 for (i = 0; i < chip->nr_cores; i++) {
856 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
857 int core_hwid = CPU_CORE(pnv_core)->core_id;
858
859 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
860 uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
861 PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir));
862
863 memory_region_add_subregion(&chip->icp_mmio, pir << 12, &icp->mmio);
864 }
865 }
866
867 g_free(typename);
868 }
869
870 static void pnv_chip_realize(DeviceState *dev, Error **errp)
871 {
872 PnvChip *chip = PNV_CHIP(dev);
873 Error *error = NULL;
874 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
875 char *typename = pnv_core_typename(pcc->cpu_model);
876 size_t typesize = object_type_get_instance_size(typename);
877 int i, core_hwid;
878
879 if (!object_class_by_name(typename)) {
880 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
881 return;
882 }
883
884 /* XSCOM bridge */
885 pnv_xscom_realize(chip, &error);
886 if (error) {
887 error_propagate(errp, error);
888 return;
889 }
890 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
891
892 /* Cores */
893 pnv_chip_core_sanitize(chip, &error);
894 if (error) {
895 error_propagate(errp, error);
896 return;
897 }
898
899 chip->cores = g_malloc0(typesize * chip->nr_cores);
900
901 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
902 && (i < chip->nr_cores); core_hwid++) {
903 char core_name[32];
904 void *pnv_core = chip->cores + i * typesize;
905
906 if (!(chip->cores_mask & (1ull << core_hwid))) {
907 continue;
908 }
909
910 object_initialize(pnv_core, typesize, typename);
911 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
912 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core),
913 &error_fatal);
914 object_property_set_int(OBJECT(pnv_core), smp_threads, "nr-threads",
915 &error_fatal);
916 object_property_set_int(OBJECT(pnv_core), core_hwid,
917 CPU_CORE_PROP_CORE_ID, &error_fatal);
918 object_property_set_int(OBJECT(pnv_core),
919 pcc->core_pir(chip, core_hwid),
920 "pir", &error_fatal);
921 object_property_add_const_link(OBJECT(pnv_core), "xics",
922 qdev_get_machine(), &error_fatal);
923 object_property_set_bool(OBJECT(pnv_core), true, "realized",
924 &error_fatal);
925 object_unref(OBJECT(pnv_core));
926
927 /* Each core has an XSCOM MMIO region */
928 pnv_xscom_add_subregion(chip,
929 PNV_XSCOM_EX_CORE_BASE(pcc->xscom_core_base,
930 core_hwid),
931 &PNV_CORE(pnv_core)->xscom_regs);
932 i++;
933 }
934 g_free(typename);
935
936 /* Create LPC controller */
937 object_property_set_bool(OBJECT(&chip->lpc), true, "realized",
938 &error_fatal);
939 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip->lpc.xscom_regs);
940
941 /* Interrupt Management Area. This is the memory region holding
942 * all the Interrupt Control Presenter (ICP) registers */
943 pnv_chip_icp_realize(chip, &error);
944 if (error) {
945 error_propagate(errp, error);
946 return;
947 }
948
949 /* Processor Service Interface (PSI) Host Bridge */
950 object_property_set_int(OBJECT(&chip->psi), PNV_PSIHB_BASE(chip),
951 "bar", &error_fatal);
952 object_property_set_bool(OBJECT(&chip->psi), true, "realized", &error);
953 if (error) {
954 error_propagate(errp, error);
955 return;
956 }
957 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, &chip->psi.xscom_regs);
958
959 /* Create the simplified OCC model */
960 object_property_set_bool(OBJECT(&chip->occ), true, "realized", &error);
961 if (error) {
962 error_propagate(errp, error);
963 return;
964 }
965 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip->occ.xscom_regs);
966 }
967
968 static Property pnv_chip_properties[] = {
969 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
970 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
971 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
972 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
973 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
974 DEFINE_PROP_END_OF_LIST(),
975 };
976
977 static void pnv_chip_class_init(ObjectClass *klass, void *data)
978 {
979 DeviceClass *dc = DEVICE_CLASS(klass);
980
981 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
982 dc->realize = pnv_chip_realize;
983 dc->props = pnv_chip_properties;
984 dc->desc = "PowerNV Chip";
985 }
986
987 static const TypeInfo pnv_chip_info = {
988 .name = TYPE_PNV_CHIP,
989 .parent = TYPE_SYS_BUS_DEVICE,
990 .class_init = pnv_chip_class_init,
991 .instance_init = pnv_chip_init,
992 .class_size = sizeof(PnvChipClass),
993 .abstract = true,
994 };
995
996 static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
997 {
998 PnvMachineState *pnv = POWERNV_MACHINE(xi);
999 int i;
1000
1001 for (i = 0; i < pnv->num_chips; i++) {
1002 if (ics_valid_irq(&pnv->chips[i]->psi.ics, irq)) {
1003 return &pnv->chips[i]->psi.ics;
1004 }
1005 }
1006 return NULL;
1007 }
1008
1009 static void pnv_ics_resend(XICSFabric *xi)
1010 {
1011 PnvMachineState *pnv = POWERNV_MACHINE(xi);
1012 int i;
1013
1014 for (i = 0; i < pnv->num_chips; i++) {
1015 ics_resend(&pnv->chips[i]->psi.ics);
1016 }
1017 }
1018
1019 static PowerPCCPU *ppc_get_vcpu_by_pir(int pir)
1020 {
1021 CPUState *cs;
1022
1023 CPU_FOREACH(cs) {
1024 PowerPCCPU *cpu = POWERPC_CPU(cs);
1025 CPUPPCState *env = &cpu->env;
1026
1027 if (env->spr_cb[SPR_PIR].default_value == pir) {
1028 return cpu;
1029 }
1030 }
1031
1032 return NULL;
1033 }
1034
1035 static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
1036 {
1037 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
1038
1039 return cpu ? ICP(cpu->intc) : NULL;
1040 }
1041
1042 static void pnv_pic_print_info(InterruptStatsProvider *obj,
1043 Monitor *mon)
1044 {
1045 PnvMachineState *pnv = POWERNV_MACHINE(obj);
1046 int i;
1047 CPUState *cs;
1048
1049 CPU_FOREACH(cs) {
1050 PowerPCCPU *cpu = POWERPC_CPU(cs);
1051
1052 icp_pic_print_info(ICP(cpu->intc), mon);
1053 }
1054
1055 for (i = 0; i < pnv->num_chips; i++) {
1056 ics_pic_print_info(&pnv->chips[i]->psi.ics, mon);
1057 }
1058 }
1059
1060 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name,
1061 void *opaque, Error **errp)
1062 {
1063 visit_type_uint32(v, name, &POWERNV_MACHINE(obj)->num_chips, errp);
1064 }
1065
1066 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name,
1067 void *opaque, Error **errp)
1068 {
1069 PnvMachineState *pnv = POWERNV_MACHINE(obj);
1070 uint32_t num_chips;
1071 Error *local_err = NULL;
1072
1073 visit_type_uint32(v, name, &num_chips, &local_err);
1074 if (local_err) {
1075 error_propagate(errp, local_err);
1076 return;
1077 }
1078
1079 /*
1080 * TODO: should we decide on how many chips we can create based
1081 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
1082 */
1083 if (!is_power_of_2(num_chips) || num_chips > 4) {
1084 error_setg(errp, "invalid number of chips: '%d'", num_chips);
1085 return;
1086 }
1087
1088 pnv->num_chips = num_chips;
1089 }
1090
1091 static void powernv_machine_initfn(Object *obj)
1092 {
1093 PnvMachineState *pnv = POWERNV_MACHINE(obj);
1094 pnv->num_chips = 1;
1095 }
1096
1097 static void powernv_machine_class_props_init(ObjectClass *oc)
1098 {
1099 object_class_property_add(oc, "num-chips", "uint32_t",
1100 pnv_get_num_chips, pnv_set_num_chips,
1101 NULL, NULL, NULL);
1102 object_class_property_set_description(oc, "num-chips",
1103 "Specifies the number of processor chips",
1104 NULL);
1105 }
1106
1107 static void powernv_machine_class_init(ObjectClass *oc, void *data)
1108 {
1109 MachineClass *mc = MACHINE_CLASS(oc);
1110 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
1111 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
1112
1113 mc->desc = "IBM PowerNV (Non-Virtualized)";
1114 mc->init = ppc_powernv_init;
1115 mc->reset = ppc_powernv_reset;
1116 mc->max_cpus = MAX_CPUS;
1117 mc->block_default_type = IF_IDE; /* Pnv provides a AHCI device for
1118 * storage */
1119 mc->no_parallel = 1;
1120 mc->default_boot_order = NULL;
1121 mc->default_ram_size = 1 * G_BYTE;
1122 xic->icp_get = pnv_icp_get;
1123 xic->ics_get = pnv_ics_get;
1124 xic->ics_resend = pnv_ics_resend;
1125 ispc->print_info = pnv_pic_print_info;
1126
1127 powernv_machine_class_props_init(oc);
1128 }
1129
1130 static const TypeInfo powernv_machine_info = {
1131 .name = TYPE_POWERNV_MACHINE,
1132 .parent = TYPE_MACHINE,
1133 .instance_size = sizeof(PnvMachineState),
1134 .instance_init = powernv_machine_initfn,
1135 .class_init = powernv_machine_class_init,
1136 .interfaces = (InterfaceInfo[]) {
1137 { TYPE_XICS_FABRIC },
1138 { TYPE_INTERRUPT_STATS_PROVIDER },
1139 { },
1140 },
1141 };
1142
1143 static void powernv_machine_register_types(void)
1144 {
1145 type_register_static(&powernv_machine_info);
1146 type_register_static(&pnv_chip_info);
1147 type_register_static(&pnv_chip_power8e_info);
1148 type_register_static(&pnv_chip_power8_info);
1149 type_register_static(&pnv_chip_power8nvl_info);
1150 type_register_static(&pnv_chip_power9_info);
1151 }
1152
1153 type_init(powernv_machine_register_types)