ppc/pnv: enable only one LPC bus
[qemu.git] / hw / ppc / pnv.c
1 /*
2 * QEMU PowerPC PowerNV machine model
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "sysemu/sysemu.h"
23 #include "sysemu/numa.h"
24 #include "sysemu/cpus.h"
25 #include "hw/hw.h"
26 #include "target/ppc/cpu.h"
27 #include "qemu/log.h"
28 #include "hw/ppc/fdt.h"
29 #include "hw/ppc/ppc.h"
30 #include "hw/ppc/pnv.h"
31 #include "hw/ppc/pnv_core.h"
32 #include "hw/loader.h"
33 #include "exec/address-spaces.h"
34 #include "qemu/cutils.h"
35 #include "qapi/visitor.h"
36 #include "monitor/monitor.h"
37 #include "hw/intc/intc.h"
38
39 #include "hw/ppc/xics.h"
40 #include "hw/ppc/pnv_xscom.h"
41
42 #include "hw/isa/isa.h"
43 #include "hw/char/serial.h"
44 #include "hw/timer/mc146818rtc.h"
45
46 #include <libfdt.h>
47
48 #define FDT_MAX_SIZE 0x00100000
49
50 #define FW_FILE_NAME "skiboot.lid"
51 #define FW_LOAD_ADDR 0x0
52 #define FW_MAX_SIZE 0x00400000
53
54 #define KERNEL_LOAD_ADDR 0x20000000
55 #define INITRD_LOAD_ADDR 0x40000000
56
57 /*
58 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
59 * 4 * 4 sockets * 12 cores * 8 threads = 1536
60 * Let's make it 2^11
61 */
62 #define MAX_CPUS 2048
63
64 /*
65 * Memory nodes are created by hostboot, one for each range of memory
66 * that has a different "affinity". In practice, it means one range
67 * per chip.
68 */
69 static void powernv_populate_memory_node(void *fdt, int chip_id, hwaddr start,
70 hwaddr size)
71 {
72 char *mem_name;
73 uint64_t mem_reg_property[2];
74 int off;
75
76 mem_reg_property[0] = cpu_to_be64(start);
77 mem_reg_property[1] = cpu_to_be64(size);
78
79 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
80 off = fdt_add_subnode(fdt, 0, mem_name);
81 g_free(mem_name);
82
83 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
84 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
85 sizeof(mem_reg_property))));
86 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
87 }
88
89 static int get_cpus_node(void *fdt)
90 {
91 int cpus_offset = fdt_path_offset(fdt, "/cpus");
92
93 if (cpus_offset < 0) {
94 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
95 "cpus");
96 if (cpus_offset) {
97 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
98 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
99 }
100 }
101 _FDT(cpus_offset);
102 return cpus_offset;
103 }
104
105 /*
106 * The PowerNV cores (and threads) need to use real HW ids and not an
107 * incremental index like it has been done on other platforms. This HW
108 * id is stored in the CPU PIR, it is used to create cpu nodes in the
109 * device tree, used in XSCOM to address cores and in interrupt
110 * servers.
111 */
112 static void powernv_create_core_node(PnvChip *chip, PnvCore *pc, void *fdt)
113 {
114 CPUState *cs = CPU(DEVICE(pc->threads));
115 DeviceClass *dc = DEVICE_GET_CLASS(cs);
116 PowerPCCPU *cpu = POWERPC_CPU(cs);
117 int smt_threads = CPU_CORE(pc)->nr_threads;
118 CPUPPCState *env = &cpu->env;
119 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
120 uint32_t servers_prop[smt_threads];
121 int i;
122 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
123 0xffffffff, 0xffffffff};
124 uint32_t tbfreq = PNV_TIMEBASE_FREQ;
125 uint32_t cpufreq = 1000000000;
126 uint32_t page_sizes_prop[64];
127 size_t page_sizes_prop_size;
128 const uint8_t pa_features[] = { 24, 0,
129 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
130 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
131 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
132 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
133 int offset;
134 char *nodename;
135 int cpus_offset = get_cpus_node(fdt);
136
137 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
138 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
139 _FDT(offset);
140 g_free(nodename);
141
142 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
143
144 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
145 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
146 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
147
148 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
149 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
150 env->dcache_line_size)));
151 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
152 env->dcache_line_size)));
153 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
154 env->icache_line_size)));
155 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
156 env->icache_line_size)));
157
158 if (pcc->l1_dcache_size) {
159 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
160 pcc->l1_dcache_size)));
161 } else {
162 error_report("Warning: Unknown L1 dcache size for cpu");
163 }
164 if (pcc->l1_icache_size) {
165 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
166 pcc->l1_icache_size)));
167 } else {
168 error_report("Warning: Unknown L1 icache size for cpu");
169 }
170
171 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
172 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
173 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
174 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
175 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
176
177 if (env->spr_cb[SPR_PURR].oea_read) {
178 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
179 }
180
181 if (env->mmu_model & POWERPC_MMU_1TSEG) {
182 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
183 segs, sizeof(segs))));
184 }
185
186 /* Advertise VMX/VSX (vector extensions) if available
187 * 0 / no property == no vector extensions
188 * 1 == VMX / Altivec available
189 * 2 == VSX available */
190 if (env->insns_flags & PPC_ALTIVEC) {
191 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
192
193 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
194 }
195
196 /* Advertise DFP (Decimal Floating Point) if available
197 * 0 / no property == no DFP
198 * 1 == DFP available */
199 if (env->insns_flags2 & PPC2_DFP) {
200 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
201 }
202
203 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
204 sizeof(page_sizes_prop));
205 if (page_sizes_prop_size) {
206 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
207 page_sizes_prop, page_sizes_prop_size)));
208 }
209
210 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
211 pa_features, sizeof(pa_features))));
212
213 /* Build interrupt servers properties */
214 for (i = 0; i < smt_threads; i++) {
215 servers_prop[i] = cpu_to_be32(pc->pir + i);
216 }
217 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
218 servers_prop, sizeof(servers_prop))));
219 }
220
221 static void powernv_populate_icp(PnvChip *chip, void *fdt, uint32_t pir,
222 uint32_t nr_threads)
223 {
224 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
225 char *name;
226 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
227 uint32_t irange[2], i, rsize;
228 uint64_t *reg;
229 int offset;
230
231 irange[0] = cpu_to_be32(pir);
232 irange[1] = cpu_to_be32(nr_threads);
233
234 rsize = sizeof(uint64_t) * 2 * nr_threads;
235 reg = g_malloc(rsize);
236 for (i = 0; i < nr_threads; i++) {
237 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
238 reg[i * 2 + 1] = cpu_to_be64(0x1000);
239 }
240
241 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
242 offset = fdt_add_subnode(fdt, 0, name);
243 _FDT(offset);
244 g_free(name);
245
246 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
247 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
248 _FDT((fdt_setprop_string(fdt, offset, "device_type",
249 "PowerPC-External-Interrupt-Presentation")));
250 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
251 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
252 irange, sizeof(irange))));
253 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
254 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
255 g_free(reg);
256 }
257
258 static int pnv_chip_lpc_offset(PnvChip *chip, void *fdt)
259 {
260 char *name;
261 int offset;
262
263 name = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
264 (uint64_t) PNV_XSCOM_BASE(chip), PNV_XSCOM_LPC_BASE);
265 offset = fdt_path_offset(fdt, name);
266 g_free(name);
267 return offset;
268 }
269
270 static void powernv_populate_chip(PnvChip *chip, void *fdt)
271 {
272 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
273 char *typename = pnv_core_typename(pcc->cpu_model);
274 size_t typesize = object_type_get_instance_size(typename);
275 int i;
276
277 pnv_xscom_populate(chip, fdt, 0);
278
279 /* The default LPC bus of a multichip system is on chip 0. It's
280 * recognized by the firmware (skiboot) using a "primary"
281 * property.
282 */
283 if (chip->chip_id == 0x0) {
284 int lpc_offset = pnv_chip_lpc_offset(chip, fdt);
285
286 _FDT((fdt_setprop(fdt, lpc_offset, "primary", NULL, 0)));
287 }
288
289 for (i = 0; i < chip->nr_cores; i++) {
290 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
291
292 powernv_create_core_node(chip, pnv_core, fdt);
293
294 /* Interrupt Control Presenters (ICP). One per core. */
295 powernv_populate_icp(chip, fdt, pnv_core->pir,
296 CPU_CORE(pnv_core)->nr_threads);
297 }
298
299 if (chip->ram_size) {
300 powernv_populate_memory_node(fdt, chip->chip_id, chip->ram_start,
301 chip->ram_size);
302 }
303 g_free(typename);
304 }
305
306 static void *powernv_create_fdt(MachineState *machine)
307 {
308 const char plat_compat[] = "qemu,powernv\0ibm,powernv";
309 PnvMachineState *pnv = POWERNV_MACHINE(machine);
310 void *fdt;
311 char *buf;
312 int off;
313 int i;
314
315 fdt = g_malloc0(FDT_MAX_SIZE);
316 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
317
318 /* Root node */
319 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
320 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
321 _FDT((fdt_setprop_string(fdt, 0, "model",
322 "IBM PowerNV (emulated by qemu)")));
323 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat,
324 sizeof(plat_compat))));
325
326 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
327 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
328 if (qemu_uuid_set) {
329 _FDT((fdt_property_string(fdt, "system-id", buf)));
330 }
331 g_free(buf);
332
333 off = fdt_add_subnode(fdt, 0, "chosen");
334 if (machine->kernel_cmdline) {
335 _FDT((fdt_setprop_string(fdt, off, "bootargs",
336 machine->kernel_cmdline)));
337 }
338
339 if (pnv->initrd_size) {
340 uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
341 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
342
343 _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
344 &start_prop, sizeof(start_prop))));
345 _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
346 &end_prop, sizeof(end_prop))));
347 }
348
349 /* Populate device tree for each chip */
350 for (i = 0; i < pnv->num_chips; i++) {
351 powernv_populate_chip(pnv->chips[i], fdt);
352 }
353 return fdt;
354 }
355
356 static void ppc_powernv_reset(void)
357 {
358 MachineState *machine = MACHINE(qdev_get_machine());
359 void *fdt;
360
361 qemu_devices_reset();
362
363 fdt = powernv_create_fdt(machine);
364
365 /* Pack resulting tree */
366 _FDT((fdt_pack(fdt)));
367
368 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
369 }
370
371 static ISABus *pnv_isa_create(PnvChip *chip)
372 {
373 PnvLpcController *lpc = &chip->lpc;
374 ISABus *isa_bus;
375 qemu_irq *irqs;
376 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
377
378 /* let isa_bus_new() create its own bridge on SysBus otherwise
379 * devices speficied on the command line won't find the bus and
380 * will fail to create.
381 */
382 isa_bus = isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io,
383 &error_fatal);
384
385 irqs = pnv_lpc_isa_irq_create(lpc, pcc->chip_type, ISA_NUM_IRQS);
386
387 isa_bus_irqs(isa_bus, irqs);
388 return isa_bus;
389 }
390
391 static void ppc_powernv_init(MachineState *machine)
392 {
393 PnvMachineState *pnv = POWERNV_MACHINE(machine);
394 MemoryRegion *ram;
395 char *fw_filename;
396 long fw_size;
397 int i;
398 char *chip_typename;
399
400 /* allocate RAM */
401 if (machine->ram_size < (1 * G_BYTE)) {
402 error_report("Warning: skiboot may not work with < 1GB of RAM");
403 }
404
405 ram = g_new(MemoryRegion, 1);
406 memory_region_allocate_system_memory(ram, NULL, "ppc_powernv.ram",
407 machine->ram_size);
408 memory_region_add_subregion(get_system_memory(), 0, ram);
409
410 /* load skiboot firmware */
411 if (bios_name == NULL) {
412 bios_name = FW_FILE_NAME;
413 }
414
415 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
416
417 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE);
418 if (fw_size < 0) {
419 error_report("Could not load OPAL '%s'", fw_filename);
420 exit(1);
421 }
422 g_free(fw_filename);
423
424 /* load kernel */
425 if (machine->kernel_filename) {
426 long kernel_size;
427
428 kernel_size = load_image_targphys(machine->kernel_filename,
429 KERNEL_LOAD_ADDR, 0x2000000);
430 if (kernel_size < 0) {
431 error_report("Could not load kernel '%s'",
432 machine->kernel_filename);
433 exit(1);
434 }
435 }
436
437 /* load initrd */
438 if (machine->initrd_filename) {
439 pnv->initrd_base = INITRD_LOAD_ADDR;
440 pnv->initrd_size = load_image_targphys(machine->initrd_filename,
441 pnv->initrd_base, 0x10000000); /* 128MB max */
442 if (pnv->initrd_size < 0) {
443 error_report("Could not load initial ram disk '%s'",
444 machine->initrd_filename);
445 exit(1);
446 }
447 }
448
449 /* We need some cpu model to instantiate the PnvChip class */
450 if (machine->cpu_model == NULL) {
451 machine->cpu_model = "POWER8";
452 }
453
454 /* Create the processor chips */
455 chip_typename = g_strdup_printf(TYPE_PNV_CHIP "-%s", machine->cpu_model);
456 if (!object_class_by_name(chip_typename)) {
457 error_report("qemu: invalid CPU model '%s' for %s machine",
458 machine->cpu_model, MACHINE_GET_CLASS(machine)->name);
459 exit(1);
460 }
461
462 pnv->chips = g_new0(PnvChip *, pnv->num_chips);
463 for (i = 0; i < pnv->num_chips; i++) {
464 char chip_name[32];
465 Object *chip = object_new(chip_typename);
466
467 pnv->chips[i] = PNV_CHIP(chip);
468
469 /* TODO: put all the memory in one node on chip 0 until we find a
470 * way to specify different ranges for each chip
471 */
472 if (i == 0) {
473 object_property_set_int(chip, machine->ram_size, "ram-size",
474 &error_fatal);
475 }
476
477 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i));
478 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal);
479 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id",
480 &error_fatal);
481 object_property_set_int(chip, smp_cores, "nr-cores", &error_fatal);
482 object_property_set_bool(chip, true, "realized", &error_fatal);
483 }
484 g_free(chip_typename);
485
486 /* Instantiate ISA bus on chip 0 */
487 pnv->isa_bus = pnv_isa_create(pnv->chips[0]);
488
489 /* Create serial port */
490 serial_hds_isa_init(pnv->isa_bus, 0, MAX_SERIAL_PORTS);
491
492 /* Create an RTC ISA device too */
493 rtc_init(pnv->isa_bus, 2000, NULL);
494 }
495
496 /*
497 * 0:21 Reserved - Read as zeros
498 * 22:24 Chip ID
499 * 25:28 Core number
500 * 29:31 Thread ID
501 */
502 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
503 {
504 return (chip->chip_id << 7) | (core_id << 3);
505 }
506
507 /*
508 * 0:48 Reserved - Read as zeroes
509 * 49:52 Node ID
510 * 53:55 Chip ID
511 * 56 Reserved - Read as zero
512 * 57:61 Core number
513 * 62:63 Thread ID
514 *
515 * We only care about the lower bits. uint32_t is fine for the moment.
516 */
517 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
518 {
519 return (chip->chip_id << 8) | (core_id << 2);
520 }
521
522 /* Allowed core identifiers on a POWER8 Processor Chip :
523 *
524 * <EX0 reserved>
525 * EX1 - Venice only
526 * EX2 - Venice only
527 * EX3 - Venice only
528 * EX4
529 * EX5
530 * EX6
531 * <EX7,8 reserved> <reserved>
532 * EX9 - Venice only
533 * EX10 - Venice only
534 * EX11 - Venice only
535 * EX12
536 * EX13
537 * EX14
538 * <EX15 reserved>
539 */
540 #define POWER8E_CORE_MASK (0x7070ull)
541 #define POWER8_CORE_MASK (0x7e7eull)
542
543 /*
544 * POWER9 has 24 cores, ids starting at 0x20
545 */
546 #define POWER9_CORE_MASK (0xffffff00000000ull)
547
548 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
549 {
550 DeviceClass *dc = DEVICE_CLASS(klass);
551 PnvChipClass *k = PNV_CHIP_CLASS(klass);
552
553 k->cpu_model = "POWER8E";
554 k->chip_type = PNV_CHIP_POWER8E;
555 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
556 k->cores_mask = POWER8E_CORE_MASK;
557 k->core_pir = pnv_chip_core_pir_p8;
558 k->xscom_base = 0x003fc0000000000ull;
559 k->xscom_core_base = 0x10000000ull;
560 dc->desc = "PowerNV Chip POWER8E";
561 }
562
563 static const TypeInfo pnv_chip_power8e_info = {
564 .name = TYPE_PNV_CHIP_POWER8E,
565 .parent = TYPE_PNV_CHIP,
566 .instance_size = sizeof(PnvChip),
567 .class_init = pnv_chip_power8e_class_init,
568 };
569
570 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
571 {
572 DeviceClass *dc = DEVICE_CLASS(klass);
573 PnvChipClass *k = PNV_CHIP_CLASS(klass);
574
575 k->cpu_model = "POWER8";
576 k->chip_type = PNV_CHIP_POWER8;
577 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
578 k->cores_mask = POWER8_CORE_MASK;
579 k->core_pir = pnv_chip_core_pir_p8;
580 k->xscom_base = 0x003fc0000000000ull;
581 k->xscom_core_base = 0x10000000ull;
582 dc->desc = "PowerNV Chip POWER8";
583 }
584
585 static const TypeInfo pnv_chip_power8_info = {
586 .name = TYPE_PNV_CHIP_POWER8,
587 .parent = TYPE_PNV_CHIP,
588 .instance_size = sizeof(PnvChip),
589 .class_init = pnv_chip_power8_class_init,
590 };
591
592 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
593 {
594 DeviceClass *dc = DEVICE_CLASS(klass);
595 PnvChipClass *k = PNV_CHIP_CLASS(klass);
596
597 k->cpu_model = "POWER8NVL";
598 k->chip_type = PNV_CHIP_POWER8NVL;
599 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
600 k->cores_mask = POWER8_CORE_MASK;
601 k->core_pir = pnv_chip_core_pir_p8;
602 k->xscom_base = 0x003fc0000000000ull;
603 k->xscom_core_base = 0x10000000ull;
604 dc->desc = "PowerNV Chip POWER8NVL";
605 }
606
607 static const TypeInfo pnv_chip_power8nvl_info = {
608 .name = TYPE_PNV_CHIP_POWER8NVL,
609 .parent = TYPE_PNV_CHIP,
610 .instance_size = sizeof(PnvChip),
611 .class_init = pnv_chip_power8nvl_class_init,
612 };
613
614 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
615 {
616 DeviceClass *dc = DEVICE_CLASS(klass);
617 PnvChipClass *k = PNV_CHIP_CLASS(klass);
618
619 k->cpu_model = "POWER9";
620 k->chip_type = PNV_CHIP_POWER9;
621 k->chip_cfam_id = 0x100d104980000000ull; /* P9 Nimbus DD1.0 */
622 k->cores_mask = POWER9_CORE_MASK;
623 k->core_pir = pnv_chip_core_pir_p9;
624 k->xscom_base = 0x00603fc00000000ull;
625 k->xscom_core_base = 0x0ull;
626 dc->desc = "PowerNV Chip POWER9";
627 }
628
629 static const TypeInfo pnv_chip_power9_info = {
630 .name = TYPE_PNV_CHIP_POWER9,
631 .parent = TYPE_PNV_CHIP,
632 .instance_size = sizeof(PnvChip),
633 .class_init = pnv_chip_power9_class_init,
634 };
635
636 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
637 {
638 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
639 int cores_max;
640
641 /*
642 * No custom mask for this chip, let's use the default one from *
643 * the chip class
644 */
645 if (!chip->cores_mask) {
646 chip->cores_mask = pcc->cores_mask;
647 }
648
649 /* filter alien core ids ! some are reserved */
650 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
651 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
652 chip->cores_mask);
653 return;
654 }
655 chip->cores_mask &= pcc->cores_mask;
656
657 /* now that we have a sane layout, let check the number of cores */
658 cores_max = ctpop64(chip->cores_mask);
659 if (chip->nr_cores > cores_max) {
660 error_setg(errp, "warning: too many cores for chip ! Limit is %d",
661 cores_max);
662 return;
663 }
664 }
665
666 static void pnv_chip_init(Object *obj)
667 {
668 PnvChip *chip = PNV_CHIP(obj);
669 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
670
671 chip->xscom_base = pcc->xscom_base;
672
673 object_initialize(&chip->lpc, sizeof(chip->lpc), TYPE_PNV_LPC);
674 object_property_add_child(obj, "lpc", OBJECT(&chip->lpc), NULL);
675
676 object_initialize(&chip->psi, sizeof(chip->psi), TYPE_PNV_PSI);
677 object_property_add_child(obj, "psi", OBJECT(&chip->psi), NULL);
678 object_property_add_const_link(OBJECT(&chip->psi), "xics",
679 OBJECT(qdev_get_machine()), &error_abort);
680
681 object_initialize(&chip->occ, sizeof(chip->occ), TYPE_PNV_OCC);
682 object_property_add_child(obj, "occ", OBJECT(&chip->occ), NULL);
683 object_property_add_const_link(OBJECT(&chip->occ), "psi",
684 OBJECT(&chip->psi), &error_abort);
685
686 /* The LPC controller needs PSI to generate interrupts */
687 object_property_add_const_link(OBJECT(&chip->lpc), "psi",
688 OBJECT(&chip->psi), &error_abort);
689 }
690
691 static void pnv_chip_icp_realize(PnvChip *chip, Error **errp)
692 {
693 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
694 char *typename = pnv_core_typename(pcc->cpu_model);
695 size_t typesize = object_type_get_instance_size(typename);
696 int i, j;
697 char *name;
698 XICSFabric *xi = XICS_FABRIC(qdev_get_machine());
699
700 name = g_strdup_printf("icp-%x", chip->chip_id);
701 memory_region_init(&chip->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
702 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip->icp_mmio);
703 g_free(name);
704
705 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip));
706
707 /* Map the ICP registers for each thread */
708 for (i = 0; i < chip->nr_cores; i++) {
709 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
710 int core_hwid = CPU_CORE(pnv_core)->core_id;
711
712 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
713 uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
714 PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir));
715
716 memory_region_add_subregion(&chip->icp_mmio, pir << 12, &icp->mmio);
717 }
718 }
719
720 g_free(typename);
721 }
722
723 static void pnv_chip_realize(DeviceState *dev, Error **errp)
724 {
725 PnvChip *chip = PNV_CHIP(dev);
726 Error *error = NULL;
727 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
728 char *typename = pnv_core_typename(pcc->cpu_model);
729 size_t typesize = object_type_get_instance_size(typename);
730 int i, core_hwid;
731
732 if (!object_class_by_name(typename)) {
733 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
734 return;
735 }
736
737 /* XSCOM bridge */
738 pnv_xscom_realize(chip, &error);
739 if (error) {
740 error_propagate(errp, error);
741 return;
742 }
743 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
744
745 /* Cores */
746 pnv_chip_core_sanitize(chip, &error);
747 if (error) {
748 error_propagate(errp, error);
749 return;
750 }
751
752 chip->cores = g_malloc0(typesize * chip->nr_cores);
753
754 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
755 && (i < chip->nr_cores); core_hwid++) {
756 char core_name[32];
757 void *pnv_core = chip->cores + i * typesize;
758
759 if (!(chip->cores_mask & (1ull << core_hwid))) {
760 continue;
761 }
762
763 object_initialize(pnv_core, typesize, typename);
764 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
765 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core),
766 &error_fatal);
767 object_property_set_int(OBJECT(pnv_core), smp_threads, "nr-threads",
768 &error_fatal);
769 object_property_set_int(OBJECT(pnv_core), core_hwid,
770 CPU_CORE_PROP_CORE_ID, &error_fatal);
771 object_property_set_int(OBJECT(pnv_core),
772 pcc->core_pir(chip, core_hwid),
773 "pir", &error_fatal);
774 object_property_add_const_link(OBJECT(pnv_core), "xics",
775 qdev_get_machine(), &error_fatal);
776 object_property_set_bool(OBJECT(pnv_core), true, "realized",
777 &error_fatal);
778 object_unref(OBJECT(pnv_core));
779
780 /* Each core has an XSCOM MMIO region */
781 pnv_xscom_add_subregion(chip,
782 PNV_XSCOM_EX_CORE_BASE(pcc->xscom_core_base,
783 core_hwid),
784 &PNV_CORE(pnv_core)->xscom_regs);
785 i++;
786 }
787 g_free(typename);
788
789 /* Create LPC controller */
790 object_property_set_bool(OBJECT(&chip->lpc), true, "realized",
791 &error_fatal);
792 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip->lpc.xscom_regs);
793
794 /* Interrupt Management Area. This is the memory region holding
795 * all the Interrupt Control Presenter (ICP) registers */
796 pnv_chip_icp_realize(chip, &error);
797 if (error) {
798 error_propagate(errp, error);
799 return;
800 }
801
802 /* Processor Service Interface (PSI) Host Bridge */
803 object_property_set_int(OBJECT(&chip->psi), PNV_PSIHB_BASE(chip),
804 "bar", &error_fatal);
805 object_property_set_bool(OBJECT(&chip->psi), true, "realized", &error);
806 if (error) {
807 error_propagate(errp, error);
808 return;
809 }
810 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, &chip->psi.xscom_regs);
811
812 /* Create the simplified OCC model */
813 object_property_set_bool(OBJECT(&chip->occ), true, "realized", &error);
814 if (error) {
815 error_propagate(errp, error);
816 return;
817 }
818 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip->occ.xscom_regs);
819 }
820
821 static Property pnv_chip_properties[] = {
822 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
823 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
824 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
825 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
826 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
827 DEFINE_PROP_END_OF_LIST(),
828 };
829
830 static void pnv_chip_class_init(ObjectClass *klass, void *data)
831 {
832 DeviceClass *dc = DEVICE_CLASS(klass);
833
834 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
835 dc->realize = pnv_chip_realize;
836 dc->props = pnv_chip_properties;
837 dc->desc = "PowerNV Chip";
838 }
839
840 static const TypeInfo pnv_chip_info = {
841 .name = TYPE_PNV_CHIP,
842 .parent = TYPE_SYS_BUS_DEVICE,
843 .class_init = pnv_chip_class_init,
844 .instance_init = pnv_chip_init,
845 .class_size = sizeof(PnvChipClass),
846 .abstract = true,
847 };
848
849 static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
850 {
851 PnvMachineState *pnv = POWERNV_MACHINE(xi);
852 int i;
853
854 for (i = 0; i < pnv->num_chips; i++) {
855 if (ics_valid_irq(&pnv->chips[i]->psi.ics, irq)) {
856 return &pnv->chips[i]->psi.ics;
857 }
858 }
859 return NULL;
860 }
861
862 static void pnv_ics_resend(XICSFabric *xi)
863 {
864 PnvMachineState *pnv = POWERNV_MACHINE(xi);
865 int i;
866
867 for (i = 0; i < pnv->num_chips; i++) {
868 ics_resend(&pnv->chips[i]->psi.ics);
869 }
870 }
871
872 static PowerPCCPU *ppc_get_vcpu_by_pir(int pir)
873 {
874 CPUState *cs;
875
876 CPU_FOREACH(cs) {
877 PowerPCCPU *cpu = POWERPC_CPU(cs);
878 CPUPPCState *env = &cpu->env;
879
880 if (env->spr_cb[SPR_PIR].default_value == pir) {
881 return cpu;
882 }
883 }
884
885 return NULL;
886 }
887
888 static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
889 {
890 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
891
892 return cpu ? ICP(cpu->intc) : NULL;
893 }
894
895 static void pnv_pic_print_info(InterruptStatsProvider *obj,
896 Monitor *mon)
897 {
898 PnvMachineState *pnv = POWERNV_MACHINE(obj);
899 int i;
900 CPUState *cs;
901
902 CPU_FOREACH(cs) {
903 PowerPCCPU *cpu = POWERPC_CPU(cs);
904
905 icp_pic_print_info(ICP(cpu->intc), mon);
906 }
907
908 for (i = 0; i < pnv->num_chips; i++) {
909 ics_pic_print_info(&pnv->chips[i]->psi.ics, mon);
910 }
911 }
912
913 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name,
914 void *opaque, Error **errp)
915 {
916 visit_type_uint32(v, name, &POWERNV_MACHINE(obj)->num_chips, errp);
917 }
918
919 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name,
920 void *opaque, Error **errp)
921 {
922 PnvMachineState *pnv = POWERNV_MACHINE(obj);
923 uint32_t num_chips;
924 Error *local_err = NULL;
925
926 visit_type_uint32(v, name, &num_chips, &local_err);
927 if (local_err) {
928 error_propagate(errp, local_err);
929 return;
930 }
931
932 /*
933 * TODO: should we decide on how many chips we can create based
934 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
935 */
936 if (!is_power_of_2(num_chips) || num_chips > 4) {
937 error_setg(errp, "invalid number of chips: '%d'", num_chips);
938 return;
939 }
940
941 pnv->num_chips = num_chips;
942 }
943
944 static void powernv_machine_initfn(Object *obj)
945 {
946 PnvMachineState *pnv = POWERNV_MACHINE(obj);
947 pnv->num_chips = 1;
948 }
949
950 static void powernv_machine_class_props_init(ObjectClass *oc)
951 {
952 object_class_property_add(oc, "num-chips", "uint32_t",
953 pnv_get_num_chips, pnv_set_num_chips,
954 NULL, NULL, NULL);
955 object_class_property_set_description(oc, "num-chips",
956 "Specifies the number of processor chips",
957 NULL);
958 }
959
960 static void powernv_machine_class_init(ObjectClass *oc, void *data)
961 {
962 MachineClass *mc = MACHINE_CLASS(oc);
963 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
964 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
965
966 mc->desc = "IBM PowerNV (Non-Virtualized)";
967 mc->init = ppc_powernv_init;
968 mc->reset = ppc_powernv_reset;
969 mc->max_cpus = MAX_CPUS;
970 mc->block_default_type = IF_IDE; /* Pnv provides a AHCI device for
971 * storage */
972 mc->no_parallel = 1;
973 mc->default_boot_order = NULL;
974 mc->default_ram_size = 1 * G_BYTE;
975 xic->icp_get = pnv_icp_get;
976 xic->ics_get = pnv_ics_get;
977 xic->ics_resend = pnv_ics_resend;
978 ispc->print_info = pnv_pic_print_info;
979
980 powernv_machine_class_props_init(oc);
981 }
982
983 static const TypeInfo powernv_machine_info = {
984 .name = TYPE_POWERNV_MACHINE,
985 .parent = TYPE_MACHINE,
986 .instance_size = sizeof(PnvMachineState),
987 .instance_init = powernv_machine_initfn,
988 .class_init = powernv_machine_class_init,
989 .interfaces = (InterfaceInfo[]) {
990 { TYPE_XICS_FABRIC },
991 { TYPE_INTERRUPT_STATS_PROVIDER },
992 { },
993 },
994 };
995
996 static void powernv_machine_register_types(void)
997 {
998 type_register_static(&powernv_machine_info);
999 type_register_static(&pnv_chip_info);
1000 type_register_static(&pnv_chip_power8e_info);
1001 type_register_static(&pnv_chip_power8_info);
1002 type_register_static(&pnv_chip_power8nvl_info);
1003 type_register_static(&pnv_chip_power9_info);
1004 }
1005
1006 type_init(powernv_machine_register_types)