ppc/pnv: populate device tree for IPMI BT devices
[qemu.git] / hw / ppc / pnv.c
1 /*
2 * QEMU PowerPC PowerNV machine model
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "sysemu/sysemu.h"
23 #include "sysemu/numa.h"
24 #include "sysemu/cpus.h"
25 #include "hw/hw.h"
26 #include "target/ppc/cpu.h"
27 #include "qemu/log.h"
28 #include "hw/ppc/fdt.h"
29 #include "hw/ppc/ppc.h"
30 #include "hw/ppc/pnv.h"
31 #include "hw/ppc/pnv_core.h"
32 #include "hw/loader.h"
33 #include "exec/address-spaces.h"
34 #include "qemu/cutils.h"
35 #include "qapi/visitor.h"
36 #include "monitor/monitor.h"
37 #include "hw/intc/intc.h"
38
39 #include "hw/ppc/xics.h"
40 #include "hw/ppc/pnv_xscom.h"
41
42 #include "hw/isa/isa.h"
43 #include "hw/char/serial.h"
44 #include "hw/timer/mc146818rtc.h"
45
46 #include <libfdt.h>
47
48 #define FDT_MAX_SIZE 0x00100000
49
50 #define FW_FILE_NAME "skiboot.lid"
51 #define FW_LOAD_ADDR 0x0
52 #define FW_MAX_SIZE 0x00400000
53
54 #define KERNEL_LOAD_ADDR 0x20000000
55 #define INITRD_LOAD_ADDR 0x40000000
56
57 /*
58 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
59 * 4 * 4 sockets * 12 cores * 8 threads = 1536
60 * Let's make it 2^11
61 */
62 #define MAX_CPUS 2048
63
64 /*
65 * Memory nodes are created by hostboot, one for each range of memory
66 * that has a different "affinity". In practice, it means one range
67 * per chip.
68 */
69 static void powernv_populate_memory_node(void *fdt, int chip_id, hwaddr start,
70 hwaddr size)
71 {
72 char *mem_name;
73 uint64_t mem_reg_property[2];
74 int off;
75
76 mem_reg_property[0] = cpu_to_be64(start);
77 mem_reg_property[1] = cpu_to_be64(size);
78
79 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
80 off = fdt_add_subnode(fdt, 0, mem_name);
81 g_free(mem_name);
82
83 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
84 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
85 sizeof(mem_reg_property))));
86 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
87 }
88
89 static int get_cpus_node(void *fdt)
90 {
91 int cpus_offset = fdt_path_offset(fdt, "/cpus");
92
93 if (cpus_offset < 0) {
94 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
95 "cpus");
96 if (cpus_offset) {
97 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
98 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
99 }
100 }
101 _FDT(cpus_offset);
102 return cpus_offset;
103 }
104
105 /*
106 * The PowerNV cores (and threads) need to use real HW ids and not an
107 * incremental index like it has been done on other platforms. This HW
108 * id is stored in the CPU PIR, it is used to create cpu nodes in the
109 * device tree, used in XSCOM to address cores and in interrupt
110 * servers.
111 */
112 static void powernv_create_core_node(PnvChip *chip, PnvCore *pc, void *fdt)
113 {
114 CPUState *cs = CPU(DEVICE(pc->threads));
115 DeviceClass *dc = DEVICE_GET_CLASS(cs);
116 PowerPCCPU *cpu = POWERPC_CPU(cs);
117 int smt_threads = CPU_CORE(pc)->nr_threads;
118 CPUPPCState *env = &cpu->env;
119 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
120 uint32_t servers_prop[smt_threads];
121 int i;
122 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
123 0xffffffff, 0xffffffff};
124 uint32_t tbfreq = PNV_TIMEBASE_FREQ;
125 uint32_t cpufreq = 1000000000;
126 uint32_t page_sizes_prop[64];
127 size_t page_sizes_prop_size;
128 const uint8_t pa_features[] = { 24, 0,
129 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
130 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
131 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
132 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
133 int offset;
134 char *nodename;
135 int cpus_offset = get_cpus_node(fdt);
136
137 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
138 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
139 _FDT(offset);
140 g_free(nodename);
141
142 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
143
144 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
145 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
146 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
147
148 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
149 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
150 env->dcache_line_size)));
151 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
152 env->dcache_line_size)));
153 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
154 env->icache_line_size)));
155 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
156 env->icache_line_size)));
157
158 if (pcc->l1_dcache_size) {
159 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
160 pcc->l1_dcache_size)));
161 } else {
162 error_report("Warning: Unknown L1 dcache size for cpu");
163 }
164 if (pcc->l1_icache_size) {
165 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
166 pcc->l1_icache_size)));
167 } else {
168 error_report("Warning: Unknown L1 icache size for cpu");
169 }
170
171 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
172 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
173 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
174 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
175 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
176
177 if (env->spr_cb[SPR_PURR].oea_read) {
178 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
179 }
180
181 if (env->mmu_model & POWERPC_MMU_1TSEG) {
182 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
183 segs, sizeof(segs))));
184 }
185
186 /* Advertise VMX/VSX (vector extensions) if available
187 * 0 / no property == no vector extensions
188 * 1 == VMX / Altivec available
189 * 2 == VSX available */
190 if (env->insns_flags & PPC_ALTIVEC) {
191 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
192
193 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
194 }
195
196 /* Advertise DFP (Decimal Floating Point) if available
197 * 0 / no property == no DFP
198 * 1 == DFP available */
199 if (env->insns_flags2 & PPC2_DFP) {
200 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
201 }
202
203 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
204 sizeof(page_sizes_prop));
205 if (page_sizes_prop_size) {
206 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
207 page_sizes_prop, page_sizes_prop_size)));
208 }
209
210 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
211 pa_features, sizeof(pa_features))));
212
213 /* Build interrupt servers properties */
214 for (i = 0; i < smt_threads; i++) {
215 servers_prop[i] = cpu_to_be32(pc->pir + i);
216 }
217 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
218 servers_prop, sizeof(servers_prop))));
219 }
220
221 static void powernv_populate_icp(PnvChip *chip, void *fdt, uint32_t pir,
222 uint32_t nr_threads)
223 {
224 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
225 char *name;
226 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
227 uint32_t irange[2], i, rsize;
228 uint64_t *reg;
229 int offset;
230
231 irange[0] = cpu_to_be32(pir);
232 irange[1] = cpu_to_be32(nr_threads);
233
234 rsize = sizeof(uint64_t) * 2 * nr_threads;
235 reg = g_malloc(rsize);
236 for (i = 0; i < nr_threads; i++) {
237 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
238 reg[i * 2 + 1] = cpu_to_be64(0x1000);
239 }
240
241 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
242 offset = fdt_add_subnode(fdt, 0, name);
243 _FDT(offset);
244 g_free(name);
245
246 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
247 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
248 _FDT((fdt_setprop_string(fdt, offset, "device_type",
249 "PowerPC-External-Interrupt-Presentation")));
250 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
251 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
252 irange, sizeof(irange))));
253 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
254 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
255 g_free(reg);
256 }
257
258 static int pnv_chip_lpc_offset(PnvChip *chip, void *fdt)
259 {
260 char *name;
261 int offset;
262
263 name = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
264 (uint64_t) PNV_XSCOM_BASE(chip), PNV_XSCOM_LPC_BASE);
265 offset = fdt_path_offset(fdt, name);
266 g_free(name);
267 return offset;
268 }
269
270 static void powernv_populate_chip(PnvChip *chip, void *fdt)
271 {
272 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
273 char *typename = pnv_core_typename(pcc->cpu_model);
274 size_t typesize = object_type_get_instance_size(typename);
275 int i;
276
277 pnv_xscom_populate(chip, fdt, 0);
278
279 /* The default LPC bus of a multichip system is on chip 0. It's
280 * recognized by the firmware (skiboot) using a "primary"
281 * property.
282 */
283 if (chip->chip_id == 0x0) {
284 int lpc_offset = pnv_chip_lpc_offset(chip, fdt);
285
286 _FDT((fdt_setprop(fdt, lpc_offset, "primary", NULL, 0)));
287 }
288
289 for (i = 0; i < chip->nr_cores; i++) {
290 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
291
292 powernv_create_core_node(chip, pnv_core, fdt);
293
294 /* Interrupt Control Presenters (ICP). One per core. */
295 powernv_populate_icp(chip, fdt, pnv_core->pir,
296 CPU_CORE(pnv_core)->nr_threads);
297 }
298
299 if (chip->ram_size) {
300 powernv_populate_memory_node(fdt, chip->chip_id, chip->ram_start,
301 chip->ram_size);
302 }
303 g_free(typename);
304 }
305
306 static void powernv_populate_rtc(ISADevice *d, void *fdt, int lpc_off)
307 {
308 uint32_t io_base = d->ioport_id;
309 uint32_t io_regs[] = {
310 cpu_to_be32(1),
311 cpu_to_be32(io_base),
312 cpu_to_be32(2)
313 };
314 char *name;
315 int node;
316
317 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
318 node = fdt_add_subnode(fdt, lpc_off, name);
319 _FDT(node);
320 g_free(name);
321
322 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
323 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
324 }
325
326 static void powernv_populate_serial(ISADevice *d, void *fdt, int lpc_off)
327 {
328 const char compatible[] = "ns16550\0pnpPNP,501";
329 uint32_t io_base = d->ioport_id;
330 uint32_t io_regs[] = {
331 cpu_to_be32(1),
332 cpu_to_be32(io_base),
333 cpu_to_be32(8)
334 };
335 char *name;
336 int node;
337
338 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
339 node = fdt_add_subnode(fdt, lpc_off, name);
340 _FDT(node);
341 g_free(name);
342
343 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
344 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
345 sizeof(compatible))));
346
347 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
348 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
349 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0])));
350 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
351 fdt_get_phandle(fdt, lpc_off))));
352
353 /* This is needed by Linux */
354 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
355 }
356
357 static void powernv_populate_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
358 {
359 const char compatible[] = "bt\0ipmi-bt";
360 uint32_t io_base;
361 uint32_t io_regs[] = {
362 cpu_to_be32(1),
363 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
364 cpu_to_be32(3)
365 };
366 uint32_t irq;
367 char *name;
368 int node;
369
370 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal);
371 io_regs[1] = cpu_to_be32(io_base);
372
373 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal);
374
375 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
376 node = fdt_add_subnode(fdt, lpc_off, name);
377 _FDT(node);
378 g_free(name);
379
380 fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs));
381 fdt_setprop(fdt, node, "compatible", compatible, sizeof(compatible));
382
383 /* Mark it as reserved to avoid Linux trying to claim it */
384 _FDT((fdt_setprop_string(fdt, node, "status", "reserved")));
385 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
386 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
387 fdt_get_phandle(fdt, lpc_off))));
388 }
389
390 typedef struct ForeachPopulateArgs {
391 void *fdt;
392 int offset;
393 } ForeachPopulateArgs;
394
395 static int powernv_populate_isa_device(DeviceState *dev, void *opaque)
396 {
397 ForeachPopulateArgs *args = opaque;
398 ISADevice *d = ISA_DEVICE(dev);
399
400 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
401 powernv_populate_rtc(d, args->fdt, args->offset);
402 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
403 powernv_populate_serial(d, args->fdt, args->offset);
404 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) {
405 powernv_populate_ipmi_bt(d, args->fdt, args->offset);
406 } else {
407 error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
408 d->ioport_id);
409 }
410
411 return 0;
412 }
413
414 static void powernv_populate_isa(ISABus *bus, void *fdt, int lpc_offset)
415 {
416 ForeachPopulateArgs args = {
417 .fdt = fdt,
418 .offset = lpc_offset,
419 };
420
421 /* ISA devices are not necessarily parented to the ISA bus so we
422 * can not use object_child_foreach() */
423 qbus_walk_children(BUS(bus), powernv_populate_isa_device,
424 NULL, NULL, NULL, &args);
425 }
426
427 static void *powernv_create_fdt(MachineState *machine)
428 {
429 const char plat_compat[] = "qemu,powernv\0ibm,powernv";
430 PnvMachineState *pnv = POWERNV_MACHINE(machine);
431 void *fdt;
432 char *buf;
433 int off;
434 int i;
435 int lpc_offset;
436
437 fdt = g_malloc0(FDT_MAX_SIZE);
438 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
439
440 /* Root node */
441 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
442 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
443 _FDT((fdt_setprop_string(fdt, 0, "model",
444 "IBM PowerNV (emulated by qemu)")));
445 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat,
446 sizeof(plat_compat))));
447
448 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
449 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
450 if (qemu_uuid_set) {
451 _FDT((fdt_property_string(fdt, "system-id", buf)));
452 }
453 g_free(buf);
454
455 off = fdt_add_subnode(fdt, 0, "chosen");
456 if (machine->kernel_cmdline) {
457 _FDT((fdt_setprop_string(fdt, off, "bootargs",
458 machine->kernel_cmdline)));
459 }
460
461 if (pnv->initrd_size) {
462 uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
463 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
464
465 _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
466 &start_prop, sizeof(start_prop))));
467 _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
468 &end_prop, sizeof(end_prop))));
469 }
470
471 /* Populate device tree for each chip */
472 for (i = 0; i < pnv->num_chips; i++) {
473 powernv_populate_chip(pnv->chips[i], fdt);
474 }
475
476 /* Populate ISA devices on chip 0 */
477 lpc_offset = pnv_chip_lpc_offset(pnv->chips[0], fdt);
478 powernv_populate_isa(pnv->isa_bus, fdt, lpc_offset);
479 return fdt;
480 }
481
482 static void ppc_powernv_reset(void)
483 {
484 MachineState *machine = MACHINE(qdev_get_machine());
485 void *fdt;
486
487 qemu_devices_reset();
488
489 fdt = powernv_create_fdt(machine);
490
491 /* Pack resulting tree */
492 _FDT((fdt_pack(fdt)));
493
494 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
495 }
496
497 static ISABus *pnv_isa_create(PnvChip *chip)
498 {
499 PnvLpcController *lpc = &chip->lpc;
500 ISABus *isa_bus;
501 qemu_irq *irqs;
502 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
503
504 /* let isa_bus_new() create its own bridge on SysBus otherwise
505 * devices speficied on the command line won't find the bus and
506 * will fail to create.
507 */
508 isa_bus = isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io,
509 &error_fatal);
510
511 irqs = pnv_lpc_isa_irq_create(lpc, pcc->chip_type, ISA_NUM_IRQS);
512
513 isa_bus_irqs(isa_bus, irqs);
514 return isa_bus;
515 }
516
517 static void ppc_powernv_init(MachineState *machine)
518 {
519 PnvMachineState *pnv = POWERNV_MACHINE(machine);
520 MemoryRegion *ram;
521 char *fw_filename;
522 long fw_size;
523 int i;
524 char *chip_typename;
525
526 /* allocate RAM */
527 if (machine->ram_size < (1 * G_BYTE)) {
528 error_report("Warning: skiboot may not work with < 1GB of RAM");
529 }
530
531 ram = g_new(MemoryRegion, 1);
532 memory_region_allocate_system_memory(ram, NULL, "ppc_powernv.ram",
533 machine->ram_size);
534 memory_region_add_subregion(get_system_memory(), 0, ram);
535
536 /* load skiboot firmware */
537 if (bios_name == NULL) {
538 bios_name = FW_FILE_NAME;
539 }
540
541 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
542
543 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE);
544 if (fw_size < 0) {
545 error_report("Could not load OPAL '%s'", fw_filename);
546 exit(1);
547 }
548 g_free(fw_filename);
549
550 /* load kernel */
551 if (machine->kernel_filename) {
552 long kernel_size;
553
554 kernel_size = load_image_targphys(machine->kernel_filename,
555 KERNEL_LOAD_ADDR, 0x2000000);
556 if (kernel_size < 0) {
557 error_report("Could not load kernel '%s'",
558 machine->kernel_filename);
559 exit(1);
560 }
561 }
562
563 /* load initrd */
564 if (machine->initrd_filename) {
565 pnv->initrd_base = INITRD_LOAD_ADDR;
566 pnv->initrd_size = load_image_targphys(machine->initrd_filename,
567 pnv->initrd_base, 0x10000000); /* 128MB max */
568 if (pnv->initrd_size < 0) {
569 error_report("Could not load initial ram disk '%s'",
570 machine->initrd_filename);
571 exit(1);
572 }
573 }
574
575 /* We need some cpu model to instantiate the PnvChip class */
576 if (machine->cpu_model == NULL) {
577 machine->cpu_model = "POWER8";
578 }
579
580 /* Create the processor chips */
581 chip_typename = g_strdup_printf(TYPE_PNV_CHIP "-%s", machine->cpu_model);
582 if (!object_class_by_name(chip_typename)) {
583 error_report("qemu: invalid CPU model '%s' for %s machine",
584 machine->cpu_model, MACHINE_GET_CLASS(machine)->name);
585 exit(1);
586 }
587
588 pnv->chips = g_new0(PnvChip *, pnv->num_chips);
589 for (i = 0; i < pnv->num_chips; i++) {
590 char chip_name[32];
591 Object *chip = object_new(chip_typename);
592
593 pnv->chips[i] = PNV_CHIP(chip);
594
595 /* TODO: put all the memory in one node on chip 0 until we find a
596 * way to specify different ranges for each chip
597 */
598 if (i == 0) {
599 object_property_set_int(chip, machine->ram_size, "ram-size",
600 &error_fatal);
601 }
602
603 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i));
604 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal);
605 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id",
606 &error_fatal);
607 object_property_set_int(chip, smp_cores, "nr-cores", &error_fatal);
608 object_property_set_bool(chip, true, "realized", &error_fatal);
609 }
610 g_free(chip_typename);
611
612 /* Instantiate ISA bus on chip 0 */
613 pnv->isa_bus = pnv_isa_create(pnv->chips[0]);
614
615 /* Create serial port */
616 serial_hds_isa_init(pnv->isa_bus, 0, MAX_SERIAL_PORTS);
617
618 /* Create an RTC ISA device too */
619 rtc_init(pnv->isa_bus, 2000, NULL);
620 }
621
622 /*
623 * 0:21 Reserved - Read as zeros
624 * 22:24 Chip ID
625 * 25:28 Core number
626 * 29:31 Thread ID
627 */
628 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
629 {
630 return (chip->chip_id << 7) | (core_id << 3);
631 }
632
633 /*
634 * 0:48 Reserved - Read as zeroes
635 * 49:52 Node ID
636 * 53:55 Chip ID
637 * 56 Reserved - Read as zero
638 * 57:61 Core number
639 * 62:63 Thread ID
640 *
641 * We only care about the lower bits. uint32_t is fine for the moment.
642 */
643 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
644 {
645 return (chip->chip_id << 8) | (core_id << 2);
646 }
647
648 /* Allowed core identifiers on a POWER8 Processor Chip :
649 *
650 * <EX0 reserved>
651 * EX1 - Venice only
652 * EX2 - Venice only
653 * EX3 - Venice only
654 * EX4
655 * EX5
656 * EX6
657 * <EX7,8 reserved> <reserved>
658 * EX9 - Venice only
659 * EX10 - Venice only
660 * EX11 - Venice only
661 * EX12
662 * EX13
663 * EX14
664 * <EX15 reserved>
665 */
666 #define POWER8E_CORE_MASK (0x7070ull)
667 #define POWER8_CORE_MASK (0x7e7eull)
668
669 /*
670 * POWER9 has 24 cores, ids starting at 0x20
671 */
672 #define POWER9_CORE_MASK (0xffffff00000000ull)
673
674 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
675 {
676 DeviceClass *dc = DEVICE_CLASS(klass);
677 PnvChipClass *k = PNV_CHIP_CLASS(klass);
678
679 k->cpu_model = "POWER8E";
680 k->chip_type = PNV_CHIP_POWER8E;
681 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
682 k->cores_mask = POWER8E_CORE_MASK;
683 k->core_pir = pnv_chip_core_pir_p8;
684 k->xscom_base = 0x003fc0000000000ull;
685 k->xscom_core_base = 0x10000000ull;
686 dc->desc = "PowerNV Chip POWER8E";
687 }
688
689 static const TypeInfo pnv_chip_power8e_info = {
690 .name = TYPE_PNV_CHIP_POWER8E,
691 .parent = TYPE_PNV_CHIP,
692 .instance_size = sizeof(PnvChip),
693 .class_init = pnv_chip_power8e_class_init,
694 };
695
696 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
697 {
698 DeviceClass *dc = DEVICE_CLASS(klass);
699 PnvChipClass *k = PNV_CHIP_CLASS(klass);
700
701 k->cpu_model = "POWER8";
702 k->chip_type = PNV_CHIP_POWER8;
703 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
704 k->cores_mask = POWER8_CORE_MASK;
705 k->core_pir = pnv_chip_core_pir_p8;
706 k->xscom_base = 0x003fc0000000000ull;
707 k->xscom_core_base = 0x10000000ull;
708 dc->desc = "PowerNV Chip POWER8";
709 }
710
711 static const TypeInfo pnv_chip_power8_info = {
712 .name = TYPE_PNV_CHIP_POWER8,
713 .parent = TYPE_PNV_CHIP,
714 .instance_size = sizeof(PnvChip),
715 .class_init = pnv_chip_power8_class_init,
716 };
717
718 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
719 {
720 DeviceClass *dc = DEVICE_CLASS(klass);
721 PnvChipClass *k = PNV_CHIP_CLASS(klass);
722
723 k->cpu_model = "POWER8NVL";
724 k->chip_type = PNV_CHIP_POWER8NVL;
725 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
726 k->cores_mask = POWER8_CORE_MASK;
727 k->core_pir = pnv_chip_core_pir_p8;
728 k->xscom_base = 0x003fc0000000000ull;
729 k->xscom_core_base = 0x10000000ull;
730 dc->desc = "PowerNV Chip POWER8NVL";
731 }
732
733 static const TypeInfo pnv_chip_power8nvl_info = {
734 .name = TYPE_PNV_CHIP_POWER8NVL,
735 .parent = TYPE_PNV_CHIP,
736 .instance_size = sizeof(PnvChip),
737 .class_init = pnv_chip_power8nvl_class_init,
738 };
739
740 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
741 {
742 DeviceClass *dc = DEVICE_CLASS(klass);
743 PnvChipClass *k = PNV_CHIP_CLASS(klass);
744
745 k->cpu_model = "POWER9";
746 k->chip_type = PNV_CHIP_POWER9;
747 k->chip_cfam_id = 0x100d104980000000ull; /* P9 Nimbus DD1.0 */
748 k->cores_mask = POWER9_CORE_MASK;
749 k->core_pir = pnv_chip_core_pir_p9;
750 k->xscom_base = 0x00603fc00000000ull;
751 k->xscom_core_base = 0x0ull;
752 dc->desc = "PowerNV Chip POWER9";
753 }
754
755 static const TypeInfo pnv_chip_power9_info = {
756 .name = TYPE_PNV_CHIP_POWER9,
757 .parent = TYPE_PNV_CHIP,
758 .instance_size = sizeof(PnvChip),
759 .class_init = pnv_chip_power9_class_init,
760 };
761
762 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
763 {
764 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
765 int cores_max;
766
767 /*
768 * No custom mask for this chip, let's use the default one from *
769 * the chip class
770 */
771 if (!chip->cores_mask) {
772 chip->cores_mask = pcc->cores_mask;
773 }
774
775 /* filter alien core ids ! some are reserved */
776 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
777 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
778 chip->cores_mask);
779 return;
780 }
781 chip->cores_mask &= pcc->cores_mask;
782
783 /* now that we have a sane layout, let check the number of cores */
784 cores_max = ctpop64(chip->cores_mask);
785 if (chip->nr_cores > cores_max) {
786 error_setg(errp, "warning: too many cores for chip ! Limit is %d",
787 cores_max);
788 return;
789 }
790 }
791
792 static void pnv_chip_init(Object *obj)
793 {
794 PnvChip *chip = PNV_CHIP(obj);
795 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
796
797 chip->xscom_base = pcc->xscom_base;
798
799 object_initialize(&chip->lpc, sizeof(chip->lpc), TYPE_PNV_LPC);
800 object_property_add_child(obj, "lpc", OBJECT(&chip->lpc), NULL);
801
802 object_initialize(&chip->psi, sizeof(chip->psi), TYPE_PNV_PSI);
803 object_property_add_child(obj, "psi", OBJECT(&chip->psi), NULL);
804 object_property_add_const_link(OBJECT(&chip->psi), "xics",
805 OBJECT(qdev_get_machine()), &error_abort);
806
807 object_initialize(&chip->occ, sizeof(chip->occ), TYPE_PNV_OCC);
808 object_property_add_child(obj, "occ", OBJECT(&chip->occ), NULL);
809 object_property_add_const_link(OBJECT(&chip->occ), "psi",
810 OBJECT(&chip->psi), &error_abort);
811
812 /* The LPC controller needs PSI to generate interrupts */
813 object_property_add_const_link(OBJECT(&chip->lpc), "psi",
814 OBJECT(&chip->psi), &error_abort);
815 }
816
817 static void pnv_chip_icp_realize(PnvChip *chip, Error **errp)
818 {
819 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
820 char *typename = pnv_core_typename(pcc->cpu_model);
821 size_t typesize = object_type_get_instance_size(typename);
822 int i, j;
823 char *name;
824 XICSFabric *xi = XICS_FABRIC(qdev_get_machine());
825
826 name = g_strdup_printf("icp-%x", chip->chip_id);
827 memory_region_init(&chip->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
828 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip->icp_mmio);
829 g_free(name);
830
831 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip));
832
833 /* Map the ICP registers for each thread */
834 for (i = 0; i < chip->nr_cores; i++) {
835 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
836 int core_hwid = CPU_CORE(pnv_core)->core_id;
837
838 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
839 uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
840 PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir));
841
842 memory_region_add_subregion(&chip->icp_mmio, pir << 12, &icp->mmio);
843 }
844 }
845
846 g_free(typename);
847 }
848
849 static void pnv_chip_realize(DeviceState *dev, Error **errp)
850 {
851 PnvChip *chip = PNV_CHIP(dev);
852 Error *error = NULL;
853 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
854 char *typename = pnv_core_typename(pcc->cpu_model);
855 size_t typesize = object_type_get_instance_size(typename);
856 int i, core_hwid;
857
858 if (!object_class_by_name(typename)) {
859 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
860 return;
861 }
862
863 /* XSCOM bridge */
864 pnv_xscom_realize(chip, &error);
865 if (error) {
866 error_propagate(errp, error);
867 return;
868 }
869 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
870
871 /* Cores */
872 pnv_chip_core_sanitize(chip, &error);
873 if (error) {
874 error_propagate(errp, error);
875 return;
876 }
877
878 chip->cores = g_malloc0(typesize * chip->nr_cores);
879
880 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
881 && (i < chip->nr_cores); core_hwid++) {
882 char core_name[32];
883 void *pnv_core = chip->cores + i * typesize;
884
885 if (!(chip->cores_mask & (1ull << core_hwid))) {
886 continue;
887 }
888
889 object_initialize(pnv_core, typesize, typename);
890 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
891 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core),
892 &error_fatal);
893 object_property_set_int(OBJECT(pnv_core), smp_threads, "nr-threads",
894 &error_fatal);
895 object_property_set_int(OBJECT(pnv_core), core_hwid,
896 CPU_CORE_PROP_CORE_ID, &error_fatal);
897 object_property_set_int(OBJECT(pnv_core),
898 pcc->core_pir(chip, core_hwid),
899 "pir", &error_fatal);
900 object_property_add_const_link(OBJECT(pnv_core), "xics",
901 qdev_get_machine(), &error_fatal);
902 object_property_set_bool(OBJECT(pnv_core), true, "realized",
903 &error_fatal);
904 object_unref(OBJECT(pnv_core));
905
906 /* Each core has an XSCOM MMIO region */
907 pnv_xscom_add_subregion(chip,
908 PNV_XSCOM_EX_CORE_BASE(pcc->xscom_core_base,
909 core_hwid),
910 &PNV_CORE(pnv_core)->xscom_regs);
911 i++;
912 }
913 g_free(typename);
914
915 /* Create LPC controller */
916 object_property_set_bool(OBJECT(&chip->lpc), true, "realized",
917 &error_fatal);
918 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip->lpc.xscom_regs);
919
920 /* Interrupt Management Area. This is the memory region holding
921 * all the Interrupt Control Presenter (ICP) registers */
922 pnv_chip_icp_realize(chip, &error);
923 if (error) {
924 error_propagate(errp, error);
925 return;
926 }
927
928 /* Processor Service Interface (PSI) Host Bridge */
929 object_property_set_int(OBJECT(&chip->psi), PNV_PSIHB_BASE(chip),
930 "bar", &error_fatal);
931 object_property_set_bool(OBJECT(&chip->psi), true, "realized", &error);
932 if (error) {
933 error_propagate(errp, error);
934 return;
935 }
936 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, &chip->psi.xscom_regs);
937
938 /* Create the simplified OCC model */
939 object_property_set_bool(OBJECT(&chip->occ), true, "realized", &error);
940 if (error) {
941 error_propagate(errp, error);
942 return;
943 }
944 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip->occ.xscom_regs);
945 }
946
947 static Property pnv_chip_properties[] = {
948 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
949 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
950 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
951 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
952 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
953 DEFINE_PROP_END_OF_LIST(),
954 };
955
956 static void pnv_chip_class_init(ObjectClass *klass, void *data)
957 {
958 DeviceClass *dc = DEVICE_CLASS(klass);
959
960 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
961 dc->realize = pnv_chip_realize;
962 dc->props = pnv_chip_properties;
963 dc->desc = "PowerNV Chip";
964 }
965
966 static const TypeInfo pnv_chip_info = {
967 .name = TYPE_PNV_CHIP,
968 .parent = TYPE_SYS_BUS_DEVICE,
969 .class_init = pnv_chip_class_init,
970 .instance_init = pnv_chip_init,
971 .class_size = sizeof(PnvChipClass),
972 .abstract = true,
973 };
974
975 static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
976 {
977 PnvMachineState *pnv = POWERNV_MACHINE(xi);
978 int i;
979
980 for (i = 0; i < pnv->num_chips; i++) {
981 if (ics_valid_irq(&pnv->chips[i]->psi.ics, irq)) {
982 return &pnv->chips[i]->psi.ics;
983 }
984 }
985 return NULL;
986 }
987
988 static void pnv_ics_resend(XICSFabric *xi)
989 {
990 PnvMachineState *pnv = POWERNV_MACHINE(xi);
991 int i;
992
993 for (i = 0; i < pnv->num_chips; i++) {
994 ics_resend(&pnv->chips[i]->psi.ics);
995 }
996 }
997
998 static PowerPCCPU *ppc_get_vcpu_by_pir(int pir)
999 {
1000 CPUState *cs;
1001
1002 CPU_FOREACH(cs) {
1003 PowerPCCPU *cpu = POWERPC_CPU(cs);
1004 CPUPPCState *env = &cpu->env;
1005
1006 if (env->spr_cb[SPR_PIR].default_value == pir) {
1007 return cpu;
1008 }
1009 }
1010
1011 return NULL;
1012 }
1013
1014 static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
1015 {
1016 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
1017
1018 return cpu ? ICP(cpu->intc) : NULL;
1019 }
1020
1021 static void pnv_pic_print_info(InterruptStatsProvider *obj,
1022 Monitor *mon)
1023 {
1024 PnvMachineState *pnv = POWERNV_MACHINE(obj);
1025 int i;
1026 CPUState *cs;
1027
1028 CPU_FOREACH(cs) {
1029 PowerPCCPU *cpu = POWERPC_CPU(cs);
1030
1031 icp_pic_print_info(ICP(cpu->intc), mon);
1032 }
1033
1034 for (i = 0; i < pnv->num_chips; i++) {
1035 ics_pic_print_info(&pnv->chips[i]->psi.ics, mon);
1036 }
1037 }
1038
1039 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name,
1040 void *opaque, Error **errp)
1041 {
1042 visit_type_uint32(v, name, &POWERNV_MACHINE(obj)->num_chips, errp);
1043 }
1044
1045 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name,
1046 void *opaque, Error **errp)
1047 {
1048 PnvMachineState *pnv = POWERNV_MACHINE(obj);
1049 uint32_t num_chips;
1050 Error *local_err = NULL;
1051
1052 visit_type_uint32(v, name, &num_chips, &local_err);
1053 if (local_err) {
1054 error_propagate(errp, local_err);
1055 return;
1056 }
1057
1058 /*
1059 * TODO: should we decide on how many chips we can create based
1060 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
1061 */
1062 if (!is_power_of_2(num_chips) || num_chips > 4) {
1063 error_setg(errp, "invalid number of chips: '%d'", num_chips);
1064 return;
1065 }
1066
1067 pnv->num_chips = num_chips;
1068 }
1069
1070 static void powernv_machine_initfn(Object *obj)
1071 {
1072 PnvMachineState *pnv = POWERNV_MACHINE(obj);
1073 pnv->num_chips = 1;
1074 }
1075
1076 static void powernv_machine_class_props_init(ObjectClass *oc)
1077 {
1078 object_class_property_add(oc, "num-chips", "uint32_t",
1079 pnv_get_num_chips, pnv_set_num_chips,
1080 NULL, NULL, NULL);
1081 object_class_property_set_description(oc, "num-chips",
1082 "Specifies the number of processor chips",
1083 NULL);
1084 }
1085
1086 static void powernv_machine_class_init(ObjectClass *oc, void *data)
1087 {
1088 MachineClass *mc = MACHINE_CLASS(oc);
1089 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
1090 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
1091
1092 mc->desc = "IBM PowerNV (Non-Virtualized)";
1093 mc->init = ppc_powernv_init;
1094 mc->reset = ppc_powernv_reset;
1095 mc->max_cpus = MAX_CPUS;
1096 mc->block_default_type = IF_IDE; /* Pnv provides a AHCI device for
1097 * storage */
1098 mc->no_parallel = 1;
1099 mc->default_boot_order = NULL;
1100 mc->default_ram_size = 1 * G_BYTE;
1101 xic->icp_get = pnv_icp_get;
1102 xic->ics_get = pnv_ics_get;
1103 xic->ics_resend = pnv_ics_resend;
1104 ispc->print_info = pnv_pic_print_info;
1105
1106 powernv_machine_class_props_init(oc);
1107 }
1108
1109 static const TypeInfo powernv_machine_info = {
1110 .name = TYPE_POWERNV_MACHINE,
1111 .parent = TYPE_MACHINE,
1112 .instance_size = sizeof(PnvMachineState),
1113 .instance_init = powernv_machine_initfn,
1114 .class_init = powernv_machine_class_init,
1115 .interfaces = (InterfaceInfo[]) {
1116 { TYPE_XICS_FABRIC },
1117 { TYPE_INTERRUPT_STATS_PROVIDER },
1118 { },
1119 },
1120 };
1121
1122 static void powernv_machine_register_types(void)
1123 {
1124 type_register_static(&powernv_machine_info);
1125 type_register_static(&pnv_chip_info);
1126 type_register_static(&pnv_chip_power8e_info);
1127 type_register_static(&pnv_chip_power8_info);
1128 type_register_static(&pnv_chip_power8nvl_info);
1129 type_register_static(&pnv_chip_power9_info);
1130 }
1131
1132 type_init(powernv_machine_register_types)