ppc/pnv: populate device tree for serial devices
[qemu.git] / hw / ppc / pnv.c
1 /*
2 * QEMU PowerPC PowerNV machine model
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "sysemu/sysemu.h"
23 #include "sysemu/numa.h"
24 #include "sysemu/cpus.h"
25 #include "hw/hw.h"
26 #include "target/ppc/cpu.h"
27 #include "qemu/log.h"
28 #include "hw/ppc/fdt.h"
29 #include "hw/ppc/ppc.h"
30 #include "hw/ppc/pnv.h"
31 #include "hw/ppc/pnv_core.h"
32 #include "hw/loader.h"
33 #include "exec/address-spaces.h"
34 #include "qemu/cutils.h"
35 #include "qapi/visitor.h"
36 #include "monitor/monitor.h"
37 #include "hw/intc/intc.h"
38
39 #include "hw/ppc/xics.h"
40 #include "hw/ppc/pnv_xscom.h"
41
42 #include "hw/isa/isa.h"
43 #include "hw/char/serial.h"
44 #include "hw/timer/mc146818rtc.h"
45
46 #include <libfdt.h>
47
48 #define FDT_MAX_SIZE 0x00100000
49
50 #define FW_FILE_NAME "skiboot.lid"
51 #define FW_LOAD_ADDR 0x0
52 #define FW_MAX_SIZE 0x00400000
53
54 #define KERNEL_LOAD_ADDR 0x20000000
55 #define INITRD_LOAD_ADDR 0x40000000
56
57 /*
58 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
59 * 4 * 4 sockets * 12 cores * 8 threads = 1536
60 * Let's make it 2^11
61 */
62 #define MAX_CPUS 2048
63
64 /*
65 * Memory nodes are created by hostboot, one for each range of memory
66 * that has a different "affinity". In practice, it means one range
67 * per chip.
68 */
69 static void powernv_populate_memory_node(void *fdt, int chip_id, hwaddr start,
70 hwaddr size)
71 {
72 char *mem_name;
73 uint64_t mem_reg_property[2];
74 int off;
75
76 mem_reg_property[0] = cpu_to_be64(start);
77 mem_reg_property[1] = cpu_to_be64(size);
78
79 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
80 off = fdt_add_subnode(fdt, 0, mem_name);
81 g_free(mem_name);
82
83 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
84 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
85 sizeof(mem_reg_property))));
86 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
87 }
88
89 static int get_cpus_node(void *fdt)
90 {
91 int cpus_offset = fdt_path_offset(fdt, "/cpus");
92
93 if (cpus_offset < 0) {
94 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
95 "cpus");
96 if (cpus_offset) {
97 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
98 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
99 }
100 }
101 _FDT(cpus_offset);
102 return cpus_offset;
103 }
104
105 /*
106 * The PowerNV cores (and threads) need to use real HW ids and not an
107 * incremental index like it has been done on other platforms. This HW
108 * id is stored in the CPU PIR, it is used to create cpu nodes in the
109 * device tree, used in XSCOM to address cores and in interrupt
110 * servers.
111 */
112 static void powernv_create_core_node(PnvChip *chip, PnvCore *pc, void *fdt)
113 {
114 CPUState *cs = CPU(DEVICE(pc->threads));
115 DeviceClass *dc = DEVICE_GET_CLASS(cs);
116 PowerPCCPU *cpu = POWERPC_CPU(cs);
117 int smt_threads = CPU_CORE(pc)->nr_threads;
118 CPUPPCState *env = &cpu->env;
119 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
120 uint32_t servers_prop[smt_threads];
121 int i;
122 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
123 0xffffffff, 0xffffffff};
124 uint32_t tbfreq = PNV_TIMEBASE_FREQ;
125 uint32_t cpufreq = 1000000000;
126 uint32_t page_sizes_prop[64];
127 size_t page_sizes_prop_size;
128 const uint8_t pa_features[] = { 24, 0,
129 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
130 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
131 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
132 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
133 int offset;
134 char *nodename;
135 int cpus_offset = get_cpus_node(fdt);
136
137 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
138 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
139 _FDT(offset);
140 g_free(nodename);
141
142 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
143
144 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
145 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
146 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
147
148 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
149 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
150 env->dcache_line_size)));
151 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
152 env->dcache_line_size)));
153 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
154 env->icache_line_size)));
155 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
156 env->icache_line_size)));
157
158 if (pcc->l1_dcache_size) {
159 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
160 pcc->l1_dcache_size)));
161 } else {
162 error_report("Warning: Unknown L1 dcache size for cpu");
163 }
164 if (pcc->l1_icache_size) {
165 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
166 pcc->l1_icache_size)));
167 } else {
168 error_report("Warning: Unknown L1 icache size for cpu");
169 }
170
171 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
172 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
173 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
174 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
175 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
176
177 if (env->spr_cb[SPR_PURR].oea_read) {
178 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
179 }
180
181 if (env->mmu_model & POWERPC_MMU_1TSEG) {
182 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
183 segs, sizeof(segs))));
184 }
185
186 /* Advertise VMX/VSX (vector extensions) if available
187 * 0 / no property == no vector extensions
188 * 1 == VMX / Altivec available
189 * 2 == VSX available */
190 if (env->insns_flags & PPC_ALTIVEC) {
191 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
192
193 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
194 }
195
196 /* Advertise DFP (Decimal Floating Point) if available
197 * 0 / no property == no DFP
198 * 1 == DFP available */
199 if (env->insns_flags2 & PPC2_DFP) {
200 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
201 }
202
203 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
204 sizeof(page_sizes_prop));
205 if (page_sizes_prop_size) {
206 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
207 page_sizes_prop, page_sizes_prop_size)));
208 }
209
210 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
211 pa_features, sizeof(pa_features))));
212
213 /* Build interrupt servers properties */
214 for (i = 0; i < smt_threads; i++) {
215 servers_prop[i] = cpu_to_be32(pc->pir + i);
216 }
217 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
218 servers_prop, sizeof(servers_prop))));
219 }
220
221 static void powernv_populate_icp(PnvChip *chip, void *fdt, uint32_t pir,
222 uint32_t nr_threads)
223 {
224 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
225 char *name;
226 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
227 uint32_t irange[2], i, rsize;
228 uint64_t *reg;
229 int offset;
230
231 irange[0] = cpu_to_be32(pir);
232 irange[1] = cpu_to_be32(nr_threads);
233
234 rsize = sizeof(uint64_t) * 2 * nr_threads;
235 reg = g_malloc(rsize);
236 for (i = 0; i < nr_threads; i++) {
237 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
238 reg[i * 2 + 1] = cpu_to_be64(0x1000);
239 }
240
241 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
242 offset = fdt_add_subnode(fdt, 0, name);
243 _FDT(offset);
244 g_free(name);
245
246 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
247 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
248 _FDT((fdt_setprop_string(fdt, offset, "device_type",
249 "PowerPC-External-Interrupt-Presentation")));
250 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
251 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
252 irange, sizeof(irange))));
253 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
254 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
255 g_free(reg);
256 }
257
258 static int pnv_chip_lpc_offset(PnvChip *chip, void *fdt)
259 {
260 char *name;
261 int offset;
262
263 name = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
264 (uint64_t) PNV_XSCOM_BASE(chip), PNV_XSCOM_LPC_BASE);
265 offset = fdt_path_offset(fdt, name);
266 g_free(name);
267 return offset;
268 }
269
270 static void powernv_populate_chip(PnvChip *chip, void *fdt)
271 {
272 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
273 char *typename = pnv_core_typename(pcc->cpu_model);
274 size_t typesize = object_type_get_instance_size(typename);
275 int i;
276
277 pnv_xscom_populate(chip, fdt, 0);
278
279 /* The default LPC bus of a multichip system is on chip 0. It's
280 * recognized by the firmware (skiboot) using a "primary"
281 * property.
282 */
283 if (chip->chip_id == 0x0) {
284 int lpc_offset = pnv_chip_lpc_offset(chip, fdt);
285
286 _FDT((fdt_setprop(fdt, lpc_offset, "primary", NULL, 0)));
287 }
288
289 for (i = 0; i < chip->nr_cores; i++) {
290 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
291
292 powernv_create_core_node(chip, pnv_core, fdt);
293
294 /* Interrupt Control Presenters (ICP). One per core. */
295 powernv_populate_icp(chip, fdt, pnv_core->pir,
296 CPU_CORE(pnv_core)->nr_threads);
297 }
298
299 if (chip->ram_size) {
300 powernv_populate_memory_node(fdt, chip->chip_id, chip->ram_start,
301 chip->ram_size);
302 }
303 g_free(typename);
304 }
305
306 static void powernv_populate_rtc(ISADevice *d, void *fdt, int lpc_off)
307 {
308 uint32_t io_base = d->ioport_id;
309 uint32_t io_regs[] = {
310 cpu_to_be32(1),
311 cpu_to_be32(io_base),
312 cpu_to_be32(2)
313 };
314 char *name;
315 int node;
316
317 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
318 node = fdt_add_subnode(fdt, lpc_off, name);
319 _FDT(node);
320 g_free(name);
321
322 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
323 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
324 }
325
326 static void powernv_populate_serial(ISADevice *d, void *fdt, int lpc_off)
327 {
328 const char compatible[] = "ns16550\0pnpPNP,501";
329 uint32_t io_base = d->ioport_id;
330 uint32_t io_regs[] = {
331 cpu_to_be32(1),
332 cpu_to_be32(io_base),
333 cpu_to_be32(8)
334 };
335 char *name;
336 int node;
337
338 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
339 node = fdt_add_subnode(fdt, lpc_off, name);
340 _FDT(node);
341 g_free(name);
342
343 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
344 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
345 sizeof(compatible))));
346
347 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
348 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
349 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0])));
350 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
351 fdt_get_phandle(fdt, lpc_off))));
352
353 /* This is needed by Linux */
354 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
355 }
356
357 typedef struct ForeachPopulateArgs {
358 void *fdt;
359 int offset;
360 } ForeachPopulateArgs;
361
362 static int powernv_populate_isa_device(DeviceState *dev, void *opaque)
363 {
364 ForeachPopulateArgs *args = opaque;
365 ISADevice *d = ISA_DEVICE(dev);
366
367 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
368 powernv_populate_rtc(d, args->fdt, args->offset);
369 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
370 powernv_populate_serial(d, args->fdt, args->offset);
371 } else {
372 error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
373 d->ioport_id);
374 }
375
376 return 0;
377 }
378
379 static void powernv_populate_isa(ISABus *bus, void *fdt, int lpc_offset)
380 {
381 ForeachPopulateArgs args = {
382 .fdt = fdt,
383 .offset = lpc_offset,
384 };
385
386 /* ISA devices are not necessarily parented to the ISA bus so we
387 * can not use object_child_foreach() */
388 qbus_walk_children(BUS(bus), powernv_populate_isa_device,
389 NULL, NULL, NULL, &args);
390 }
391
392 static void *powernv_create_fdt(MachineState *machine)
393 {
394 const char plat_compat[] = "qemu,powernv\0ibm,powernv";
395 PnvMachineState *pnv = POWERNV_MACHINE(machine);
396 void *fdt;
397 char *buf;
398 int off;
399 int i;
400 int lpc_offset;
401
402 fdt = g_malloc0(FDT_MAX_SIZE);
403 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
404
405 /* Root node */
406 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
407 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
408 _FDT((fdt_setprop_string(fdt, 0, "model",
409 "IBM PowerNV (emulated by qemu)")));
410 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat,
411 sizeof(plat_compat))));
412
413 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
414 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
415 if (qemu_uuid_set) {
416 _FDT((fdt_property_string(fdt, "system-id", buf)));
417 }
418 g_free(buf);
419
420 off = fdt_add_subnode(fdt, 0, "chosen");
421 if (machine->kernel_cmdline) {
422 _FDT((fdt_setprop_string(fdt, off, "bootargs",
423 machine->kernel_cmdline)));
424 }
425
426 if (pnv->initrd_size) {
427 uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
428 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
429
430 _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
431 &start_prop, sizeof(start_prop))));
432 _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
433 &end_prop, sizeof(end_prop))));
434 }
435
436 /* Populate device tree for each chip */
437 for (i = 0; i < pnv->num_chips; i++) {
438 powernv_populate_chip(pnv->chips[i], fdt);
439 }
440
441 /* Populate ISA devices on chip 0 */
442 lpc_offset = pnv_chip_lpc_offset(pnv->chips[0], fdt);
443 powernv_populate_isa(pnv->isa_bus, fdt, lpc_offset);
444 return fdt;
445 }
446
447 static void ppc_powernv_reset(void)
448 {
449 MachineState *machine = MACHINE(qdev_get_machine());
450 void *fdt;
451
452 qemu_devices_reset();
453
454 fdt = powernv_create_fdt(machine);
455
456 /* Pack resulting tree */
457 _FDT((fdt_pack(fdt)));
458
459 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
460 }
461
462 static ISABus *pnv_isa_create(PnvChip *chip)
463 {
464 PnvLpcController *lpc = &chip->lpc;
465 ISABus *isa_bus;
466 qemu_irq *irqs;
467 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
468
469 /* let isa_bus_new() create its own bridge on SysBus otherwise
470 * devices speficied on the command line won't find the bus and
471 * will fail to create.
472 */
473 isa_bus = isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io,
474 &error_fatal);
475
476 irqs = pnv_lpc_isa_irq_create(lpc, pcc->chip_type, ISA_NUM_IRQS);
477
478 isa_bus_irqs(isa_bus, irqs);
479 return isa_bus;
480 }
481
482 static void ppc_powernv_init(MachineState *machine)
483 {
484 PnvMachineState *pnv = POWERNV_MACHINE(machine);
485 MemoryRegion *ram;
486 char *fw_filename;
487 long fw_size;
488 int i;
489 char *chip_typename;
490
491 /* allocate RAM */
492 if (machine->ram_size < (1 * G_BYTE)) {
493 error_report("Warning: skiboot may not work with < 1GB of RAM");
494 }
495
496 ram = g_new(MemoryRegion, 1);
497 memory_region_allocate_system_memory(ram, NULL, "ppc_powernv.ram",
498 machine->ram_size);
499 memory_region_add_subregion(get_system_memory(), 0, ram);
500
501 /* load skiboot firmware */
502 if (bios_name == NULL) {
503 bios_name = FW_FILE_NAME;
504 }
505
506 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
507
508 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE);
509 if (fw_size < 0) {
510 error_report("Could not load OPAL '%s'", fw_filename);
511 exit(1);
512 }
513 g_free(fw_filename);
514
515 /* load kernel */
516 if (machine->kernel_filename) {
517 long kernel_size;
518
519 kernel_size = load_image_targphys(machine->kernel_filename,
520 KERNEL_LOAD_ADDR, 0x2000000);
521 if (kernel_size < 0) {
522 error_report("Could not load kernel '%s'",
523 machine->kernel_filename);
524 exit(1);
525 }
526 }
527
528 /* load initrd */
529 if (machine->initrd_filename) {
530 pnv->initrd_base = INITRD_LOAD_ADDR;
531 pnv->initrd_size = load_image_targphys(machine->initrd_filename,
532 pnv->initrd_base, 0x10000000); /* 128MB max */
533 if (pnv->initrd_size < 0) {
534 error_report("Could not load initial ram disk '%s'",
535 machine->initrd_filename);
536 exit(1);
537 }
538 }
539
540 /* We need some cpu model to instantiate the PnvChip class */
541 if (machine->cpu_model == NULL) {
542 machine->cpu_model = "POWER8";
543 }
544
545 /* Create the processor chips */
546 chip_typename = g_strdup_printf(TYPE_PNV_CHIP "-%s", machine->cpu_model);
547 if (!object_class_by_name(chip_typename)) {
548 error_report("qemu: invalid CPU model '%s' for %s machine",
549 machine->cpu_model, MACHINE_GET_CLASS(machine)->name);
550 exit(1);
551 }
552
553 pnv->chips = g_new0(PnvChip *, pnv->num_chips);
554 for (i = 0; i < pnv->num_chips; i++) {
555 char chip_name[32];
556 Object *chip = object_new(chip_typename);
557
558 pnv->chips[i] = PNV_CHIP(chip);
559
560 /* TODO: put all the memory in one node on chip 0 until we find a
561 * way to specify different ranges for each chip
562 */
563 if (i == 0) {
564 object_property_set_int(chip, machine->ram_size, "ram-size",
565 &error_fatal);
566 }
567
568 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i));
569 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal);
570 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id",
571 &error_fatal);
572 object_property_set_int(chip, smp_cores, "nr-cores", &error_fatal);
573 object_property_set_bool(chip, true, "realized", &error_fatal);
574 }
575 g_free(chip_typename);
576
577 /* Instantiate ISA bus on chip 0 */
578 pnv->isa_bus = pnv_isa_create(pnv->chips[0]);
579
580 /* Create serial port */
581 serial_hds_isa_init(pnv->isa_bus, 0, MAX_SERIAL_PORTS);
582
583 /* Create an RTC ISA device too */
584 rtc_init(pnv->isa_bus, 2000, NULL);
585 }
586
587 /*
588 * 0:21 Reserved - Read as zeros
589 * 22:24 Chip ID
590 * 25:28 Core number
591 * 29:31 Thread ID
592 */
593 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
594 {
595 return (chip->chip_id << 7) | (core_id << 3);
596 }
597
598 /*
599 * 0:48 Reserved - Read as zeroes
600 * 49:52 Node ID
601 * 53:55 Chip ID
602 * 56 Reserved - Read as zero
603 * 57:61 Core number
604 * 62:63 Thread ID
605 *
606 * We only care about the lower bits. uint32_t is fine for the moment.
607 */
608 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
609 {
610 return (chip->chip_id << 8) | (core_id << 2);
611 }
612
613 /* Allowed core identifiers on a POWER8 Processor Chip :
614 *
615 * <EX0 reserved>
616 * EX1 - Venice only
617 * EX2 - Venice only
618 * EX3 - Venice only
619 * EX4
620 * EX5
621 * EX6
622 * <EX7,8 reserved> <reserved>
623 * EX9 - Venice only
624 * EX10 - Venice only
625 * EX11 - Venice only
626 * EX12
627 * EX13
628 * EX14
629 * <EX15 reserved>
630 */
631 #define POWER8E_CORE_MASK (0x7070ull)
632 #define POWER8_CORE_MASK (0x7e7eull)
633
634 /*
635 * POWER9 has 24 cores, ids starting at 0x20
636 */
637 #define POWER9_CORE_MASK (0xffffff00000000ull)
638
639 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
640 {
641 DeviceClass *dc = DEVICE_CLASS(klass);
642 PnvChipClass *k = PNV_CHIP_CLASS(klass);
643
644 k->cpu_model = "POWER8E";
645 k->chip_type = PNV_CHIP_POWER8E;
646 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
647 k->cores_mask = POWER8E_CORE_MASK;
648 k->core_pir = pnv_chip_core_pir_p8;
649 k->xscom_base = 0x003fc0000000000ull;
650 k->xscom_core_base = 0x10000000ull;
651 dc->desc = "PowerNV Chip POWER8E";
652 }
653
654 static const TypeInfo pnv_chip_power8e_info = {
655 .name = TYPE_PNV_CHIP_POWER8E,
656 .parent = TYPE_PNV_CHIP,
657 .instance_size = sizeof(PnvChip),
658 .class_init = pnv_chip_power8e_class_init,
659 };
660
661 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
662 {
663 DeviceClass *dc = DEVICE_CLASS(klass);
664 PnvChipClass *k = PNV_CHIP_CLASS(klass);
665
666 k->cpu_model = "POWER8";
667 k->chip_type = PNV_CHIP_POWER8;
668 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
669 k->cores_mask = POWER8_CORE_MASK;
670 k->core_pir = pnv_chip_core_pir_p8;
671 k->xscom_base = 0x003fc0000000000ull;
672 k->xscom_core_base = 0x10000000ull;
673 dc->desc = "PowerNV Chip POWER8";
674 }
675
676 static const TypeInfo pnv_chip_power8_info = {
677 .name = TYPE_PNV_CHIP_POWER8,
678 .parent = TYPE_PNV_CHIP,
679 .instance_size = sizeof(PnvChip),
680 .class_init = pnv_chip_power8_class_init,
681 };
682
683 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
684 {
685 DeviceClass *dc = DEVICE_CLASS(klass);
686 PnvChipClass *k = PNV_CHIP_CLASS(klass);
687
688 k->cpu_model = "POWER8NVL";
689 k->chip_type = PNV_CHIP_POWER8NVL;
690 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
691 k->cores_mask = POWER8_CORE_MASK;
692 k->core_pir = pnv_chip_core_pir_p8;
693 k->xscom_base = 0x003fc0000000000ull;
694 k->xscom_core_base = 0x10000000ull;
695 dc->desc = "PowerNV Chip POWER8NVL";
696 }
697
698 static const TypeInfo pnv_chip_power8nvl_info = {
699 .name = TYPE_PNV_CHIP_POWER8NVL,
700 .parent = TYPE_PNV_CHIP,
701 .instance_size = sizeof(PnvChip),
702 .class_init = pnv_chip_power8nvl_class_init,
703 };
704
705 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
706 {
707 DeviceClass *dc = DEVICE_CLASS(klass);
708 PnvChipClass *k = PNV_CHIP_CLASS(klass);
709
710 k->cpu_model = "POWER9";
711 k->chip_type = PNV_CHIP_POWER9;
712 k->chip_cfam_id = 0x100d104980000000ull; /* P9 Nimbus DD1.0 */
713 k->cores_mask = POWER9_CORE_MASK;
714 k->core_pir = pnv_chip_core_pir_p9;
715 k->xscom_base = 0x00603fc00000000ull;
716 k->xscom_core_base = 0x0ull;
717 dc->desc = "PowerNV Chip POWER9";
718 }
719
720 static const TypeInfo pnv_chip_power9_info = {
721 .name = TYPE_PNV_CHIP_POWER9,
722 .parent = TYPE_PNV_CHIP,
723 .instance_size = sizeof(PnvChip),
724 .class_init = pnv_chip_power9_class_init,
725 };
726
727 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
728 {
729 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
730 int cores_max;
731
732 /*
733 * No custom mask for this chip, let's use the default one from *
734 * the chip class
735 */
736 if (!chip->cores_mask) {
737 chip->cores_mask = pcc->cores_mask;
738 }
739
740 /* filter alien core ids ! some are reserved */
741 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
742 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
743 chip->cores_mask);
744 return;
745 }
746 chip->cores_mask &= pcc->cores_mask;
747
748 /* now that we have a sane layout, let check the number of cores */
749 cores_max = ctpop64(chip->cores_mask);
750 if (chip->nr_cores > cores_max) {
751 error_setg(errp, "warning: too many cores for chip ! Limit is %d",
752 cores_max);
753 return;
754 }
755 }
756
757 static void pnv_chip_init(Object *obj)
758 {
759 PnvChip *chip = PNV_CHIP(obj);
760 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
761
762 chip->xscom_base = pcc->xscom_base;
763
764 object_initialize(&chip->lpc, sizeof(chip->lpc), TYPE_PNV_LPC);
765 object_property_add_child(obj, "lpc", OBJECT(&chip->lpc), NULL);
766
767 object_initialize(&chip->psi, sizeof(chip->psi), TYPE_PNV_PSI);
768 object_property_add_child(obj, "psi", OBJECT(&chip->psi), NULL);
769 object_property_add_const_link(OBJECT(&chip->psi), "xics",
770 OBJECT(qdev_get_machine()), &error_abort);
771
772 object_initialize(&chip->occ, sizeof(chip->occ), TYPE_PNV_OCC);
773 object_property_add_child(obj, "occ", OBJECT(&chip->occ), NULL);
774 object_property_add_const_link(OBJECT(&chip->occ), "psi",
775 OBJECT(&chip->psi), &error_abort);
776
777 /* The LPC controller needs PSI to generate interrupts */
778 object_property_add_const_link(OBJECT(&chip->lpc), "psi",
779 OBJECT(&chip->psi), &error_abort);
780 }
781
782 static void pnv_chip_icp_realize(PnvChip *chip, Error **errp)
783 {
784 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
785 char *typename = pnv_core_typename(pcc->cpu_model);
786 size_t typesize = object_type_get_instance_size(typename);
787 int i, j;
788 char *name;
789 XICSFabric *xi = XICS_FABRIC(qdev_get_machine());
790
791 name = g_strdup_printf("icp-%x", chip->chip_id);
792 memory_region_init(&chip->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
793 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip->icp_mmio);
794 g_free(name);
795
796 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip));
797
798 /* Map the ICP registers for each thread */
799 for (i = 0; i < chip->nr_cores; i++) {
800 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
801 int core_hwid = CPU_CORE(pnv_core)->core_id;
802
803 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
804 uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
805 PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir));
806
807 memory_region_add_subregion(&chip->icp_mmio, pir << 12, &icp->mmio);
808 }
809 }
810
811 g_free(typename);
812 }
813
814 static void pnv_chip_realize(DeviceState *dev, Error **errp)
815 {
816 PnvChip *chip = PNV_CHIP(dev);
817 Error *error = NULL;
818 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
819 char *typename = pnv_core_typename(pcc->cpu_model);
820 size_t typesize = object_type_get_instance_size(typename);
821 int i, core_hwid;
822
823 if (!object_class_by_name(typename)) {
824 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
825 return;
826 }
827
828 /* XSCOM bridge */
829 pnv_xscom_realize(chip, &error);
830 if (error) {
831 error_propagate(errp, error);
832 return;
833 }
834 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
835
836 /* Cores */
837 pnv_chip_core_sanitize(chip, &error);
838 if (error) {
839 error_propagate(errp, error);
840 return;
841 }
842
843 chip->cores = g_malloc0(typesize * chip->nr_cores);
844
845 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
846 && (i < chip->nr_cores); core_hwid++) {
847 char core_name[32];
848 void *pnv_core = chip->cores + i * typesize;
849
850 if (!(chip->cores_mask & (1ull << core_hwid))) {
851 continue;
852 }
853
854 object_initialize(pnv_core, typesize, typename);
855 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
856 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core),
857 &error_fatal);
858 object_property_set_int(OBJECT(pnv_core), smp_threads, "nr-threads",
859 &error_fatal);
860 object_property_set_int(OBJECT(pnv_core), core_hwid,
861 CPU_CORE_PROP_CORE_ID, &error_fatal);
862 object_property_set_int(OBJECT(pnv_core),
863 pcc->core_pir(chip, core_hwid),
864 "pir", &error_fatal);
865 object_property_add_const_link(OBJECT(pnv_core), "xics",
866 qdev_get_machine(), &error_fatal);
867 object_property_set_bool(OBJECT(pnv_core), true, "realized",
868 &error_fatal);
869 object_unref(OBJECT(pnv_core));
870
871 /* Each core has an XSCOM MMIO region */
872 pnv_xscom_add_subregion(chip,
873 PNV_XSCOM_EX_CORE_BASE(pcc->xscom_core_base,
874 core_hwid),
875 &PNV_CORE(pnv_core)->xscom_regs);
876 i++;
877 }
878 g_free(typename);
879
880 /* Create LPC controller */
881 object_property_set_bool(OBJECT(&chip->lpc), true, "realized",
882 &error_fatal);
883 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip->lpc.xscom_regs);
884
885 /* Interrupt Management Area. This is the memory region holding
886 * all the Interrupt Control Presenter (ICP) registers */
887 pnv_chip_icp_realize(chip, &error);
888 if (error) {
889 error_propagate(errp, error);
890 return;
891 }
892
893 /* Processor Service Interface (PSI) Host Bridge */
894 object_property_set_int(OBJECT(&chip->psi), PNV_PSIHB_BASE(chip),
895 "bar", &error_fatal);
896 object_property_set_bool(OBJECT(&chip->psi), true, "realized", &error);
897 if (error) {
898 error_propagate(errp, error);
899 return;
900 }
901 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, &chip->psi.xscom_regs);
902
903 /* Create the simplified OCC model */
904 object_property_set_bool(OBJECT(&chip->occ), true, "realized", &error);
905 if (error) {
906 error_propagate(errp, error);
907 return;
908 }
909 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip->occ.xscom_regs);
910 }
911
912 static Property pnv_chip_properties[] = {
913 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
914 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
915 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
916 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
917 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
918 DEFINE_PROP_END_OF_LIST(),
919 };
920
921 static void pnv_chip_class_init(ObjectClass *klass, void *data)
922 {
923 DeviceClass *dc = DEVICE_CLASS(klass);
924
925 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
926 dc->realize = pnv_chip_realize;
927 dc->props = pnv_chip_properties;
928 dc->desc = "PowerNV Chip";
929 }
930
931 static const TypeInfo pnv_chip_info = {
932 .name = TYPE_PNV_CHIP,
933 .parent = TYPE_SYS_BUS_DEVICE,
934 .class_init = pnv_chip_class_init,
935 .instance_init = pnv_chip_init,
936 .class_size = sizeof(PnvChipClass),
937 .abstract = true,
938 };
939
940 static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
941 {
942 PnvMachineState *pnv = POWERNV_MACHINE(xi);
943 int i;
944
945 for (i = 0; i < pnv->num_chips; i++) {
946 if (ics_valid_irq(&pnv->chips[i]->psi.ics, irq)) {
947 return &pnv->chips[i]->psi.ics;
948 }
949 }
950 return NULL;
951 }
952
953 static void pnv_ics_resend(XICSFabric *xi)
954 {
955 PnvMachineState *pnv = POWERNV_MACHINE(xi);
956 int i;
957
958 for (i = 0; i < pnv->num_chips; i++) {
959 ics_resend(&pnv->chips[i]->psi.ics);
960 }
961 }
962
963 static PowerPCCPU *ppc_get_vcpu_by_pir(int pir)
964 {
965 CPUState *cs;
966
967 CPU_FOREACH(cs) {
968 PowerPCCPU *cpu = POWERPC_CPU(cs);
969 CPUPPCState *env = &cpu->env;
970
971 if (env->spr_cb[SPR_PIR].default_value == pir) {
972 return cpu;
973 }
974 }
975
976 return NULL;
977 }
978
979 static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
980 {
981 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
982
983 return cpu ? ICP(cpu->intc) : NULL;
984 }
985
986 static void pnv_pic_print_info(InterruptStatsProvider *obj,
987 Monitor *mon)
988 {
989 PnvMachineState *pnv = POWERNV_MACHINE(obj);
990 int i;
991 CPUState *cs;
992
993 CPU_FOREACH(cs) {
994 PowerPCCPU *cpu = POWERPC_CPU(cs);
995
996 icp_pic_print_info(ICP(cpu->intc), mon);
997 }
998
999 for (i = 0; i < pnv->num_chips; i++) {
1000 ics_pic_print_info(&pnv->chips[i]->psi.ics, mon);
1001 }
1002 }
1003
1004 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name,
1005 void *opaque, Error **errp)
1006 {
1007 visit_type_uint32(v, name, &POWERNV_MACHINE(obj)->num_chips, errp);
1008 }
1009
1010 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name,
1011 void *opaque, Error **errp)
1012 {
1013 PnvMachineState *pnv = POWERNV_MACHINE(obj);
1014 uint32_t num_chips;
1015 Error *local_err = NULL;
1016
1017 visit_type_uint32(v, name, &num_chips, &local_err);
1018 if (local_err) {
1019 error_propagate(errp, local_err);
1020 return;
1021 }
1022
1023 /*
1024 * TODO: should we decide on how many chips we can create based
1025 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
1026 */
1027 if (!is_power_of_2(num_chips) || num_chips > 4) {
1028 error_setg(errp, "invalid number of chips: '%d'", num_chips);
1029 return;
1030 }
1031
1032 pnv->num_chips = num_chips;
1033 }
1034
1035 static void powernv_machine_initfn(Object *obj)
1036 {
1037 PnvMachineState *pnv = POWERNV_MACHINE(obj);
1038 pnv->num_chips = 1;
1039 }
1040
1041 static void powernv_machine_class_props_init(ObjectClass *oc)
1042 {
1043 object_class_property_add(oc, "num-chips", "uint32_t",
1044 pnv_get_num_chips, pnv_set_num_chips,
1045 NULL, NULL, NULL);
1046 object_class_property_set_description(oc, "num-chips",
1047 "Specifies the number of processor chips",
1048 NULL);
1049 }
1050
1051 static void powernv_machine_class_init(ObjectClass *oc, void *data)
1052 {
1053 MachineClass *mc = MACHINE_CLASS(oc);
1054 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
1055 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
1056
1057 mc->desc = "IBM PowerNV (Non-Virtualized)";
1058 mc->init = ppc_powernv_init;
1059 mc->reset = ppc_powernv_reset;
1060 mc->max_cpus = MAX_CPUS;
1061 mc->block_default_type = IF_IDE; /* Pnv provides a AHCI device for
1062 * storage */
1063 mc->no_parallel = 1;
1064 mc->default_boot_order = NULL;
1065 mc->default_ram_size = 1 * G_BYTE;
1066 xic->icp_get = pnv_icp_get;
1067 xic->ics_get = pnv_ics_get;
1068 xic->ics_resend = pnv_ics_resend;
1069 ispc->print_info = pnv_pic_print_info;
1070
1071 powernv_machine_class_props_init(oc);
1072 }
1073
1074 static const TypeInfo powernv_machine_info = {
1075 .name = TYPE_POWERNV_MACHINE,
1076 .parent = TYPE_MACHINE,
1077 .instance_size = sizeof(PnvMachineState),
1078 .instance_init = powernv_machine_initfn,
1079 .class_init = powernv_machine_class_init,
1080 .interfaces = (InterfaceInfo[]) {
1081 { TYPE_XICS_FABRIC },
1082 { TYPE_INTERRUPT_STATS_PROVIDER },
1083 { },
1084 },
1085 };
1086
1087 static void powernv_machine_register_types(void)
1088 {
1089 type_register_static(&powernv_machine_info);
1090 type_register_static(&pnv_chip_info);
1091 type_register_static(&pnv_chip_power8e_info);
1092 type_register_static(&pnv_chip_power8_info);
1093 type_register_static(&pnv_chip_power8nvl_info);
1094 type_register_static(&pnv_chip_power9_info);
1095 }
1096
1097 type_init(powernv_machine_register_types)