ppc/pnv: extend the machine with a InterruptStatsProvider interface
[qemu.git] / hw / ppc / pnv.c
1 /*
2 * QEMU PowerPC PowerNV machine model
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "sysemu/sysemu.h"
23 #include "sysemu/numa.h"
24 #include "sysemu/cpus.h"
25 #include "hw/hw.h"
26 #include "target/ppc/cpu.h"
27 #include "qemu/log.h"
28 #include "hw/ppc/fdt.h"
29 #include "hw/ppc/ppc.h"
30 #include "hw/ppc/pnv.h"
31 #include "hw/ppc/pnv_core.h"
32 #include "hw/loader.h"
33 #include "exec/address-spaces.h"
34 #include "qemu/cutils.h"
35 #include "qapi/visitor.h"
36 #include "monitor/monitor.h"
37 #include "hw/intc/intc.h"
38
39 #include "hw/ppc/xics.h"
40 #include "hw/ppc/pnv_xscom.h"
41
42 #include "hw/isa/isa.h"
43 #include "hw/char/serial.h"
44 #include "hw/timer/mc146818rtc.h"
45
46 #include <libfdt.h>
47
48 #define FDT_MAX_SIZE 0x00100000
49
50 #define FW_FILE_NAME "skiboot.lid"
51 #define FW_LOAD_ADDR 0x0
52 #define FW_MAX_SIZE 0x00400000
53
54 #define KERNEL_LOAD_ADDR 0x20000000
55 #define INITRD_LOAD_ADDR 0x40000000
56
57 /*
58 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
59 * 4 * 4 sockets * 12 cores * 8 threads = 1536
60 * Let's make it 2^11
61 */
62 #define MAX_CPUS 2048
63
64 /*
65 * Memory nodes are created by hostboot, one for each range of memory
66 * that has a different "affinity". In practice, it means one range
67 * per chip.
68 */
69 static void powernv_populate_memory_node(void *fdt, int chip_id, hwaddr start,
70 hwaddr size)
71 {
72 char *mem_name;
73 uint64_t mem_reg_property[2];
74 int off;
75
76 mem_reg_property[0] = cpu_to_be64(start);
77 mem_reg_property[1] = cpu_to_be64(size);
78
79 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
80 off = fdt_add_subnode(fdt, 0, mem_name);
81 g_free(mem_name);
82
83 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
84 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
85 sizeof(mem_reg_property))));
86 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
87 }
88
89 static int get_cpus_node(void *fdt)
90 {
91 int cpus_offset = fdt_path_offset(fdt, "/cpus");
92
93 if (cpus_offset < 0) {
94 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"),
95 "cpus");
96 if (cpus_offset) {
97 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
98 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
99 }
100 }
101 _FDT(cpus_offset);
102 return cpus_offset;
103 }
104
105 /*
106 * The PowerNV cores (and threads) need to use real HW ids and not an
107 * incremental index like it has been done on other platforms. This HW
108 * id is stored in the CPU PIR, it is used to create cpu nodes in the
109 * device tree, used in XSCOM to address cores and in interrupt
110 * servers.
111 */
112 static void powernv_create_core_node(PnvChip *chip, PnvCore *pc, void *fdt)
113 {
114 CPUState *cs = CPU(DEVICE(pc->threads));
115 DeviceClass *dc = DEVICE_GET_CLASS(cs);
116 PowerPCCPU *cpu = POWERPC_CPU(cs);
117 int smt_threads = CPU_CORE(pc)->nr_threads;
118 CPUPPCState *env = &cpu->env;
119 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
120 uint32_t servers_prop[smt_threads];
121 int i;
122 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
123 0xffffffff, 0xffffffff};
124 uint32_t tbfreq = PNV_TIMEBASE_FREQ;
125 uint32_t cpufreq = 1000000000;
126 uint32_t page_sizes_prop[64];
127 size_t page_sizes_prop_size;
128 const uint8_t pa_features[] = { 24, 0,
129 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
130 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
131 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
132 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
133 int offset;
134 char *nodename;
135 int cpus_offset = get_cpus_node(fdt);
136
137 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
138 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
139 _FDT(offset);
140 g_free(nodename);
141
142 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
143
144 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
145 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
146 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
147
148 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
149 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
150 env->dcache_line_size)));
151 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
152 env->dcache_line_size)));
153 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
154 env->icache_line_size)));
155 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
156 env->icache_line_size)));
157
158 if (pcc->l1_dcache_size) {
159 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
160 pcc->l1_dcache_size)));
161 } else {
162 error_report("Warning: Unknown L1 dcache size for cpu");
163 }
164 if (pcc->l1_icache_size) {
165 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
166 pcc->l1_icache_size)));
167 } else {
168 error_report("Warning: Unknown L1 icache size for cpu");
169 }
170
171 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
172 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
173 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr)));
174 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
175 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
176
177 if (env->spr_cb[SPR_PURR].oea_read) {
178 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
179 }
180
181 if (env->mmu_model & POWERPC_MMU_1TSEG) {
182 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
183 segs, sizeof(segs))));
184 }
185
186 /* Advertise VMX/VSX (vector extensions) if available
187 * 0 / no property == no vector extensions
188 * 1 == VMX / Altivec available
189 * 2 == VSX available */
190 if (env->insns_flags & PPC_ALTIVEC) {
191 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
192
193 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
194 }
195
196 /* Advertise DFP (Decimal Floating Point) if available
197 * 0 / no property == no DFP
198 * 1 == DFP available */
199 if (env->insns_flags2 & PPC2_DFP) {
200 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
201 }
202
203 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop,
204 sizeof(page_sizes_prop));
205 if (page_sizes_prop_size) {
206 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
207 page_sizes_prop, page_sizes_prop_size)));
208 }
209
210 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
211 pa_features, sizeof(pa_features))));
212
213 /* Build interrupt servers properties */
214 for (i = 0; i < smt_threads; i++) {
215 servers_prop[i] = cpu_to_be32(pc->pir + i);
216 }
217 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
218 servers_prop, sizeof(servers_prop))));
219 }
220
221 static void powernv_populate_chip(PnvChip *chip, void *fdt)
222 {
223 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
224 char *typename = pnv_core_typename(pcc->cpu_model);
225 size_t typesize = object_type_get_instance_size(typename);
226 int i;
227
228 pnv_xscom_populate(chip, fdt, 0);
229
230 for (i = 0; i < chip->nr_cores; i++) {
231 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
232
233 powernv_create_core_node(chip, pnv_core, fdt);
234 }
235
236 if (chip->ram_size) {
237 powernv_populate_memory_node(fdt, chip->chip_id, chip->ram_start,
238 chip->ram_size);
239 }
240 g_free(typename);
241 }
242
243 static void *powernv_create_fdt(MachineState *machine)
244 {
245 const char plat_compat[] = "qemu,powernv\0ibm,powernv";
246 PnvMachineState *pnv = POWERNV_MACHINE(machine);
247 void *fdt;
248 char *buf;
249 int off;
250 int i;
251
252 fdt = g_malloc0(FDT_MAX_SIZE);
253 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
254
255 /* Root node */
256 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
257 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
258 _FDT((fdt_setprop_string(fdt, 0, "model",
259 "IBM PowerNV (emulated by qemu)")));
260 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat,
261 sizeof(plat_compat))));
262
263 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
264 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
265 if (qemu_uuid_set) {
266 _FDT((fdt_property_string(fdt, "system-id", buf)));
267 }
268 g_free(buf);
269
270 off = fdt_add_subnode(fdt, 0, "chosen");
271 if (machine->kernel_cmdline) {
272 _FDT((fdt_setprop_string(fdt, off, "bootargs",
273 machine->kernel_cmdline)));
274 }
275
276 if (pnv->initrd_size) {
277 uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
278 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
279
280 _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
281 &start_prop, sizeof(start_prop))));
282 _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
283 &end_prop, sizeof(end_prop))));
284 }
285
286 /* Populate device tree for each chip */
287 for (i = 0; i < pnv->num_chips; i++) {
288 powernv_populate_chip(pnv->chips[i], fdt);
289 }
290 return fdt;
291 }
292
293 static void ppc_powernv_reset(void)
294 {
295 MachineState *machine = MACHINE(qdev_get_machine());
296 void *fdt;
297
298 qemu_devices_reset();
299
300 fdt = powernv_create_fdt(machine);
301
302 /* Pack resulting tree */
303 _FDT((fdt_pack(fdt)));
304
305 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
306 }
307
308 /* If we don't use the built-in LPC interrupt deserializer, we need
309 * to provide a set of qirqs for the ISA bus or things will go bad.
310 *
311 * Most machines using pre-Naples chips (without said deserializer)
312 * have a CPLD that will collect the SerIRQ and shoot them as a
313 * single level interrupt to the P8 chip. So let's setup a hook
314 * for doing just that.
315 *
316 * Note: The actual interrupt input isn't emulated yet, this will
317 * come with the PSI bridge model.
318 */
319 static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level)
320 {
321 /* We don't yet emulate the PSI bridge which provides the external
322 * interrupt, so just drop interrupts on the floor
323 */
324 }
325
326 static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level)
327 {
328 /* XXX TODO */
329 }
330
331 static ISABus *pnv_isa_create(PnvChip *chip)
332 {
333 PnvLpcController *lpc = &chip->lpc;
334 ISABus *isa_bus;
335 qemu_irq *irqs;
336 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
337
338 /* let isa_bus_new() create its own bridge on SysBus otherwise
339 * devices speficied on the command line won't find the bus and
340 * will fail to create.
341 */
342 isa_bus = isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io,
343 &error_fatal);
344
345 /* Not all variants have a working serial irq decoder. If not,
346 * handling of LPC interrupts becomes a platform issue (some
347 * platforms have a CPLD to do it).
348 */
349 if (pcc->chip_type == PNV_CHIP_POWER8NVL) {
350 irqs = qemu_allocate_irqs(pnv_lpc_isa_irq_handler, chip, ISA_NUM_IRQS);
351 } else {
352 irqs = qemu_allocate_irqs(pnv_lpc_isa_irq_handler_cpld, chip,
353 ISA_NUM_IRQS);
354 }
355
356 isa_bus_irqs(isa_bus, irqs);
357 return isa_bus;
358 }
359
360 static void ppc_powernv_init(MachineState *machine)
361 {
362 PnvMachineState *pnv = POWERNV_MACHINE(machine);
363 MemoryRegion *ram;
364 char *fw_filename;
365 long fw_size;
366 int i;
367 char *chip_typename;
368
369 /* allocate RAM */
370 if (machine->ram_size < (1 * G_BYTE)) {
371 error_report("Warning: skiboot may not work with < 1GB of RAM");
372 }
373
374 ram = g_new(MemoryRegion, 1);
375 memory_region_allocate_system_memory(ram, NULL, "ppc_powernv.ram",
376 machine->ram_size);
377 memory_region_add_subregion(get_system_memory(), 0, ram);
378
379 /* load skiboot firmware */
380 if (bios_name == NULL) {
381 bios_name = FW_FILE_NAME;
382 }
383
384 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
385
386 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE);
387 if (fw_size < 0) {
388 error_report("Could not load OPAL '%s'", fw_filename);
389 exit(1);
390 }
391 g_free(fw_filename);
392
393 /* load kernel */
394 if (machine->kernel_filename) {
395 long kernel_size;
396
397 kernel_size = load_image_targphys(machine->kernel_filename,
398 KERNEL_LOAD_ADDR, 0x2000000);
399 if (kernel_size < 0) {
400 error_report("Could not load kernel '%s'",
401 machine->kernel_filename);
402 exit(1);
403 }
404 }
405
406 /* load initrd */
407 if (machine->initrd_filename) {
408 pnv->initrd_base = INITRD_LOAD_ADDR;
409 pnv->initrd_size = load_image_targphys(machine->initrd_filename,
410 pnv->initrd_base, 0x10000000); /* 128MB max */
411 if (pnv->initrd_size < 0) {
412 error_report("Could not load initial ram disk '%s'",
413 machine->initrd_filename);
414 exit(1);
415 }
416 }
417
418 /* We need some cpu model to instantiate the PnvChip class */
419 if (machine->cpu_model == NULL) {
420 machine->cpu_model = "POWER8";
421 }
422
423 /* Create the processor chips */
424 chip_typename = g_strdup_printf(TYPE_PNV_CHIP "-%s", machine->cpu_model);
425 if (!object_class_by_name(chip_typename)) {
426 error_report("qemu: invalid CPU model '%s' for %s machine",
427 machine->cpu_model, MACHINE_GET_CLASS(machine)->name);
428 exit(1);
429 }
430
431 pnv->chips = g_new0(PnvChip *, pnv->num_chips);
432 for (i = 0; i < pnv->num_chips; i++) {
433 char chip_name[32];
434 Object *chip = object_new(chip_typename);
435
436 pnv->chips[i] = PNV_CHIP(chip);
437
438 /* TODO: put all the memory in one node on chip 0 until we find a
439 * way to specify different ranges for each chip
440 */
441 if (i == 0) {
442 object_property_set_int(chip, machine->ram_size, "ram-size",
443 &error_fatal);
444 }
445
446 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i));
447 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal);
448 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id",
449 &error_fatal);
450 object_property_set_int(chip, smp_cores, "nr-cores", &error_fatal);
451 object_property_set_bool(chip, true, "realized", &error_fatal);
452 }
453 g_free(chip_typename);
454
455 /* Instantiate ISA bus on chip 0 */
456 pnv->isa_bus = pnv_isa_create(pnv->chips[0]);
457
458 /* Create serial port */
459 serial_hds_isa_init(pnv->isa_bus, 0, MAX_SERIAL_PORTS);
460
461 /* Create an RTC ISA device too */
462 rtc_init(pnv->isa_bus, 2000, NULL);
463 }
464
465 /*
466 * 0:21 Reserved - Read as zeros
467 * 22:24 Chip ID
468 * 25:28 Core number
469 * 29:31 Thread ID
470 */
471 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
472 {
473 return (chip->chip_id << 7) | (core_id << 3);
474 }
475
476 /*
477 * 0:48 Reserved - Read as zeroes
478 * 49:52 Node ID
479 * 53:55 Chip ID
480 * 56 Reserved - Read as zero
481 * 57:61 Core number
482 * 62:63 Thread ID
483 *
484 * We only care about the lower bits. uint32_t is fine for the moment.
485 */
486 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
487 {
488 return (chip->chip_id << 8) | (core_id << 2);
489 }
490
491 /* Allowed core identifiers on a POWER8 Processor Chip :
492 *
493 * <EX0 reserved>
494 * EX1 - Venice only
495 * EX2 - Venice only
496 * EX3 - Venice only
497 * EX4
498 * EX5
499 * EX6
500 * <EX7,8 reserved> <reserved>
501 * EX9 - Venice only
502 * EX10 - Venice only
503 * EX11 - Venice only
504 * EX12
505 * EX13
506 * EX14
507 * <EX15 reserved>
508 */
509 #define POWER8E_CORE_MASK (0x7070ull)
510 #define POWER8_CORE_MASK (0x7e7eull)
511
512 /*
513 * POWER9 has 24 cores, ids starting at 0x20
514 */
515 #define POWER9_CORE_MASK (0xffffff00000000ull)
516
517 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
518 {
519 DeviceClass *dc = DEVICE_CLASS(klass);
520 PnvChipClass *k = PNV_CHIP_CLASS(klass);
521
522 k->cpu_model = "POWER8E";
523 k->chip_type = PNV_CHIP_POWER8E;
524 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
525 k->cores_mask = POWER8E_CORE_MASK;
526 k->core_pir = pnv_chip_core_pir_p8;
527 k->xscom_base = 0x003fc0000000000ull;
528 k->xscom_core_base = 0x10000000ull;
529 dc->desc = "PowerNV Chip POWER8E";
530 }
531
532 static const TypeInfo pnv_chip_power8e_info = {
533 .name = TYPE_PNV_CHIP_POWER8E,
534 .parent = TYPE_PNV_CHIP,
535 .instance_size = sizeof(PnvChip),
536 .class_init = pnv_chip_power8e_class_init,
537 };
538
539 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
540 {
541 DeviceClass *dc = DEVICE_CLASS(klass);
542 PnvChipClass *k = PNV_CHIP_CLASS(klass);
543
544 k->cpu_model = "POWER8";
545 k->chip_type = PNV_CHIP_POWER8;
546 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
547 k->cores_mask = POWER8_CORE_MASK;
548 k->core_pir = pnv_chip_core_pir_p8;
549 k->xscom_base = 0x003fc0000000000ull;
550 k->xscom_core_base = 0x10000000ull;
551 dc->desc = "PowerNV Chip POWER8";
552 }
553
554 static const TypeInfo pnv_chip_power8_info = {
555 .name = TYPE_PNV_CHIP_POWER8,
556 .parent = TYPE_PNV_CHIP,
557 .instance_size = sizeof(PnvChip),
558 .class_init = pnv_chip_power8_class_init,
559 };
560
561 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
562 {
563 DeviceClass *dc = DEVICE_CLASS(klass);
564 PnvChipClass *k = PNV_CHIP_CLASS(klass);
565
566 k->cpu_model = "POWER8NVL";
567 k->chip_type = PNV_CHIP_POWER8NVL;
568 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
569 k->cores_mask = POWER8_CORE_MASK;
570 k->core_pir = pnv_chip_core_pir_p8;
571 k->xscom_base = 0x003fc0000000000ull;
572 k->xscom_core_base = 0x10000000ull;
573 dc->desc = "PowerNV Chip POWER8NVL";
574 }
575
576 static const TypeInfo pnv_chip_power8nvl_info = {
577 .name = TYPE_PNV_CHIP_POWER8NVL,
578 .parent = TYPE_PNV_CHIP,
579 .instance_size = sizeof(PnvChip),
580 .class_init = pnv_chip_power8nvl_class_init,
581 };
582
583 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
584 {
585 DeviceClass *dc = DEVICE_CLASS(klass);
586 PnvChipClass *k = PNV_CHIP_CLASS(klass);
587
588 k->cpu_model = "POWER9";
589 k->chip_type = PNV_CHIP_POWER9;
590 k->chip_cfam_id = 0x100d104980000000ull; /* P9 Nimbus DD1.0 */
591 k->cores_mask = POWER9_CORE_MASK;
592 k->core_pir = pnv_chip_core_pir_p9;
593 k->xscom_base = 0x00603fc00000000ull;
594 k->xscom_core_base = 0x0ull;
595 dc->desc = "PowerNV Chip POWER9";
596 }
597
598 static const TypeInfo pnv_chip_power9_info = {
599 .name = TYPE_PNV_CHIP_POWER9,
600 .parent = TYPE_PNV_CHIP,
601 .instance_size = sizeof(PnvChip),
602 .class_init = pnv_chip_power9_class_init,
603 };
604
605 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
606 {
607 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
608 int cores_max;
609
610 /*
611 * No custom mask for this chip, let's use the default one from *
612 * the chip class
613 */
614 if (!chip->cores_mask) {
615 chip->cores_mask = pcc->cores_mask;
616 }
617
618 /* filter alien core ids ! some are reserved */
619 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
620 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
621 chip->cores_mask);
622 return;
623 }
624 chip->cores_mask &= pcc->cores_mask;
625
626 /* now that we have a sane layout, let check the number of cores */
627 cores_max = ctpop64(chip->cores_mask);
628 if (chip->nr_cores > cores_max) {
629 error_setg(errp, "warning: too many cores for chip ! Limit is %d",
630 cores_max);
631 return;
632 }
633 }
634
635 static void pnv_chip_init(Object *obj)
636 {
637 PnvChip *chip = PNV_CHIP(obj);
638 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
639
640 chip->xscom_base = pcc->xscom_base;
641
642 object_initialize(&chip->lpc, sizeof(chip->lpc), TYPE_PNV_LPC);
643 object_property_add_child(obj, "lpc", OBJECT(&chip->lpc), NULL);
644 }
645
646 static void pnv_chip_realize(DeviceState *dev, Error **errp)
647 {
648 PnvChip *chip = PNV_CHIP(dev);
649 Error *error = NULL;
650 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
651 char *typename = pnv_core_typename(pcc->cpu_model);
652 size_t typesize = object_type_get_instance_size(typename);
653 int i, core_hwid;
654
655 if (!object_class_by_name(typename)) {
656 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
657 return;
658 }
659
660 /* XSCOM bridge */
661 pnv_xscom_realize(chip, &error);
662 if (error) {
663 error_propagate(errp, error);
664 return;
665 }
666 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
667
668 /* Cores */
669 pnv_chip_core_sanitize(chip, &error);
670 if (error) {
671 error_propagate(errp, error);
672 return;
673 }
674
675 chip->cores = g_malloc0(typesize * chip->nr_cores);
676
677 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
678 && (i < chip->nr_cores); core_hwid++) {
679 char core_name[32];
680 void *pnv_core = chip->cores + i * typesize;
681
682 if (!(chip->cores_mask & (1ull << core_hwid))) {
683 continue;
684 }
685
686 object_initialize(pnv_core, typesize, typename);
687 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
688 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core),
689 &error_fatal);
690 object_property_set_int(OBJECT(pnv_core), smp_threads, "nr-threads",
691 &error_fatal);
692 object_property_set_int(OBJECT(pnv_core), core_hwid,
693 CPU_CORE_PROP_CORE_ID, &error_fatal);
694 object_property_set_int(OBJECT(pnv_core),
695 pcc->core_pir(chip, core_hwid),
696 "pir", &error_fatal);
697 object_property_set_bool(OBJECT(pnv_core), true, "realized",
698 &error_fatal);
699 object_unref(OBJECT(pnv_core));
700
701 /* Each core has an XSCOM MMIO region */
702 pnv_xscom_add_subregion(chip,
703 PNV_XSCOM_EX_CORE_BASE(pcc->xscom_core_base,
704 core_hwid),
705 &PNV_CORE(pnv_core)->xscom_regs);
706 i++;
707 }
708 g_free(typename);
709
710 /* Create LPC controller */
711 object_property_set_bool(OBJECT(&chip->lpc), true, "realized",
712 &error_fatal);
713 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip->lpc.xscom_regs);
714 }
715
716 static Property pnv_chip_properties[] = {
717 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
718 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
719 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
720 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
721 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
722 DEFINE_PROP_END_OF_LIST(),
723 };
724
725 static void pnv_chip_class_init(ObjectClass *klass, void *data)
726 {
727 DeviceClass *dc = DEVICE_CLASS(klass);
728
729 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
730 dc->realize = pnv_chip_realize;
731 dc->props = pnv_chip_properties;
732 dc->desc = "PowerNV Chip";
733 }
734
735 static const TypeInfo pnv_chip_info = {
736 .name = TYPE_PNV_CHIP,
737 .parent = TYPE_SYS_BUS_DEVICE,
738 .class_init = pnv_chip_class_init,
739 .instance_init = pnv_chip_init,
740 .class_size = sizeof(PnvChipClass),
741 .abstract = true,
742 };
743
744 static PowerPCCPU *ppc_get_vcpu_by_pir(int pir)
745 {
746 CPUState *cs;
747
748 CPU_FOREACH(cs) {
749 PowerPCCPU *cpu = POWERPC_CPU(cs);
750 CPUPPCState *env = &cpu->env;
751
752 if (env->spr_cb[SPR_PIR].default_value == pir) {
753 return cpu;
754 }
755 }
756
757 return NULL;
758 }
759
760 static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
761 {
762 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
763
764 return cpu ? ICP(cpu->intc) : NULL;
765 }
766
767 static void pnv_pic_print_info(InterruptStatsProvider *obj,
768 Monitor *mon)
769 {
770 CPUState *cs;
771
772 CPU_FOREACH(cs) {
773 PowerPCCPU *cpu = POWERPC_CPU(cs);
774
775 icp_pic_print_info(ICP(cpu->intc), mon);
776 }
777 }
778
779 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name,
780 void *opaque, Error **errp)
781 {
782 visit_type_uint32(v, name, &POWERNV_MACHINE(obj)->num_chips, errp);
783 }
784
785 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name,
786 void *opaque, Error **errp)
787 {
788 PnvMachineState *pnv = POWERNV_MACHINE(obj);
789 uint32_t num_chips;
790 Error *local_err = NULL;
791
792 visit_type_uint32(v, name, &num_chips, &local_err);
793 if (local_err) {
794 error_propagate(errp, local_err);
795 return;
796 }
797
798 /*
799 * TODO: should we decide on how many chips we can create based
800 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
801 */
802 if (!is_power_of_2(num_chips) || num_chips > 4) {
803 error_setg(errp, "invalid number of chips: '%d'", num_chips);
804 return;
805 }
806
807 pnv->num_chips = num_chips;
808 }
809
810 static void powernv_machine_initfn(Object *obj)
811 {
812 PnvMachineState *pnv = POWERNV_MACHINE(obj);
813 pnv->num_chips = 1;
814 }
815
816 static void powernv_machine_class_props_init(ObjectClass *oc)
817 {
818 object_class_property_add(oc, "num-chips", "uint32_t",
819 pnv_get_num_chips, pnv_set_num_chips,
820 NULL, NULL, NULL);
821 object_class_property_set_description(oc, "num-chips",
822 "Specifies the number of processor chips",
823 NULL);
824 }
825
826 static void powernv_machine_class_init(ObjectClass *oc, void *data)
827 {
828 MachineClass *mc = MACHINE_CLASS(oc);
829 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
830 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
831
832 mc->desc = "IBM PowerNV (Non-Virtualized)";
833 mc->init = ppc_powernv_init;
834 mc->reset = ppc_powernv_reset;
835 mc->max_cpus = MAX_CPUS;
836 mc->block_default_type = IF_IDE; /* Pnv provides a AHCI device for
837 * storage */
838 mc->no_parallel = 1;
839 mc->default_boot_order = NULL;
840 mc->default_ram_size = 1 * G_BYTE;
841 xic->icp_get = pnv_icp_get;
842 ispc->print_info = pnv_pic_print_info;
843
844 powernv_machine_class_props_init(oc);
845 }
846
847 static const TypeInfo powernv_machine_info = {
848 .name = TYPE_POWERNV_MACHINE,
849 .parent = TYPE_MACHINE,
850 .instance_size = sizeof(PnvMachineState),
851 .instance_init = powernv_machine_initfn,
852 .class_init = powernv_machine_class_init,
853 .interfaces = (InterfaceInfo[]) {
854 { TYPE_XICS_FABRIC },
855 { TYPE_INTERRUPT_STATS_PROVIDER },
856 { },
857 },
858 };
859
860 static void powernv_machine_register_types(void)
861 {
862 type_register_static(&powernv_machine_info);
863 type_register_static(&pnv_chip_info);
864 type_register_static(&pnv_chip_power8e_info);
865 type_register_static(&pnv_chip_power8_info);
866 type_register_static(&pnv_chip_power8nvl_info);
867 type_register_static(&pnv_chip_power9_info);
868 }
869
870 type_init(powernv_machine_register_types)