Merge remote-tracking branch 'remotes/philmd-gitlab/tags/renesas-20201027' into staging
[qemu.git] / hw / ppc / pnv_core.c
1 /*
2 * QEMU PowerPC PowerNV CPU Core model
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public License
8 * as published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "sysemu/reset.h"
22 #include "qapi/error.h"
23 #include "qemu/log.h"
24 #include "qemu/module.h"
25 #include "target/ppc/cpu.h"
26 #include "hw/ppc/ppc.h"
27 #include "hw/ppc/pnv.h"
28 #include "hw/ppc/pnv_core.h"
29 #include "hw/ppc/pnv_xscom.h"
30 #include "hw/ppc/xics.h"
31 #include "hw/qdev-properties.h"
32
33 static const char *pnv_core_cpu_typename(PnvCore *pc)
34 {
35 const char *core_type = object_class_get_name(object_get_class(OBJECT(pc)));
36 int len = strlen(core_type) - strlen(PNV_CORE_TYPE_SUFFIX);
37 char *s = g_strdup_printf(POWERPC_CPU_TYPE_NAME("%.*s"), len, core_type);
38 const char *cpu_type = object_class_get_name(object_class_by_name(s));
39 g_free(s);
40 return cpu_type;
41 }
42
43 static void pnv_core_cpu_reset(PnvCore *pc, PowerPCCPU *cpu)
44 {
45 CPUState *cs = CPU(cpu);
46 CPUPPCState *env = &cpu->env;
47 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip);
48
49 cpu_reset(cs);
50
51 /*
52 * the skiboot firmware elects a primary thread to initialize the
53 * system and it can be any.
54 */
55 env->gpr[3] = PNV_FDT_ADDR;
56 env->nip = 0x10;
57 env->msr |= MSR_HVB; /* Hypervisor mode */
58
59 env->spr[SPR_HRMOR] = pc->hrmor;
60
61 pcc->intc_reset(pc->chip, cpu);
62 }
63
64 /*
65 * These values are read by the PowerNV HW monitors under Linux
66 */
67 #define PNV_XSCOM_EX_DTS_RESULT0 0x50000
68 #define PNV_XSCOM_EX_DTS_RESULT1 0x50001
69
70 static uint64_t pnv_core_power8_xscom_read(void *opaque, hwaddr addr,
71 unsigned int width)
72 {
73 uint32_t offset = addr >> 3;
74 uint64_t val = 0;
75
76 /* The result should be 38 C */
77 switch (offset) {
78 case PNV_XSCOM_EX_DTS_RESULT0:
79 val = 0x26f024f023f0000ull;
80 break;
81 case PNV_XSCOM_EX_DTS_RESULT1:
82 val = 0x24f000000000000ull;
83 break;
84 default:
85 qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
86 addr);
87 }
88
89 return val;
90 }
91
92 static void pnv_core_power8_xscom_write(void *opaque, hwaddr addr, uint64_t val,
93 unsigned int width)
94 {
95 qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
96 addr);
97 }
98
99 static const MemoryRegionOps pnv_core_power8_xscom_ops = {
100 .read = pnv_core_power8_xscom_read,
101 .write = pnv_core_power8_xscom_write,
102 .valid.min_access_size = 8,
103 .valid.max_access_size = 8,
104 .impl.min_access_size = 8,
105 .impl.max_access_size = 8,
106 .endianness = DEVICE_BIG_ENDIAN,
107 };
108
109
110 /*
111 * POWER9 core controls
112 */
113 #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d
114 #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a
115
116 static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr,
117 unsigned int width)
118 {
119 uint32_t offset = addr >> 3;
120 uint64_t val = 0;
121
122 /* The result should be 38 C */
123 switch (offset) {
124 case PNV_XSCOM_EX_DTS_RESULT0:
125 val = 0x26f024f023f0000ull;
126 break;
127 case PNV_XSCOM_EX_DTS_RESULT1:
128 val = 0x24f000000000000ull;
129 break;
130 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP:
131 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR:
132 val = 0x0;
133 break;
134 default:
135 qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
136 addr);
137 }
138
139 return val;
140 }
141
142 static void pnv_core_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val,
143 unsigned int width)
144 {
145 uint32_t offset = addr >> 3;
146
147 switch (offset) {
148 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP:
149 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR:
150 break;
151 default:
152 qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
153 addr);
154 }
155 }
156
157 static const MemoryRegionOps pnv_core_power9_xscom_ops = {
158 .read = pnv_core_power9_xscom_read,
159 .write = pnv_core_power9_xscom_write,
160 .valid.min_access_size = 8,
161 .valid.max_access_size = 8,
162 .impl.min_access_size = 8,
163 .impl.max_access_size = 8,
164 .endianness = DEVICE_BIG_ENDIAN,
165 };
166
167 static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp)
168 {
169 CPUPPCState *env = &cpu->env;
170 int core_pir;
171 int thread_index = 0; /* TODO: TCG supports only one thread */
172 ppc_spr_t *pir = &env->spr_cb[SPR_PIR];
173 Error *local_err = NULL;
174 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip);
175
176 if (!qdev_realize(DEVICE(cpu), NULL, errp)) {
177 return;
178 }
179
180 pcc->intc_create(pc->chip, cpu, &local_err);
181 if (local_err) {
182 error_propagate(errp, local_err);
183 return;
184 }
185
186 core_pir = object_property_get_uint(OBJECT(pc), "pir", &error_abort);
187
188 /*
189 * The PIR of a thread is the core PIR + the thread index. We will
190 * need to find a way to get the thread index when TCG supports
191 * more than 1. We could use the object name ?
192 */
193 pir->default_value = core_pir + thread_index;
194
195 /* Set time-base frequency to 512 MHz */
196 cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ);
197 }
198
199 static void pnv_core_reset(void *dev)
200 {
201 CPUCore *cc = CPU_CORE(dev);
202 PnvCore *pc = PNV_CORE(dev);
203 int i;
204
205 for (i = 0; i < cc->nr_threads; i++) {
206 pnv_core_cpu_reset(pc, pc->threads[i]);
207 }
208 }
209
210 static void pnv_core_realize(DeviceState *dev, Error **errp)
211 {
212 PnvCore *pc = PNV_CORE(OBJECT(dev));
213 PnvCoreClass *pcc = PNV_CORE_GET_CLASS(pc);
214 CPUCore *cc = CPU_CORE(OBJECT(dev));
215 const char *typename = pnv_core_cpu_typename(pc);
216 Error *local_err = NULL;
217 void *obj;
218 int i, j;
219 char name[32];
220
221 assert(pc->chip);
222
223 pc->threads = g_new(PowerPCCPU *, cc->nr_threads);
224 for (i = 0; i < cc->nr_threads; i++) {
225 PowerPCCPU *cpu;
226
227 obj = object_new(typename);
228 cpu = POWERPC_CPU(obj);
229
230 pc->threads[i] = POWERPC_CPU(obj);
231
232 snprintf(name, sizeof(name), "thread[%d]", i);
233 object_property_add_child(OBJECT(pc), name, obj);
234
235 cpu->machine_data = g_new0(PnvCPUState, 1);
236
237 object_unref(obj);
238 }
239
240 for (j = 0; j < cc->nr_threads; j++) {
241 pnv_core_cpu_realize(pc, pc->threads[j], &local_err);
242 if (local_err) {
243 goto err;
244 }
245 }
246
247 snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id);
248 /* TODO: check PNV_XSCOM_EX_SIZE for p10 */
249 pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), pcc->xscom_ops,
250 pc, name, PNV_XSCOM_EX_SIZE);
251
252 qemu_register_reset(pnv_core_reset, pc);
253 return;
254
255 err:
256 while (--i >= 0) {
257 obj = OBJECT(pc->threads[i]);
258 object_unparent(obj);
259 }
260 g_free(pc->threads);
261 error_propagate(errp, local_err);
262 }
263
264 static void pnv_core_cpu_unrealize(PnvCore *pc, PowerPCCPU *cpu)
265 {
266 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
267 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip);
268
269 pcc->intc_destroy(pc->chip, cpu);
270 cpu_remove_sync(CPU(cpu));
271 cpu->machine_data = NULL;
272 g_free(pnv_cpu);
273 object_unparent(OBJECT(cpu));
274 }
275
276 static void pnv_core_unrealize(DeviceState *dev)
277 {
278 PnvCore *pc = PNV_CORE(dev);
279 CPUCore *cc = CPU_CORE(dev);
280 int i;
281
282 qemu_unregister_reset(pnv_core_reset, pc);
283
284 for (i = 0; i < cc->nr_threads; i++) {
285 pnv_core_cpu_unrealize(pc, pc->threads[i]);
286 }
287 g_free(pc->threads);
288 }
289
290 static Property pnv_core_properties[] = {
291 DEFINE_PROP_UINT32("pir", PnvCore, pir, 0),
292 DEFINE_PROP_UINT64("hrmor", PnvCore, hrmor, 0),
293 DEFINE_PROP_LINK("chip", PnvCore, chip, TYPE_PNV_CHIP, PnvChip *),
294 DEFINE_PROP_END_OF_LIST(),
295 };
296
297 static void pnv_core_power8_class_init(ObjectClass *oc, void *data)
298 {
299 PnvCoreClass *pcc = PNV_CORE_CLASS(oc);
300
301 pcc->xscom_ops = &pnv_core_power8_xscom_ops;
302 }
303
304 static void pnv_core_power9_class_init(ObjectClass *oc, void *data)
305 {
306 PnvCoreClass *pcc = PNV_CORE_CLASS(oc);
307
308 pcc->xscom_ops = &pnv_core_power9_xscom_ops;
309 }
310
311 static void pnv_core_power10_class_init(ObjectClass *oc, void *data)
312 {
313 PnvCoreClass *pcc = PNV_CORE_CLASS(oc);
314
315 /* TODO: Use the P9 XSCOMs for now on P10 */
316 pcc->xscom_ops = &pnv_core_power9_xscom_ops;
317 }
318
319 static void pnv_core_class_init(ObjectClass *oc, void *data)
320 {
321 DeviceClass *dc = DEVICE_CLASS(oc);
322
323 dc->realize = pnv_core_realize;
324 dc->unrealize = pnv_core_unrealize;
325 device_class_set_props(dc, pnv_core_properties);
326 dc->user_creatable = false;
327 }
328
329 #define DEFINE_PNV_CORE_TYPE(family, cpu_model) \
330 { \
331 .parent = TYPE_PNV_CORE, \
332 .name = PNV_CORE_TYPE_NAME(cpu_model), \
333 .class_init = pnv_core_##family##_class_init, \
334 }
335
336 static const TypeInfo pnv_core_infos[] = {
337 {
338 .name = TYPE_PNV_CORE,
339 .parent = TYPE_CPU_CORE,
340 .instance_size = sizeof(PnvCore),
341 .class_size = sizeof(PnvCoreClass),
342 .class_init = pnv_core_class_init,
343 .abstract = true,
344 },
345 DEFINE_PNV_CORE_TYPE(power8, "power8e_v2.1"),
346 DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"),
347 DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"),
348 DEFINE_PNV_CORE_TYPE(power9, "power9_v2.0"),
349 DEFINE_PNV_CORE_TYPE(power10, "power10_v1.0"),
350 };
351
352 DEFINE_TYPES(pnv_core_infos)
353
354 /*
355 * POWER9 Quads
356 */
357
358 #define P9X_EX_NCU_SPEC_BAR 0x11010
359
360 static uint64_t pnv_quad_xscom_read(void *opaque, hwaddr addr,
361 unsigned int width)
362 {
363 uint32_t offset = addr >> 3;
364 uint64_t val = -1;
365
366 switch (offset) {
367 case P9X_EX_NCU_SPEC_BAR:
368 case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */
369 val = 0;
370 break;
371 default:
372 qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
373 offset);
374 }
375
376 return val;
377 }
378
379 static void pnv_quad_xscom_write(void *opaque, hwaddr addr, uint64_t val,
380 unsigned int width)
381 {
382 uint32_t offset = addr >> 3;
383
384 switch (offset) {
385 case P9X_EX_NCU_SPEC_BAR:
386 case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */
387 break;
388 default:
389 qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
390 offset);
391 }
392 }
393
394 static const MemoryRegionOps pnv_quad_xscom_ops = {
395 .read = pnv_quad_xscom_read,
396 .write = pnv_quad_xscom_write,
397 .valid.min_access_size = 8,
398 .valid.max_access_size = 8,
399 .impl.min_access_size = 8,
400 .impl.max_access_size = 8,
401 .endianness = DEVICE_BIG_ENDIAN,
402 };
403
404 static void pnv_quad_realize(DeviceState *dev, Error **errp)
405 {
406 PnvQuad *eq = PNV_QUAD(dev);
407 char name[32];
408
409 snprintf(name, sizeof(name), "xscom-quad.%d", eq->id);
410 pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), &pnv_quad_xscom_ops,
411 eq, name, PNV9_XSCOM_EQ_SIZE);
412 }
413
414 static Property pnv_quad_properties[] = {
415 DEFINE_PROP_UINT32("id", PnvQuad, id, 0),
416 DEFINE_PROP_END_OF_LIST(),
417 };
418
419 static void pnv_quad_class_init(ObjectClass *oc, void *data)
420 {
421 DeviceClass *dc = DEVICE_CLASS(oc);
422
423 dc->realize = pnv_quad_realize;
424 device_class_set_props(dc, pnv_quad_properties);
425 dc->user_creatable = false;
426 }
427
428 static const TypeInfo pnv_quad_info = {
429 .name = TYPE_PNV_QUAD,
430 .parent = TYPE_DEVICE,
431 .instance_size = sizeof(PnvQuad),
432 .class_init = pnv_quad_class_init,
433 };
434
435 static void pnv_core_register_types(void)
436 {
437 type_register_static(&pnv_quad_info);
438 }
439
440 type_init(pnv_core_register_types)