Merge tag 'pull-target-arm-20211207' of https://git.linaro.org/people/pmaydell/qemu...
[qemu.git] / hw / ppc / pnv_core.c
1 /*
2 * QEMU PowerPC PowerNV CPU Core model
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public License
8 * as published by the Free Software Foundation; either version 2.1 of
9 * the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "sysemu/reset.h"
22 #include "qapi/error.h"
23 #include "qemu/log.h"
24 #include "qemu/module.h"
25 #include "target/ppc/cpu.h"
26 #include "hw/ppc/ppc.h"
27 #include "hw/ppc/pnv.h"
28 #include "hw/ppc/pnv_core.h"
29 #include "hw/ppc/pnv_xscom.h"
30 #include "hw/ppc/xics.h"
31 #include "hw/qdev-properties.h"
32 #include "helper_regs.h"
33
34 static const char *pnv_core_cpu_typename(PnvCore *pc)
35 {
36 const char *core_type = object_class_get_name(object_get_class(OBJECT(pc)));
37 int len = strlen(core_type) - strlen(PNV_CORE_TYPE_SUFFIX);
38 char *s = g_strdup_printf(POWERPC_CPU_TYPE_NAME("%.*s"), len, core_type);
39 const char *cpu_type = object_class_get_name(object_class_by_name(s));
40 g_free(s);
41 return cpu_type;
42 }
43
44 static void pnv_core_cpu_reset(PnvCore *pc, PowerPCCPU *cpu)
45 {
46 CPUState *cs = CPU(cpu);
47 CPUPPCState *env = &cpu->env;
48 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip);
49
50 cpu_reset(cs);
51
52 /*
53 * the skiboot firmware elects a primary thread to initialize the
54 * system and it can be any.
55 */
56 env->gpr[3] = PNV_FDT_ADDR;
57 env->nip = 0x10;
58 env->msr |= MSR_HVB; /* Hypervisor mode */
59 env->spr[SPR_HRMOR] = pc->hrmor;
60 hreg_compute_hflags(env);
61
62 pcc->intc_reset(pc->chip, cpu);
63 }
64
65 /*
66 * These values are read by the PowerNV HW monitors under Linux
67 */
68 #define PNV_XSCOM_EX_DTS_RESULT0 0x50000
69 #define PNV_XSCOM_EX_DTS_RESULT1 0x50001
70
71 static uint64_t pnv_core_power8_xscom_read(void *opaque, hwaddr addr,
72 unsigned int width)
73 {
74 uint32_t offset = addr >> 3;
75 uint64_t val = 0;
76
77 /* The result should be 38 C */
78 switch (offset) {
79 case PNV_XSCOM_EX_DTS_RESULT0:
80 val = 0x26f024f023f0000ull;
81 break;
82 case PNV_XSCOM_EX_DTS_RESULT1:
83 val = 0x24f000000000000ull;
84 break;
85 default:
86 qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
87 addr);
88 }
89
90 return val;
91 }
92
93 static void pnv_core_power8_xscom_write(void *opaque, hwaddr addr, uint64_t val,
94 unsigned int width)
95 {
96 qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
97 addr);
98 }
99
100 static const MemoryRegionOps pnv_core_power8_xscom_ops = {
101 .read = pnv_core_power8_xscom_read,
102 .write = pnv_core_power8_xscom_write,
103 .valid.min_access_size = 8,
104 .valid.max_access_size = 8,
105 .impl.min_access_size = 8,
106 .impl.max_access_size = 8,
107 .endianness = DEVICE_BIG_ENDIAN,
108 };
109
110
111 /*
112 * POWER9 core controls
113 */
114 #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d
115 #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a
116
117 static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr,
118 unsigned int width)
119 {
120 uint32_t offset = addr >> 3;
121 uint64_t val = 0;
122
123 /* The result should be 38 C */
124 switch (offset) {
125 case PNV_XSCOM_EX_DTS_RESULT0:
126 val = 0x26f024f023f0000ull;
127 break;
128 case PNV_XSCOM_EX_DTS_RESULT1:
129 val = 0x24f000000000000ull;
130 break;
131 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP:
132 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR:
133 val = 0x0;
134 break;
135 default:
136 qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n",
137 addr);
138 }
139
140 return val;
141 }
142
143 static void pnv_core_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val,
144 unsigned int width)
145 {
146 uint32_t offset = addr >> 3;
147
148 switch (offset) {
149 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP:
150 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR:
151 break;
152 default:
153 qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n",
154 addr);
155 }
156 }
157
158 static const MemoryRegionOps pnv_core_power9_xscom_ops = {
159 .read = pnv_core_power9_xscom_read,
160 .write = pnv_core_power9_xscom_write,
161 .valid.min_access_size = 8,
162 .valid.max_access_size = 8,
163 .impl.min_access_size = 8,
164 .impl.max_access_size = 8,
165 .endianness = DEVICE_BIG_ENDIAN,
166 };
167
168 static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp)
169 {
170 CPUPPCState *env = &cpu->env;
171 int core_pir;
172 int thread_index = 0; /* TODO: TCG supports only one thread */
173 ppc_spr_t *pir = &env->spr_cb[SPR_PIR];
174 Error *local_err = NULL;
175 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip);
176
177 if (!qdev_realize(DEVICE(cpu), NULL, errp)) {
178 return;
179 }
180
181 pcc->intc_create(pc->chip, cpu, &local_err);
182 if (local_err) {
183 error_propagate(errp, local_err);
184 return;
185 }
186
187 core_pir = object_property_get_uint(OBJECT(pc), "pir", &error_abort);
188
189 /*
190 * The PIR of a thread is the core PIR + the thread index. We will
191 * need to find a way to get the thread index when TCG supports
192 * more than 1. We could use the object name ?
193 */
194 pir->default_value = core_pir + thread_index;
195
196 /* Set time-base frequency to 512 MHz */
197 cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ);
198 }
199
200 static void pnv_core_reset(void *dev)
201 {
202 CPUCore *cc = CPU_CORE(dev);
203 PnvCore *pc = PNV_CORE(dev);
204 int i;
205
206 for (i = 0; i < cc->nr_threads; i++) {
207 pnv_core_cpu_reset(pc, pc->threads[i]);
208 }
209 }
210
211 static void pnv_core_realize(DeviceState *dev, Error **errp)
212 {
213 PnvCore *pc = PNV_CORE(OBJECT(dev));
214 PnvCoreClass *pcc = PNV_CORE_GET_CLASS(pc);
215 CPUCore *cc = CPU_CORE(OBJECT(dev));
216 const char *typename = pnv_core_cpu_typename(pc);
217 Error *local_err = NULL;
218 void *obj;
219 int i, j;
220 char name[32];
221
222 assert(pc->chip);
223
224 pc->threads = g_new(PowerPCCPU *, cc->nr_threads);
225 for (i = 0; i < cc->nr_threads; i++) {
226 PowerPCCPU *cpu;
227
228 obj = object_new(typename);
229 cpu = POWERPC_CPU(obj);
230
231 pc->threads[i] = POWERPC_CPU(obj);
232
233 snprintf(name, sizeof(name), "thread[%d]", i);
234 object_property_add_child(OBJECT(pc), name, obj);
235
236 cpu->machine_data = g_new0(PnvCPUState, 1);
237
238 object_unref(obj);
239 }
240
241 for (j = 0; j < cc->nr_threads; j++) {
242 pnv_core_cpu_realize(pc, pc->threads[j], &local_err);
243 if (local_err) {
244 goto err;
245 }
246 }
247
248 snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id);
249 /* TODO: check PNV_XSCOM_EX_SIZE for p10 */
250 pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), pcc->xscom_ops,
251 pc, name, PNV_XSCOM_EX_SIZE);
252
253 qemu_register_reset(pnv_core_reset, pc);
254 return;
255
256 err:
257 while (--i >= 0) {
258 obj = OBJECT(pc->threads[i]);
259 object_unparent(obj);
260 }
261 g_free(pc->threads);
262 error_propagate(errp, local_err);
263 }
264
265 static void pnv_core_cpu_unrealize(PnvCore *pc, PowerPCCPU *cpu)
266 {
267 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
268 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip);
269
270 pcc->intc_destroy(pc->chip, cpu);
271 cpu_remove_sync(CPU(cpu));
272 cpu->machine_data = NULL;
273 g_free(pnv_cpu);
274 object_unparent(OBJECT(cpu));
275 }
276
277 static void pnv_core_unrealize(DeviceState *dev)
278 {
279 PnvCore *pc = PNV_CORE(dev);
280 CPUCore *cc = CPU_CORE(dev);
281 int i;
282
283 qemu_unregister_reset(pnv_core_reset, pc);
284
285 for (i = 0; i < cc->nr_threads; i++) {
286 pnv_core_cpu_unrealize(pc, pc->threads[i]);
287 }
288 g_free(pc->threads);
289 }
290
291 static Property pnv_core_properties[] = {
292 DEFINE_PROP_UINT32("pir", PnvCore, pir, 0),
293 DEFINE_PROP_UINT64("hrmor", PnvCore, hrmor, 0),
294 DEFINE_PROP_LINK("chip", PnvCore, chip, TYPE_PNV_CHIP, PnvChip *),
295 DEFINE_PROP_END_OF_LIST(),
296 };
297
298 static void pnv_core_power8_class_init(ObjectClass *oc, void *data)
299 {
300 PnvCoreClass *pcc = PNV_CORE_CLASS(oc);
301
302 pcc->xscom_ops = &pnv_core_power8_xscom_ops;
303 }
304
305 static void pnv_core_power9_class_init(ObjectClass *oc, void *data)
306 {
307 PnvCoreClass *pcc = PNV_CORE_CLASS(oc);
308
309 pcc->xscom_ops = &pnv_core_power9_xscom_ops;
310 }
311
312 static void pnv_core_power10_class_init(ObjectClass *oc, void *data)
313 {
314 PnvCoreClass *pcc = PNV_CORE_CLASS(oc);
315
316 /* TODO: Use the P9 XSCOMs for now on P10 */
317 pcc->xscom_ops = &pnv_core_power9_xscom_ops;
318 }
319
320 static void pnv_core_class_init(ObjectClass *oc, void *data)
321 {
322 DeviceClass *dc = DEVICE_CLASS(oc);
323
324 dc->realize = pnv_core_realize;
325 dc->unrealize = pnv_core_unrealize;
326 device_class_set_props(dc, pnv_core_properties);
327 dc->user_creatable = false;
328 }
329
330 #define DEFINE_PNV_CORE_TYPE(family, cpu_model) \
331 { \
332 .parent = TYPE_PNV_CORE, \
333 .name = PNV_CORE_TYPE_NAME(cpu_model), \
334 .class_init = pnv_core_##family##_class_init, \
335 }
336
337 static const TypeInfo pnv_core_infos[] = {
338 {
339 .name = TYPE_PNV_CORE,
340 .parent = TYPE_CPU_CORE,
341 .instance_size = sizeof(PnvCore),
342 .class_size = sizeof(PnvCoreClass),
343 .class_init = pnv_core_class_init,
344 .abstract = true,
345 },
346 DEFINE_PNV_CORE_TYPE(power8, "power8e_v2.1"),
347 DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"),
348 DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"),
349 DEFINE_PNV_CORE_TYPE(power9, "power9_v2.0"),
350 DEFINE_PNV_CORE_TYPE(power10, "power10_v1.0"),
351 };
352
353 DEFINE_TYPES(pnv_core_infos)
354
355 /*
356 * POWER9 Quads
357 */
358
359 #define P9X_EX_NCU_SPEC_BAR 0x11010
360
361 static uint64_t pnv_quad_xscom_read(void *opaque, hwaddr addr,
362 unsigned int width)
363 {
364 uint32_t offset = addr >> 3;
365 uint64_t val = -1;
366
367 switch (offset) {
368 case P9X_EX_NCU_SPEC_BAR:
369 case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */
370 val = 0;
371 break;
372 default:
373 qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
374 offset);
375 }
376
377 return val;
378 }
379
380 static void pnv_quad_xscom_write(void *opaque, hwaddr addr, uint64_t val,
381 unsigned int width)
382 {
383 uint32_t offset = addr >> 3;
384
385 switch (offset) {
386 case P9X_EX_NCU_SPEC_BAR:
387 case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */
388 break;
389 default:
390 qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__,
391 offset);
392 }
393 }
394
395 static const MemoryRegionOps pnv_quad_xscom_ops = {
396 .read = pnv_quad_xscom_read,
397 .write = pnv_quad_xscom_write,
398 .valid.min_access_size = 8,
399 .valid.max_access_size = 8,
400 .impl.min_access_size = 8,
401 .impl.max_access_size = 8,
402 .endianness = DEVICE_BIG_ENDIAN,
403 };
404
405 static void pnv_quad_realize(DeviceState *dev, Error **errp)
406 {
407 PnvQuad *eq = PNV_QUAD(dev);
408 char name[32];
409
410 snprintf(name, sizeof(name), "xscom-quad.%d", eq->id);
411 pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), &pnv_quad_xscom_ops,
412 eq, name, PNV9_XSCOM_EQ_SIZE);
413 }
414
415 static Property pnv_quad_properties[] = {
416 DEFINE_PROP_UINT32("id", PnvQuad, id, 0),
417 DEFINE_PROP_END_OF_LIST(),
418 };
419
420 static void pnv_quad_class_init(ObjectClass *oc, void *data)
421 {
422 DeviceClass *dc = DEVICE_CLASS(oc);
423
424 dc->realize = pnv_quad_realize;
425 device_class_set_props(dc, pnv_quad_properties);
426 dc->user_creatable = false;
427 }
428
429 static const TypeInfo pnv_quad_info = {
430 .name = TYPE_PNV_QUAD,
431 .parent = TYPE_DEVICE,
432 .instance_size = sizeof(PnvQuad),
433 .class_init = pnv_quad_class_init,
434 };
435
436 static void pnv_core_register_types(void)
437 {
438 type_register_static(&pnv_quad_info);
439 }
440
441 type_init(pnv_core_register_types)