target-ppc: Clean up ENV_GET_CPU() usage
[qemu.git] / hw / ppc / ppc405_uc.c
1 /*
2 * QEMU PowerPC 405 embedded processors emulation
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw/hw.h"
25 #include "hw/ppc/ppc.h"
26 #include "ppc405.h"
27 #include "hw/char/serial.h"
28 #include "qemu/timer.h"
29 #include "sysemu/sysemu.h"
30 #include "qemu/log.h"
31 #include "exec/address-spaces.h"
32
33 //#define DEBUG_OPBA
34 //#define DEBUG_SDRAM
35 //#define DEBUG_GPIO
36 //#define DEBUG_SERIAL
37 //#define DEBUG_OCM
38 //#define DEBUG_I2C
39 //#define DEBUG_GPT
40 //#define DEBUG_MAL
41 //#define DEBUG_CLOCKS
42 //#define DEBUG_CLOCKS_LL
43
44 ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
45 uint32_t flags)
46 {
47 CPUState *cs = CPU(ppc_env_get_cpu(env));
48 ram_addr_t bdloc;
49 int i, n;
50
51 /* We put the bd structure at the top of memory */
52 if (bd->bi_memsize >= 0x01000000UL)
53 bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t);
54 else
55 bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
56 stl_be_phys(cs->as, bdloc + 0x00, bd->bi_memstart);
57 stl_be_phys(cs->as, bdloc + 0x04, bd->bi_memsize);
58 stl_be_phys(cs->as, bdloc + 0x08, bd->bi_flashstart);
59 stl_be_phys(cs->as, bdloc + 0x0C, bd->bi_flashsize);
60 stl_be_phys(cs->as, bdloc + 0x10, bd->bi_flashoffset);
61 stl_be_phys(cs->as, bdloc + 0x14, bd->bi_sramstart);
62 stl_be_phys(cs->as, bdloc + 0x18, bd->bi_sramsize);
63 stl_be_phys(cs->as, bdloc + 0x1C, bd->bi_bootflags);
64 stl_be_phys(cs->as, bdloc + 0x20, bd->bi_ipaddr);
65 for (i = 0; i < 6; i++) {
66 stb_phys(cs->as, bdloc + 0x24 + i, bd->bi_enetaddr[i]);
67 }
68 stw_be_phys(cs->as, bdloc + 0x2A, bd->bi_ethspeed);
69 stl_be_phys(cs->as, bdloc + 0x2C, bd->bi_intfreq);
70 stl_be_phys(cs->as, bdloc + 0x30, bd->bi_busfreq);
71 stl_be_phys(cs->as, bdloc + 0x34, bd->bi_baudrate);
72 for (i = 0; i < 4; i++) {
73 stb_phys(cs->as, bdloc + 0x38 + i, bd->bi_s_version[i]);
74 }
75 for (i = 0; i < 32; i++) {
76 stb_phys(cs->as, bdloc + 0x3C + i, bd->bi_r_version[i]);
77 }
78 stl_be_phys(cs->as, bdloc + 0x5C, bd->bi_plb_busfreq);
79 stl_be_phys(cs->as, bdloc + 0x60, bd->bi_pci_busfreq);
80 for (i = 0; i < 6; i++) {
81 stb_phys(cs->as, bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
82 }
83 n = 0x6A;
84 if (flags & 0x00000001) {
85 for (i = 0; i < 6; i++)
86 stb_phys(cs->as, bdloc + n++, bd->bi_pci_enetaddr2[i]);
87 }
88 stl_be_phys(cs->as, bdloc + n, bd->bi_opbfreq);
89 n += 4;
90 for (i = 0; i < 2; i++) {
91 stl_be_phys(cs->as, bdloc + n, bd->bi_iic_fast[i]);
92 n += 4;
93 }
94
95 return bdloc;
96 }
97
98 /*****************************************************************************/
99 /* Shared peripherals */
100
101 /*****************************************************************************/
102 /* Peripheral local bus arbitrer */
103 enum {
104 PLB0_BESR = 0x084,
105 PLB0_BEAR = 0x086,
106 PLB0_ACR = 0x087,
107 };
108
109 typedef struct ppc4xx_plb_t ppc4xx_plb_t;
110 struct ppc4xx_plb_t {
111 uint32_t acr;
112 uint32_t bear;
113 uint32_t besr;
114 };
115
116 static uint32_t dcr_read_plb (void *opaque, int dcrn)
117 {
118 ppc4xx_plb_t *plb;
119 uint32_t ret;
120
121 plb = opaque;
122 switch (dcrn) {
123 case PLB0_ACR:
124 ret = plb->acr;
125 break;
126 case PLB0_BEAR:
127 ret = plb->bear;
128 break;
129 case PLB0_BESR:
130 ret = plb->besr;
131 break;
132 default:
133 /* Avoid gcc warning */
134 ret = 0;
135 break;
136 }
137
138 return ret;
139 }
140
141 static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
142 {
143 ppc4xx_plb_t *plb;
144
145 plb = opaque;
146 switch (dcrn) {
147 case PLB0_ACR:
148 /* We don't care about the actual parameters written as
149 * we don't manage any priorities on the bus
150 */
151 plb->acr = val & 0xF8000000;
152 break;
153 case PLB0_BEAR:
154 /* Read only */
155 break;
156 case PLB0_BESR:
157 /* Write-clear */
158 plb->besr &= ~val;
159 break;
160 }
161 }
162
163 static void ppc4xx_plb_reset (void *opaque)
164 {
165 ppc4xx_plb_t *plb;
166
167 plb = opaque;
168 plb->acr = 0x00000000;
169 plb->bear = 0x00000000;
170 plb->besr = 0x00000000;
171 }
172
173 static void ppc4xx_plb_init(CPUPPCState *env)
174 {
175 ppc4xx_plb_t *plb;
176
177 plb = g_malloc0(sizeof(ppc4xx_plb_t));
178 ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
179 ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
180 ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
181 qemu_register_reset(ppc4xx_plb_reset, plb);
182 }
183
184 /*****************************************************************************/
185 /* PLB to OPB bridge */
186 enum {
187 POB0_BESR0 = 0x0A0,
188 POB0_BESR1 = 0x0A2,
189 POB0_BEAR = 0x0A4,
190 };
191
192 typedef struct ppc4xx_pob_t ppc4xx_pob_t;
193 struct ppc4xx_pob_t {
194 uint32_t bear;
195 uint32_t besr0;
196 uint32_t besr1;
197 };
198
199 static uint32_t dcr_read_pob (void *opaque, int dcrn)
200 {
201 ppc4xx_pob_t *pob;
202 uint32_t ret;
203
204 pob = opaque;
205 switch (dcrn) {
206 case POB0_BEAR:
207 ret = pob->bear;
208 break;
209 case POB0_BESR0:
210 ret = pob->besr0;
211 break;
212 case POB0_BESR1:
213 ret = pob->besr1;
214 break;
215 default:
216 /* Avoid gcc warning */
217 ret = 0;
218 break;
219 }
220
221 return ret;
222 }
223
224 static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
225 {
226 ppc4xx_pob_t *pob;
227
228 pob = opaque;
229 switch (dcrn) {
230 case POB0_BEAR:
231 /* Read only */
232 break;
233 case POB0_BESR0:
234 /* Write-clear */
235 pob->besr0 &= ~val;
236 break;
237 case POB0_BESR1:
238 /* Write-clear */
239 pob->besr1 &= ~val;
240 break;
241 }
242 }
243
244 static void ppc4xx_pob_reset (void *opaque)
245 {
246 ppc4xx_pob_t *pob;
247
248 pob = opaque;
249 /* No error */
250 pob->bear = 0x00000000;
251 pob->besr0 = 0x0000000;
252 pob->besr1 = 0x0000000;
253 }
254
255 static void ppc4xx_pob_init(CPUPPCState *env)
256 {
257 ppc4xx_pob_t *pob;
258
259 pob = g_malloc0(sizeof(ppc4xx_pob_t));
260 ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
261 ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
262 ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
263 qemu_register_reset(ppc4xx_pob_reset, pob);
264 }
265
266 /*****************************************************************************/
267 /* OPB arbitrer */
268 typedef struct ppc4xx_opba_t ppc4xx_opba_t;
269 struct ppc4xx_opba_t {
270 MemoryRegion io;
271 uint8_t cr;
272 uint8_t pr;
273 };
274
275 static uint32_t opba_readb (void *opaque, hwaddr addr)
276 {
277 ppc4xx_opba_t *opba;
278 uint32_t ret;
279
280 #ifdef DEBUG_OPBA
281 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
282 #endif
283 opba = opaque;
284 switch (addr) {
285 case 0x00:
286 ret = opba->cr;
287 break;
288 case 0x01:
289 ret = opba->pr;
290 break;
291 default:
292 ret = 0x00;
293 break;
294 }
295
296 return ret;
297 }
298
299 static void opba_writeb (void *opaque,
300 hwaddr addr, uint32_t value)
301 {
302 ppc4xx_opba_t *opba;
303
304 #ifdef DEBUG_OPBA
305 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
306 value);
307 #endif
308 opba = opaque;
309 switch (addr) {
310 case 0x00:
311 opba->cr = value & 0xF8;
312 break;
313 case 0x01:
314 opba->pr = value & 0xFF;
315 break;
316 default:
317 break;
318 }
319 }
320
321 static uint32_t opba_readw (void *opaque, hwaddr addr)
322 {
323 uint32_t ret;
324
325 #ifdef DEBUG_OPBA
326 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
327 #endif
328 ret = opba_readb(opaque, addr) << 8;
329 ret |= opba_readb(opaque, addr + 1);
330
331 return ret;
332 }
333
334 static void opba_writew (void *opaque,
335 hwaddr addr, uint32_t value)
336 {
337 #ifdef DEBUG_OPBA
338 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
339 value);
340 #endif
341 opba_writeb(opaque, addr, value >> 8);
342 opba_writeb(opaque, addr + 1, value);
343 }
344
345 static uint32_t opba_readl (void *opaque, hwaddr addr)
346 {
347 uint32_t ret;
348
349 #ifdef DEBUG_OPBA
350 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
351 #endif
352 ret = opba_readb(opaque, addr) << 24;
353 ret |= opba_readb(opaque, addr + 1) << 16;
354
355 return ret;
356 }
357
358 static void opba_writel (void *opaque,
359 hwaddr addr, uint32_t value)
360 {
361 #ifdef DEBUG_OPBA
362 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
363 value);
364 #endif
365 opba_writeb(opaque, addr, value >> 24);
366 opba_writeb(opaque, addr + 1, value >> 16);
367 }
368
369 static const MemoryRegionOps opba_ops = {
370 .old_mmio = {
371 .read = { opba_readb, opba_readw, opba_readl, },
372 .write = { opba_writeb, opba_writew, opba_writel, },
373 },
374 .endianness = DEVICE_NATIVE_ENDIAN,
375 };
376
377 static void ppc4xx_opba_reset (void *opaque)
378 {
379 ppc4xx_opba_t *opba;
380
381 opba = opaque;
382 opba->cr = 0x00; /* No dynamic priorities - park disabled */
383 opba->pr = 0x11;
384 }
385
386 static void ppc4xx_opba_init(hwaddr base)
387 {
388 ppc4xx_opba_t *opba;
389
390 opba = g_malloc0(sizeof(ppc4xx_opba_t));
391 #ifdef DEBUG_OPBA
392 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
393 #endif
394 memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002);
395 memory_region_add_subregion(get_system_memory(), base, &opba->io);
396 qemu_register_reset(ppc4xx_opba_reset, opba);
397 }
398
399 /*****************************************************************************/
400 /* Code decompression controller */
401 /* XXX: TODO */
402
403 /*****************************************************************************/
404 /* Peripheral controller */
405 typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
406 struct ppc4xx_ebc_t {
407 uint32_t addr;
408 uint32_t bcr[8];
409 uint32_t bap[8];
410 uint32_t bear;
411 uint32_t besr0;
412 uint32_t besr1;
413 uint32_t cfg;
414 };
415
416 enum {
417 EBC0_CFGADDR = 0x012,
418 EBC0_CFGDATA = 0x013,
419 };
420
421 static uint32_t dcr_read_ebc (void *opaque, int dcrn)
422 {
423 ppc4xx_ebc_t *ebc;
424 uint32_t ret;
425
426 ebc = opaque;
427 switch (dcrn) {
428 case EBC0_CFGADDR:
429 ret = ebc->addr;
430 break;
431 case EBC0_CFGDATA:
432 switch (ebc->addr) {
433 case 0x00: /* B0CR */
434 ret = ebc->bcr[0];
435 break;
436 case 0x01: /* B1CR */
437 ret = ebc->bcr[1];
438 break;
439 case 0x02: /* B2CR */
440 ret = ebc->bcr[2];
441 break;
442 case 0x03: /* B3CR */
443 ret = ebc->bcr[3];
444 break;
445 case 0x04: /* B4CR */
446 ret = ebc->bcr[4];
447 break;
448 case 0x05: /* B5CR */
449 ret = ebc->bcr[5];
450 break;
451 case 0x06: /* B6CR */
452 ret = ebc->bcr[6];
453 break;
454 case 0x07: /* B7CR */
455 ret = ebc->bcr[7];
456 break;
457 case 0x10: /* B0AP */
458 ret = ebc->bap[0];
459 break;
460 case 0x11: /* B1AP */
461 ret = ebc->bap[1];
462 break;
463 case 0x12: /* B2AP */
464 ret = ebc->bap[2];
465 break;
466 case 0x13: /* B3AP */
467 ret = ebc->bap[3];
468 break;
469 case 0x14: /* B4AP */
470 ret = ebc->bap[4];
471 break;
472 case 0x15: /* B5AP */
473 ret = ebc->bap[5];
474 break;
475 case 0x16: /* B6AP */
476 ret = ebc->bap[6];
477 break;
478 case 0x17: /* B7AP */
479 ret = ebc->bap[7];
480 break;
481 case 0x20: /* BEAR */
482 ret = ebc->bear;
483 break;
484 case 0x21: /* BESR0 */
485 ret = ebc->besr0;
486 break;
487 case 0x22: /* BESR1 */
488 ret = ebc->besr1;
489 break;
490 case 0x23: /* CFG */
491 ret = ebc->cfg;
492 break;
493 default:
494 ret = 0x00000000;
495 break;
496 }
497 break;
498 default:
499 ret = 0x00000000;
500 break;
501 }
502
503 return ret;
504 }
505
506 static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
507 {
508 ppc4xx_ebc_t *ebc;
509
510 ebc = opaque;
511 switch (dcrn) {
512 case EBC0_CFGADDR:
513 ebc->addr = val;
514 break;
515 case EBC0_CFGDATA:
516 switch (ebc->addr) {
517 case 0x00: /* B0CR */
518 break;
519 case 0x01: /* B1CR */
520 break;
521 case 0x02: /* B2CR */
522 break;
523 case 0x03: /* B3CR */
524 break;
525 case 0x04: /* B4CR */
526 break;
527 case 0x05: /* B5CR */
528 break;
529 case 0x06: /* B6CR */
530 break;
531 case 0x07: /* B7CR */
532 break;
533 case 0x10: /* B0AP */
534 break;
535 case 0x11: /* B1AP */
536 break;
537 case 0x12: /* B2AP */
538 break;
539 case 0x13: /* B3AP */
540 break;
541 case 0x14: /* B4AP */
542 break;
543 case 0x15: /* B5AP */
544 break;
545 case 0x16: /* B6AP */
546 break;
547 case 0x17: /* B7AP */
548 break;
549 case 0x20: /* BEAR */
550 break;
551 case 0x21: /* BESR0 */
552 break;
553 case 0x22: /* BESR1 */
554 break;
555 case 0x23: /* CFG */
556 break;
557 default:
558 break;
559 }
560 break;
561 default:
562 break;
563 }
564 }
565
566 static void ebc_reset (void *opaque)
567 {
568 ppc4xx_ebc_t *ebc;
569 int i;
570
571 ebc = opaque;
572 ebc->addr = 0x00000000;
573 ebc->bap[0] = 0x7F8FFE80;
574 ebc->bcr[0] = 0xFFE28000;
575 for (i = 0; i < 8; i++) {
576 ebc->bap[i] = 0x00000000;
577 ebc->bcr[i] = 0x00000000;
578 }
579 ebc->besr0 = 0x00000000;
580 ebc->besr1 = 0x00000000;
581 ebc->cfg = 0x80400000;
582 }
583
584 static void ppc405_ebc_init(CPUPPCState *env)
585 {
586 ppc4xx_ebc_t *ebc;
587
588 ebc = g_malloc0(sizeof(ppc4xx_ebc_t));
589 qemu_register_reset(&ebc_reset, ebc);
590 ppc_dcr_register(env, EBC0_CFGADDR,
591 ebc, &dcr_read_ebc, &dcr_write_ebc);
592 ppc_dcr_register(env, EBC0_CFGDATA,
593 ebc, &dcr_read_ebc, &dcr_write_ebc);
594 }
595
596 /*****************************************************************************/
597 /* DMA controller */
598 enum {
599 DMA0_CR0 = 0x100,
600 DMA0_CT0 = 0x101,
601 DMA0_DA0 = 0x102,
602 DMA0_SA0 = 0x103,
603 DMA0_SG0 = 0x104,
604 DMA0_CR1 = 0x108,
605 DMA0_CT1 = 0x109,
606 DMA0_DA1 = 0x10A,
607 DMA0_SA1 = 0x10B,
608 DMA0_SG1 = 0x10C,
609 DMA0_CR2 = 0x110,
610 DMA0_CT2 = 0x111,
611 DMA0_DA2 = 0x112,
612 DMA0_SA2 = 0x113,
613 DMA0_SG2 = 0x114,
614 DMA0_CR3 = 0x118,
615 DMA0_CT3 = 0x119,
616 DMA0_DA3 = 0x11A,
617 DMA0_SA3 = 0x11B,
618 DMA0_SG3 = 0x11C,
619 DMA0_SR = 0x120,
620 DMA0_SGC = 0x123,
621 DMA0_SLP = 0x125,
622 DMA0_POL = 0x126,
623 };
624
625 typedef struct ppc405_dma_t ppc405_dma_t;
626 struct ppc405_dma_t {
627 qemu_irq irqs[4];
628 uint32_t cr[4];
629 uint32_t ct[4];
630 uint32_t da[4];
631 uint32_t sa[4];
632 uint32_t sg[4];
633 uint32_t sr;
634 uint32_t sgc;
635 uint32_t slp;
636 uint32_t pol;
637 };
638
639 static uint32_t dcr_read_dma (void *opaque, int dcrn)
640 {
641 return 0;
642 }
643
644 static void dcr_write_dma (void *opaque, int dcrn, uint32_t val)
645 {
646 }
647
648 static void ppc405_dma_reset (void *opaque)
649 {
650 ppc405_dma_t *dma;
651 int i;
652
653 dma = opaque;
654 for (i = 0; i < 4; i++) {
655 dma->cr[i] = 0x00000000;
656 dma->ct[i] = 0x00000000;
657 dma->da[i] = 0x00000000;
658 dma->sa[i] = 0x00000000;
659 dma->sg[i] = 0x00000000;
660 }
661 dma->sr = 0x00000000;
662 dma->sgc = 0x00000000;
663 dma->slp = 0x7C000000;
664 dma->pol = 0x00000000;
665 }
666
667 static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4])
668 {
669 ppc405_dma_t *dma;
670
671 dma = g_malloc0(sizeof(ppc405_dma_t));
672 memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
673 qemu_register_reset(&ppc405_dma_reset, dma);
674 ppc_dcr_register(env, DMA0_CR0,
675 dma, &dcr_read_dma, &dcr_write_dma);
676 ppc_dcr_register(env, DMA0_CT0,
677 dma, &dcr_read_dma, &dcr_write_dma);
678 ppc_dcr_register(env, DMA0_DA0,
679 dma, &dcr_read_dma, &dcr_write_dma);
680 ppc_dcr_register(env, DMA0_SA0,
681 dma, &dcr_read_dma, &dcr_write_dma);
682 ppc_dcr_register(env, DMA0_SG0,
683 dma, &dcr_read_dma, &dcr_write_dma);
684 ppc_dcr_register(env, DMA0_CR1,
685 dma, &dcr_read_dma, &dcr_write_dma);
686 ppc_dcr_register(env, DMA0_CT1,
687 dma, &dcr_read_dma, &dcr_write_dma);
688 ppc_dcr_register(env, DMA0_DA1,
689 dma, &dcr_read_dma, &dcr_write_dma);
690 ppc_dcr_register(env, DMA0_SA1,
691 dma, &dcr_read_dma, &dcr_write_dma);
692 ppc_dcr_register(env, DMA0_SG1,
693 dma, &dcr_read_dma, &dcr_write_dma);
694 ppc_dcr_register(env, DMA0_CR2,
695 dma, &dcr_read_dma, &dcr_write_dma);
696 ppc_dcr_register(env, DMA0_CT2,
697 dma, &dcr_read_dma, &dcr_write_dma);
698 ppc_dcr_register(env, DMA0_DA2,
699 dma, &dcr_read_dma, &dcr_write_dma);
700 ppc_dcr_register(env, DMA0_SA2,
701 dma, &dcr_read_dma, &dcr_write_dma);
702 ppc_dcr_register(env, DMA0_SG2,
703 dma, &dcr_read_dma, &dcr_write_dma);
704 ppc_dcr_register(env, DMA0_CR3,
705 dma, &dcr_read_dma, &dcr_write_dma);
706 ppc_dcr_register(env, DMA0_CT3,
707 dma, &dcr_read_dma, &dcr_write_dma);
708 ppc_dcr_register(env, DMA0_DA3,
709 dma, &dcr_read_dma, &dcr_write_dma);
710 ppc_dcr_register(env, DMA0_SA3,
711 dma, &dcr_read_dma, &dcr_write_dma);
712 ppc_dcr_register(env, DMA0_SG3,
713 dma, &dcr_read_dma, &dcr_write_dma);
714 ppc_dcr_register(env, DMA0_SR,
715 dma, &dcr_read_dma, &dcr_write_dma);
716 ppc_dcr_register(env, DMA0_SGC,
717 dma, &dcr_read_dma, &dcr_write_dma);
718 ppc_dcr_register(env, DMA0_SLP,
719 dma, &dcr_read_dma, &dcr_write_dma);
720 ppc_dcr_register(env, DMA0_POL,
721 dma, &dcr_read_dma, &dcr_write_dma);
722 }
723
724 /*****************************************************************************/
725 /* GPIO */
726 typedef struct ppc405_gpio_t ppc405_gpio_t;
727 struct ppc405_gpio_t {
728 MemoryRegion io;
729 uint32_t or;
730 uint32_t tcr;
731 uint32_t osrh;
732 uint32_t osrl;
733 uint32_t tsrh;
734 uint32_t tsrl;
735 uint32_t odr;
736 uint32_t ir;
737 uint32_t rr1;
738 uint32_t isr1h;
739 uint32_t isr1l;
740 };
741
742 static uint32_t ppc405_gpio_readb (void *opaque, hwaddr addr)
743 {
744 #ifdef DEBUG_GPIO
745 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
746 #endif
747
748 return 0;
749 }
750
751 static void ppc405_gpio_writeb (void *opaque,
752 hwaddr addr, uint32_t value)
753 {
754 #ifdef DEBUG_GPIO
755 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
756 value);
757 #endif
758 }
759
760 static uint32_t ppc405_gpio_readw (void *opaque, hwaddr addr)
761 {
762 #ifdef DEBUG_GPIO
763 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
764 #endif
765
766 return 0;
767 }
768
769 static void ppc405_gpio_writew (void *opaque,
770 hwaddr addr, uint32_t value)
771 {
772 #ifdef DEBUG_GPIO
773 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
774 value);
775 #endif
776 }
777
778 static uint32_t ppc405_gpio_readl (void *opaque, hwaddr addr)
779 {
780 #ifdef DEBUG_GPIO
781 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
782 #endif
783
784 return 0;
785 }
786
787 static void ppc405_gpio_writel (void *opaque,
788 hwaddr addr, uint32_t value)
789 {
790 #ifdef DEBUG_GPIO
791 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
792 value);
793 #endif
794 }
795
796 static const MemoryRegionOps ppc405_gpio_ops = {
797 .old_mmio = {
798 .read = { ppc405_gpio_readb, ppc405_gpio_readw, ppc405_gpio_readl, },
799 .write = { ppc405_gpio_writeb, ppc405_gpio_writew, ppc405_gpio_writel, },
800 },
801 .endianness = DEVICE_NATIVE_ENDIAN,
802 };
803
804 static void ppc405_gpio_reset (void *opaque)
805 {
806 }
807
808 static void ppc405_gpio_init(hwaddr base)
809 {
810 ppc405_gpio_t *gpio;
811
812 gpio = g_malloc0(sizeof(ppc405_gpio_t));
813 #ifdef DEBUG_GPIO
814 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
815 #endif
816 memory_region_init_io(&gpio->io, NULL, &ppc405_gpio_ops, gpio, "pgio", 0x038);
817 memory_region_add_subregion(get_system_memory(), base, &gpio->io);
818 qemu_register_reset(&ppc405_gpio_reset, gpio);
819 }
820
821 /*****************************************************************************/
822 /* On Chip Memory */
823 enum {
824 OCM0_ISARC = 0x018,
825 OCM0_ISACNTL = 0x019,
826 OCM0_DSARC = 0x01A,
827 OCM0_DSACNTL = 0x01B,
828 };
829
830 typedef struct ppc405_ocm_t ppc405_ocm_t;
831 struct ppc405_ocm_t {
832 MemoryRegion ram;
833 MemoryRegion isarc_ram;
834 MemoryRegion dsarc_ram;
835 uint32_t isarc;
836 uint32_t isacntl;
837 uint32_t dsarc;
838 uint32_t dsacntl;
839 };
840
841 static void ocm_update_mappings (ppc405_ocm_t *ocm,
842 uint32_t isarc, uint32_t isacntl,
843 uint32_t dsarc, uint32_t dsacntl)
844 {
845 #ifdef DEBUG_OCM
846 printf("OCM update ISA %08" PRIx32 " %08" PRIx32 " (%08" PRIx32
847 " %08" PRIx32 ") DSA %08" PRIx32 " %08" PRIx32
848 " (%08" PRIx32 " %08" PRIx32 ")\n",
849 isarc, isacntl, dsarc, dsacntl,
850 ocm->isarc, ocm->isacntl, ocm->dsarc, ocm->dsacntl);
851 #endif
852 if (ocm->isarc != isarc ||
853 (ocm->isacntl & 0x80000000) != (isacntl & 0x80000000)) {
854 if (ocm->isacntl & 0x80000000) {
855 /* Unmap previously assigned memory region */
856 printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);
857 memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram);
858 }
859 if (isacntl & 0x80000000) {
860 /* Map new instruction memory region */
861 #ifdef DEBUG_OCM
862 printf("OCM map ISA %08" PRIx32 "\n", isarc);
863 #endif
864 memory_region_add_subregion(get_system_memory(), isarc,
865 &ocm->isarc_ram);
866 }
867 }
868 if (ocm->dsarc != dsarc ||
869 (ocm->dsacntl & 0x80000000) != (dsacntl & 0x80000000)) {
870 if (ocm->dsacntl & 0x80000000) {
871 /* Beware not to unmap the region we just mapped */
872 if (!(isacntl & 0x80000000) || ocm->dsarc != isarc) {
873 /* Unmap previously assigned memory region */
874 #ifdef DEBUG_OCM
875 printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);
876 #endif
877 memory_region_del_subregion(get_system_memory(),
878 &ocm->dsarc_ram);
879 }
880 }
881 if (dsacntl & 0x80000000) {
882 /* Beware not to remap the region we just mapped */
883 if (!(isacntl & 0x80000000) || dsarc != isarc) {
884 /* Map new data memory region */
885 #ifdef DEBUG_OCM
886 printf("OCM map DSA %08" PRIx32 "\n", dsarc);
887 #endif
888 memory_region_add_subregion(get_system_memory(), dsarc,
889 &ocm->dsarc_ram);
890 }
891 }
892 }
893 }
894
895 static uint32_t dcr_read_ocm (void *opaque, int dcrn)
896 {
897 ppc405_ocm_t *ocm;
898 uint32_t ret;
899
900 ocm = opaque;
901 switch (dcrn) {
902 case OCM0_ISARC:
903 ret = ocm->isarc;
904 break;
905 case OCM0_ISACNTL:
906 ret = ocm->isacntl;
907 break;
908 case OCM0_DSARC:
909 ret = ocm->dsarc;
910 break;
911 case OCM0_DSACNTL:
912 ret = ocm->dsacntl;
913 break;
914 default:
915 ret = 0;
916 break;
917 }
918
919 return ret;
920 }
921
922 static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
923 {
924 ppc405_ocm_t *ocm;
925 uint32_t isarc, dsarc, isacntl, dsacntl;
926
927 ocm = opaque;
928 isarc = ocm->isarc;
929 dsarc = ocm->dsarc;
930 isacntl = ocm->isacntl;
931 dsacntl = ocm->dsacntl;
932 switch (dcrn) {
933 case OCM0_ISARC:
934 isarc = val & 0xFC000000;
935 break;
936 case OCM0_ISACNTL:
937 isacntl = val & 0xC0000000;
938 break;
939 case OCM0_DSARC:
940 isarc = val & 0xFC000000;
941 break;
942 case OCM0_DSACNTL:
943 isacntl = val & 0xC0000000;
944 break;
945 }
946 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
947 ocm->isarc = isarc;
948 ocm->dsarc = dsarc;
949 ocm->isacntl = isacntl;
950 ocm->dsacntl = dsacntl;
951 }
952
953 static void ocm_reset (void *opaque)
954 {
955 ppc405_ocm_t *ocm;
956 uint32_t isarc, dsarc, isacntl, dsacntl;
957
958 ocm = opaque;
959 isarc = 0x00000000;
960 isacntl = 0x00000000;
961 dsarc = 0x00000000;
962 dsacntl = 0x00000000;
963 ocm_update_mappings(ocm, isarc, isacntl, dsarc, dsacntl);
964 ocm->isarc = isarc;
965 ocm->dsarc = dsarc;
966 ocm->isacntl = isacntl;
967 ocm->dsacntl = dsacntl;
968 }
969
970 static void ppc405_ocm_init(CPUPPCState *env)
971 {
972 ppc405_ocm_t *ocm;
973
974 ocm = g_malloc0(sizeof(ppc405_ocm_t));
975 /* XXX: Size is 4096 or 0x04000000 */
976 memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4096);
977 vmstate_register_ram_global(&ocm->isarc_ram);
978 memory_region_init_alias(&ocm->dsarc_ram, NULL, "ppc405.dsarc", &ocm->isarc_ram,
979 0, 4096);
980 qemu_register_reset(&ocm_reset, ocm);
981 ppc_dcr_register(env, OCM0_ISARC,
982 ocm, &dcr_read_ocm, &dcr_write_ocm);
983 ppc_dcr_register(env, OCM0_ISACNTL,
984 ocm, &dcr_read_ocm, &dcr_write_ocm);
985 ppc_dcr_register(env, OCM0_DSARC,
986 ocm, &dcr_read_ocm, &dcr_write_ocm);
987 ppc_dcr_register(env, OCM0_DSACNTL,
988 ocm, &dcr_read_ocm, &dcr_write_ocm);
989 }
990
991 /*****************************************************************************/
992 /* I2C controller */
993 typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
994 struct ppc4xx_i2c_t {
995 qemu_irq irq;
996 MemoryRegion iomem;
997 uint8_t mdata;
998 uint8_t lmadr;
999 uint8_t hmadr;
1000 uint8_t cntl;
1001 uint8_t mdcntl;
1002 uint8_t sts;
1003 uint8_t extsts;
1004 uint8_t sdata;
1005 uint8_t lsadr;
1006 uint8_t hsadr;
1007 uint8_t clkdiv;
1008 uint8_t intrmsk;
1009 uint8_t xfrcnt;
1010 uint8_t xtcntlss;
1011 uint8_t directcntl;
1012 };
1013
1014 static uint32_t ppc4xx_i2c_readb (void *opaque, hwaddr addr)
1015 {
1016 ppc4xx_i2c_t *i2c;
1017 uint32_t ret;
1018
1019 #ifdef DEBUG_I2C
1020 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1021 #endif
1022 i2c = opaque;
1023 switch (addr) {
1024 case 0x00:
1025 // i2c_readbyte(&i2c->mdata);
1026 ret = i2c->mdata;
1027 break;
1028 case 0x02:
1029 ret = i2c->sdata;
1030 break;
1031 case 0x04:
1032 ret = i2c->lmadr;
1033 break;
1034 case 0x05:
1035 ret = i2c->hmadr;
1036 break;
1037 case 0x06:
1038 ret = i2c->cntl;
1039 break;
1040 case 0x07:
1041 ret = i2c->mdcntl;
1042 break;
1043 case 0x08:
1044 ret = i2c->sts;
1045 break;
1046 case 0x09:
1047 ret = i2c->extsts;
1048 break;
1049 case 0x0A:
1050 ret = i2c->lsadr;
1051 break;
1052 case 0x0B:
1053 ret = i2c->hsadr;
1054 break;
1055 case 0x0C:
1056 ret = i2c->clkdiv;
1057 break;
1058 case 0x0D:
1059 ret = i2c->intrmsk;
1060 break;
1061 case 0x0E:
1062 ret = i2c->xfrcnt;
1063 break;
1064 case 0x0F:
1065 ret = i2c->xtcntlss;
1066 break;
1067 case 0x10:
1068 ret = i2c->directcntl;
1069 break;
1070 default:
1071 ret = 0x00;
1072 break;
1073 }
1074 #ifdef DEBUG_I2C
1075 printf("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, addr, ret);
1076 #endif
1077
1078 return ret;
1079 }
1080
1081 static void ppc4xx_i2c_writeb (void *opaque,
1082 hwaddr addr, uint32_t value)
1083 {
1084 ppc4xx_i2c_t *i2c;
1085
1086 #ifdef DEBUG_I2C
1087 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1088 value);
1089 #endif
1090 i2c = opaque;
1091 switch (addr) {
1092 case 0x00:
1093 i2c->mdata = value;
1094 // i2c_sendbyte(&i2c->mdata);
1095 break;
1096 case 0x02:
1097 i2c->sdata = value;
1098 break;
1099 case 0x04:
1100 i2c->lmadr = value;
1101 break;
1102 case 0x05:
1103 i2c->hmadr = value;
1104 break;
1105 case 0x06:
1106 i2c->cntl = value;
1107 break;
1108 case 0x07:
1109 i2c->mdcntl = value & 0xDF;
1110 break;
1111 case 0x08:
1112 i2c->sts &= ~(value & 0x0A);
1113 break;
1114 case 0x09:
1115 i2c->extsts &= ~(value & 0x8F);
1116 break;
1117 case 0x0A:
1118 i2c->lsadr = value;
1119 break;
1120 case 0x0B:
1121 i2c->hsadr = value;
1122 break;
1123 case 0x0C:
1124 i2c->clkdiv = value;
1125 break;
1126 case 0x0D:
1127 i2c->intrmsk = value;
1128 break;
1129 case 0x0E:
1130 i2c->xfrcnt = value & 0x77;
1131 break;
1132 case 0x0F:
1133 i2c->xtcntlss = value;
1134 break;
1135 case 0x10:
1136 i2c->directcntl = value & 0x7;
1137 break;
1138 }
1139 }
1140
1141 static uint32_t ppc4xx_i2c_readw (void *opaque, hwaddr addr)
1142 {
1143 uint32_t ret;
1144
1145 #ifdef DEBUG_I2C
1146 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1147 #endif
1148 ret = ppc4xx_i2c_readb(opaque, addr) << 8;
1149 ret |= ppc4xx_i2c_readb(opaque, addr + 1);
1150
1151 return ret;
1152 }
1153
1154 static void ppc4xx_i2c_writew (void *opaque,
1155 hwaddr addr, uint32_t value)
1156 {
1157 #ifdef DEBUG_I2C
1158 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1159 value);
1160 #endif
1161 ppc4xx_i2c_writeb(opaque, addr, value >> 8);
1162 ppc4xx_i2c_writeb(opaque, addr + 1, value);
1163 }
1164
1165 static uint32_t ppc4xx_i2c_readl (void *opaque, hwaddr addr)
1166 {
1167 uint32_t ret;
1168
1169 #ifdef DEBUG_I2C
1170 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1171 #endif
1172 ret = ppc4xx_i2c_readb(opaque, addr) << 24;
1173 ret |= ppc4xx_i2c_readb(opaque, addr + 1) << 16;
1174 ret |= ppc4xx_i2c_readb(opaque, addr + 2) << 8;
1175 ret |= ppc4xx_i2c_readb(opaque, addr + 3);
1176
1177 return ret;
1178 }
1179
1180 static void ppc4xx_i2c_writel (void *opaque,
1181 hwaddr addr, uint32_t value)
1182 {
1183 #ifdef DEBUG_I2C
1184 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1185 value);
1186 #endif
1187 ppc4xx_i2c_writeb(opaque, addr, value >> 24);
1188 ppc4xx_i2c_writeb(opaque, addr + 1, value >> 16);
1189 ppc4xx_i2c_writeb(opaque, addr + 2, value >> 8);
1190 ppc4xx_i2c_writeb(opaque, addr + 3, value);
1191 }
1192
1193 static const MemoryRegionOps i2c_ops = {
1194 .old_mmio = {
1195 .read = { ppc4xx_i2c_readb, ppc4xx_i2c_readw, ppc4xx_i2c_readl, },
1196 .write = { ppc4xx_i2c_writeb, ppc4xx_i2c_writew, ppc4xx_i2c_writel, },
1197 },
1198 .endianness = DEVICE_NATIVE_ENDIAN,
1199 };
1200
1201 static void ppc4xx_i2c_reset (void *opaque)
1202 {
1203 ppc4xx_i2c_t *i2c;
1204
1205 i2c = opaque;
1206 i2c->mdata = 0x00;
1207 i2c->sdata = 0x00;
1208 i2c->cntl = 0x00;
1209 i2c->mdcntl = 0x00;
1210 i2c->sts = 0x00;
1211 i2c->extsts = 0x00;
1212 i2c->clkdiv = 0x00;
1213 i2c->xfrcnt = 0x00;
1214 i2c->directcntl = 0x0F;
1215 }
1216
1217 static void ppc405_i2c_init(hwaddr base, qemu_irq irq)
1218 {
1219 ppc4xx_i2c_t *i2c;
1220
1221 i2c = g_malloc0(sizeof(ppc4xx_i2c_t));
1222 i2c->irq = irq;
1223 #ifdef DEBUG_I2C
1224 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
1225 #endif
1226 memory_region_init_io(&i2c->iomem, NULL, &i2c_ops, i2c, "i2c", 0x011);
1227 memory_region_add_subregion(get_system_memory(), base, &i2c->iomem);
1228 qemu_register_reset(ppc4xx_i2c_reset, i2c);
1229 }
1230
1231 /*****************************************************************************/
1232 /* General purpose timers */
1233 typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
1234 struct ppc4xx_gpt_t {
1235 MemoryRegion iomem;
1236 int64_t tb_offset;
1237 uint32_t tb_freq;
1238 QEMUTimer *timer;
1239 qemu_irq irqs[5];
1240 uint32_t oe;
1241 uint32_t ol;
1242 uint32_t im;
1243 uint32_t is;
1244 uint32_t ie;
1245 uint32_t comp[5];
1246 uint32_t mask[5];
1247 };
1248
1249 static uint32_t ppc4xx_gpt_readb (void *opaque, hwaddr addr)
1250 {
1251 #ifdef DEBUG_GPT
1252 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1253 #endif
1254 /* XXX: generate a bus fault */
1255 return -1;
1256 }
1257
1258 static void ppc4xx_gpt_writeb (void *opaque,
1259 hwaddr addr, uint32_t value)
1260 {
1261 #ifdef DEBUG_I2C
1262 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1263 value);
1264 #endif
1265 /* XXX: generate a bus fault */
1266 }
1267
1268 static uint32_t ppc4xx_gpt_readw (void *opaque, hwaddr addr)
1269 {
1270 #ifdef DEBUG_GPT
1271 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1272 #endif
1273 /* XXX: generate a bus fault */
1274 return -1;
1275 }
1276
1277 static void ppc4xx_gpt_writew (void *opaque,
1278 hwaddr addr, uint32_t value)
1279 {
1280 #ifdef DEBUG_I2C
1281 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1282 value);
1283 #endif
1284 /* XXX: generate a bus fault */
1285 }
1286
1287 static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
1288 {
1289 /* XXX: TODO */
1290 return 0;
1291 }
1292
1293 static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
1294 {
1295 /* XXX: TODO */
1296 }
1297
1298 static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
1299 {
1300 uint32_t mask;
1301 int i;
1302
1303 mask = 0x80000000;
1304 for (i = 0; i < 5; i++) {
1305 if (gpt->oe & mask) {
1306 /* Output is enabled */
1307 if (ppc4xx_gpt_compare(gpt, i)) {
1308 /* Comparison is OK */
1309 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask);
1310 } else {
1311 /* Comparison is KO */
1312 ppc4xx_gpt_set_output(gpt, i, gpt->ol & mask ? 0 : 1);
1313 }
1314 }
1315 mask = mask >> 1;
1316 }
1317 }
1318
1319 static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
1320 {
1321 uint32_t mask;
1322 int i;
1323
1324 mask = 0x00008000;
1325 for (i = 0; i < 5; i++) {
1326 if (gpt->is & gpt->im & mask)
1327 qemu_irq_raise(gpt->irqs[i]);
1328 else
1329 qemu_irq_lower(gpt->irqs[i]);
1330 mask = mask >> 1;
1331 }
1332 }
1333
1334 static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
1335 {
1336 /* XXX: TODO */
1337 }
1338
1339 static uint32_t ppc4xx_gpt_readl (void *opaque, hwaddr addr)
1340 {
1341 ppc4xx_gpt_t *gpt;
1342 uint32_t ret;
1343 int idx;
1344
1345 #ifdef DEBUG_GPT
1346 printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
1347 #endif
1348 gpt = opaque;
1349 switch (addr) {
1350 case 0x00:
1351 /* Time base counter */
1352 ret = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + gpt->tb_offset,
1353 gpt->tb_freq, get_ticks_per_sec());
1354 break;
1355 case 0x10:
1356 /* Output enable */
1357 ret = gpt->oe;
1358 break;
1359 case 0x14:
1360 /* Output level */
1361 ret = gpt->ol;
1362 break;
1363 case 0x18:
1364 /* Interrupt mask */
1365 ret = gpt->im;
1366 break;
1367 case 0x1C:
1368 case 0x20:
1369 /* Interrupt status */
1370 ret = gpt->is;
1371 break;
1372 case 0x24:
1373 /* Interrupt enable */
1374 ret = gpt->ie;
1375 break;
1376 case 0x80 ... 0x90:
1377 /* Compare timer */
1378 idx = (addr - 0x80) >> 2;
1379 ret = gpt->comp[idx];
1380 break;
1381 case 0xC0 ... 0xD0:
1382 /* Compare mask */
1383 idx = (addr - 0xC0) >> 2;
1384 ret = gpt->mask[idx];
1385 break;
1386 default:
1387 ret = -1;
1388 break;
1389 }
1390
1391 return ret;
1392 }
1393
1394 static void ppc4xx_gpt_writel (void *opaque,
1395 hwaddr addr, uint32_t value)
1396 {
1397 ppc4xx_gpt_t *gpt;
1398 int idx;
1399
1400 #ifdef DEBUG_I2C
1401 printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
1402 value);
1403 #endif
1404 gpt = opaque;
1405 switch (addr) {
1406 case 0x00:
1407 /* Time base counter */
1408 gpt->tb_offset = muldiv64(value, get_ticks_per_sec(), gpt->tb_freq)
1409 - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1410 ppc4xx_gpt_compute_timer(gpt);
1411 break;
1412 case 0x10:
1413 /* Output enable */
1414 gpt->oe = value & 0xF8000000;
1415 ppc4xx_gpt_set_outputs(gpt);
1416 break;
1417 case 0x14:
1418 /* Output level */
1419 gpt->ol = value & 0xF8000000;
1420 ppc4xx_gpt_set_outputs(gpt);
1421 break;
1422 case 0x18:
1423 /* Interrupt mask */
1424 gpt->im = value & 0x0000F800;
1425 break;
1426 case 0x1C:
1427 /* Interrupt status set */
1428 gpt->is |= value & 0x0000F800;
1429 ppc4xx_gpt_set_irqs(gpt);
1430 break;
1431 case 0x20:
1432 /* Interrupt status clear */
1433 gpt->is &= ~(value & 0x0000F800);
1434 ppc4xx_gpt_set_irqs(gpt);
1435 break;
1436 case 0x24:
1437 /* Interrupt enable */
1438 gpt->ie = value & 0x0000F800;
1439 ppc4xx_gpt_set_irqs(gpt);
1440 break;
1441 case 0x80 ... 0x90:
1442 /* Compare timer */
1443 idx = (addr - 0x80) >> 2;
1444 gpt->comp[idx] = value & 0xF8000000;
1445 ppc4xx_gpt_compute_timer(gpt);
1446 break;
1447 case 0xC0 ... 0xD0:
1448 /* Compare mask */
1449 idx = (addr - 0xC0) >> 2;
1450 gpt->mask[idx] = value & 0xF8000000;
1451 ppc4xx_gpt_compute_timer(gpt);
1452 break;
1453 }
1454 }
1455
1456 static const MemoryRegionOps gpt_ops = {
1457 .old_mmio = {
1458 .read = { ppc4xx_gpt_readb, ppc4xx_gpt_readw, ppc4xx_gpt_readl, },
1459 .write = { ppc4xx_gpt_writeb, ppc4xx_gpt_writew, ppc4xx_gpt_writel, },
1460 },
1461 .endianness = DEVICE_NATIVE_ENDIAN,
1462 };
1463
1464 static void ppc4xx_gpt_cb (void *opaque)
1465 {
1466 ppc4xx_gpt_t *gpt;
1467
1468 gpt = opaque;
1469 ppc4xx_gpt_set_irqs(gpt);
1470 ppc4xx_gpt_set_outputs(gpt);
1471 ppc4xx_gpt_compute_timer(gpt);
1472 }
1473
1474 static void ppc4xx_gpt_reset (void *opaque)
1475 {
1476 ppc4xx_gpt_t *gpt;
1477 int i;
1478
1479 gpt = opaque;
1480 timer_del(gpt->timer);
1481 gpt->oe = 0x00000000;
1482 gpt->ol = 0x00000000;
1483 gpt->im = 0x00000000;
1484 gpt->is = 0x00000000;
1485 gpt->ie = 0x00000000;
1486 for (i = 0; i < 5; i++) {
1487 gpt->comp[i] = 0x00000000;
1488 gpt->mask[i] = 0x00000000;
1489 }
1490 }
1491
1492 static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5])
1493 {
1494 ppc4xx_gpt_t *gpt;
1495 int i;
1496
1497 gpt = g_malloc0(sizeof(ppc4xx_gpt_t));
1498 for (i = 0; i < 5; i++) {
1499 gpt->irqs[i] = irqs[i];
1500 }
1501 gpt->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &ppc4xx_gpt_cb, gpt);
1502 #ifdef DEBUG_GPT
1503 printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
1504 #endif
1505 memory_region_init_io(&gpt->iomem, NULL, &gpt_ops, gpt, "gpt", 0x0d4);
1506 memory_region_add_subregion(get_system_memory(), base, &gpt->iomem);
1507 qemu_register_reset(ppc4xx_gpt_reset, gpt);
1508 }
1509
1510 /*****************************************************************************/
1511 /* MAL */
1512 enum {
1513 MAL0_CFG = 0x180,
1514 MAL0_ESR = 0x181,
1515 MAL0_IER = 0x182,
1516 MAL0_TXCASR = 0x184,
1517 MAL0_TXCARR = 0x185,
1518 MAL0_TXEOBISR = 0x186,
1519 MAL0_TXDEIR = 0x187,
1520 MAL0_RXCASR = 0x190,
1521 MAL0_RXCARR = 0x191,
1522 MAL0_RXEOBISR = 0x192,
1523 MAL0_RXDEIR = 0x193,
1524 MAL0_TXCTP0R = 0x1A0,
1525 MAL0_TXCTP1R = 0x1A1,
1526 MAL0_TXCTP2R = 0x1A2,
1527 MAL0_TXCTP3R = 0x1A3,
1528 MAL0_RXCTP0R = 0x1C0,
1529 MAL0_RXCTP1R = 0x1C1,
1530 MAL0_RCBS0 = 0x1E0,
1531 MAL0_RCBS1 = 0x1E1,
1532 };
1533
1534 typedef struct ppc40x_mal_t ppc40x_mal_t;
1535 struct ppc40x_mal_t {
1536 qemu_irq irqs[4];
1537 uint32_t cfg;
1538 uint32_t esr;
1539 uint32_t ier;
1540 uint32_t txcasr;
1541 uint32_t txcarr;
1542 uint32_t txeobisr;
1543 uint32_t txdeir;
1544 uint32_t rxcasr;
1545 uint32_t rxcarr;
1546 uint32_t rxeobisr;
1547 uint32_t rxdeir;
1548 uint32_t txctpr[4];
1549 uint32_t rxctpr[2];
1550 uint32_t rcbs[2];
1551 };
1552
1553 static void ppc40x_mal_reset (void *opaque);
1554
1555 static uint32_t dcr_read_mal (void *opaque, int dcrn)
1556 {
1557 ppc40x_mal_t *mal;
1558 uint32_t ret;
1559
1560 mal = opaque;
1561 switch (dcrn) {
1562 case MAL0_CFG:
1563 ret = mal->cfg;
1564 break;
1565 case MAL0_ESR:
1566 ret = mal->esr;
1567 break;
1568 case MAL0_IER:
1569 ret = mal->ier;
1570 break;
1571 case MAL0_TXCASR:
1572 ret = mal->txcasr;
1573 break;
1574 case MAL0_TXCARR:
1575 ret = mal->txcarr;
1576 break;
1577 case MAL0_TXEOBISR:
1578 ret = mal->txeobisr;
1579 break;
1580 case MAL0_TXDEIR:
1581 ret = mal->txdeir;
1582 break;
1583 case MAL0_RXCASR:
1584 ret = mal->rxcasr;
1585 break;
1586 case MAL0_RXCARR:
1587 ret = mal->rxcarr;
1588 break;
1589 case MAL0_RXEOBISR:
1590 ret = mal->rxeobisr;
1591 break;
1592 case MAL0_RXDEIR:
1593 ret = mal->rxdeir;
1594 break;
1595 case MAL0_TXCTP0R:
1596 ret = mal->txctpr[0];
1597 break;
1598 case MAL0_TXCTP1R:
1599 ret = mal->txctpr[1];
1600 break;
1601 case MAL0_TXCTP2R:
1602 ret = mal->txctpr[2];
1603 break;
1604 case MAL0_TXCTP3R:
1605 ret = mal->txctpr[3];
1606 break;
1607 case MAL0_RXCTP0R:
1608 ret = mal->rxctpr[0];
1609 break;
1610 case MAL0_RXCTP1R:
1611 ret = mal->rxctpr[1];
1612 break;
1613 case MAL0_RCBS0:
1614 ret = mal->rcbs[0];
1615 break;
1616 case MAL0_RCBS1:
1617 ret = mal->rcbs[1];
1618 break;
1619 default:
1620 ret = 0;
1621 break;
1622 }
1623
1624 return ret;
1625 }
1626
1627 static void dcr_write_mal (void *opaque, int dcrn, uint32_t val)
1628 {
1629 ppc40x_mal_t *mal;
1630 int idx;
1631
1632 mal = opaque;
1633 switch (dcrn) {
1634 case MAL0_CFG:
1635 if (val & 0x80000000)
1636 ppc40x_mal_reset(mal);
1637 mal->cfg = val & 0x00FFC087;
1638 break;
1639 case MAL0_ESR:
1640 /* Read/clear */
1641 mal->esr &= ~val;
1642 break;
1643 case MAL0_IER:
1644 mal->ier = val & 0x0000001F;
1645 break;
1646 case MAL0_TXCASR:
1647 mal->txcasr = val & 0xF0000000;
1648 break;
1649 case MAL0_TXCARR:
1650 mal->txcarr = val & 0xF0000000;
1651 break;
1652 case MAL0_TXEOBISR:
1653 /* Read/clear */
1654 mal->txeobisr &= ~val;
1655 break;
1656 case MAL0_TXDEIR:
1657 /* Read/clear */
1658 mal->txdeir &= ~val;
1659 break;
1660 case MAL0_RXCASR:
1661 mal->rxcasr = val & 0xC0000000;
1662 break;
1663 case MAL0_RXCARR:
1664 mal->rxcarr = val & 0xC0000000;
1665 break;
1666 case MAL0_RXEOBISR:
1667 /* Read/clear */
1668 mal->rxeobisr &= ~val;
1669 break;
1670 case MAL0_RXDEIR:
1671 /* Read/clear */
1672 mal->rxdeir &= ~val;
1673 break;
1674 case MAL0_TXCTP0R:
1675 idx = 0;
1676 goto update_tx_ptr;
1677 case MAL0_TXCTP1R:
1678 idx = 1;
1679 goto update_tx_ptr;
1680 case MAL0_TXCTP2R:
1681 idx = 2;
1682 goto update_tx_ptr;
1683 case MAL0_TXCTP3R:
1684 idx = 3;
1685 update_tx_ptr:
1686 mal->txctpr[idx] = val;
1687 break;
1688 case MAL0_RXCTP0R:
1689 idx = 0;
1690 goto update_rx_ptr;
1691 case MAL0_RXCTP1R:
1692 idx = 1;
1693 update_rx_ptr:
1694 mal->rxctpr[idx] = val;
1695 break;
1696 case MAL0_RCBS0:
1697 idx = 0;
1698 goto update_rx_size;
1699 case MAL0_RCBS1:
1700 idx = 1;
1701 update_rx_size:
1702 mal->rcbs[idx] = val & 0x000000FF;
1703 break;
1704 }
1705 }
1706
1707 static void ppc40x_mal_reset (void *opaque)
1708 {
1709 ppc40x_mal_t *mal;
1710
1711 mal = opaque;
1712 mal->cfg = 0x0007C000;
1713 mal->esr = 0x00000000;
1714 mal->ier = 0x00000000;
1715 mal->rxcasr = 0x00000000;
1716 mal->rxdeir = 0x00000000;
1717 mal->rxeobisr = 0x00000000;
1718 mal->txcasr = 0x00000000;
1719 mal->txdeir = 0x00000000;
1720 mal->txeobisr = 0x00000000;
1721 }
1722
1723 static void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4])
1724 {
1725 ppc40x_mal_t *mal;
1726 int i;
1727
1728 mal = g_malloc0(sizeof(ppc40x_mal_t));
1729 for (i = 0; i < 4; i++)
1730 mal->irqs[i] = irqs[i];
1731 qemu_register_reset(&ppc40x_mal_reset, mal);
1732 ppc_dcr_register(env, MAL0_CFG,
1733 mal, &dcr_read_mal, &dcr_write_mal);
1734 ppc_dcr_register(env, MAL0_ESR,
1735 mal, &dcr_read_mal, &dcr_write_mal);
1736 ppc_dcr_register(env, MAL0_IER,
1737 mal, &dcr_read_mal, &dcr_write_mal);
1738 ppc_dcr_register(env, MAL0_TXCASR,
1739 mal, &dcr_read_mal, &dcr_write_mal);
1740 ppc_dcr_register(env, MAL0_TXCARR,
1741 mal, &dcr_read_mal, &dcr_write_mal);
1742 ppc_dcr_register(env, MAL0_TXEOBISR,
1743 mal, &dcr_read_mal, &dcr_write_mal);
1744 ppc_dcr_register(env, MAL0_TXDEIR,
1745 mal, &dcr_read_mal, &dcr_write_mal);
1746 ppc_dcr_register(env, MAL0_RXCASR,
1747 mal, &dcr_read_mal, &dcr_write_mal);
1748 ppc_dcr_register(env, MAL0_RXCARR,
1749 mal, &dcr_read_mal, &dcr_write_mal);
1750 ppc_dcr_register(env, MAL0_RXEOBISR,
1751 mal, &dcr_read_mal, &dcr_write_mal);
1752 ppc_dcr_register(env, MAL0_RXDEIR,
1753 mal, &dcr_read_mal, &dcr_write_mal);
1754 ppc_dcr_register(env, MAL0_TXCTP0R,
1755 mal, &dcr_read_mal, &dcr_write_mal);
1756 ppc_dcr_register(env, MAL0_TXCTP1R,
1757 mal, &dcr_read_mal, &dcr_write_mal);
1758 ppc_dcr_register(env, MAL0_TXCTP2R,
1759 mal, &dcr_read_mal, &dcr_write_mal);
1760 ppc_dcr_register(env, MAL0_TXCTP3R,
1761 mal, &dcr_read_mal, &dcr_write_mal);
1762 ppc_dcr_register(env, MAL0_RXCTP0R,
1763 mal, &dcr_read_mal, &dcr_write_mal);
1764 ppc_dcr_register(env, MAL0_RXCTP1R,
1765 mal, &dcr_read_mal, &dcr_write_mal);
1766 ppc_dcr_register(env, MAL0_RCBS0,
1767 mal, &dcr_read_mal, &dcr_write_mal);
1768 ppc_dcr_register(env, MAL0_RCBS1,
1769 mal, &dcr_read_mal, &dcr_write_mal);
1770 }
1771
1772 /*****************************************************************************/
1773 /* SPR */
1774 void ppc40x_core_reset(PowerPCCPU *cpu)
1775 {
1776 CPUPPCState *env = &cpu->env;
1777 target_ulong dbsr;
1778
1779 printf("Reset PowerPC core\n");
1780 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET);
1781 dbsr = env->spr[SPR_40x_DBSR];
1782 dbsr &= ~0x00000300;
1783 dbsr |= 0x00000100;
1784 env->spr[SPR_40x_DBSR] = dbsr;
1785 }
1786
1787 void ppc40x_chip_reset(PowerPCCPU *cpu)
1788 {
1789 CPUPPCState *env = &cpu->env;
1790 target_ulong dbsr;
1791
1792 printf("Reset PowerPC chip\n");
1793 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET);
1794 /* XXX: TODO reset all internal peripherals */
1795 dbsr = env->spr[SPR_40x_DBSR];
1796 dbsr &= ~0x00000300;
1797 dbsr |= 0x00000200;
1798 env->spr[SPR_40x_DBSR] = dbsr;
1799 }
1800
1801 void ppc40x_system_reset(PowerPCCPU *cpu)
1802 {
1803 printf("Reset PowerPC system\n");
1804 qemu_system_reset_request();
1805 }
1806
1807 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val)
1808 {
1809 PowerPCCPU *cpu = ppc_env_get_cpu(env);
1810
1811 switch ((val >> 28) & 0x3) {
1812 case 0x0:
1813 /* No action */
1814 break;
1815 case 0x1:
1816 /* Core reset */
1817 ppc40x_core_reset(cpu);
1818 break;
1819 case 0x2:
1820 /* Chip reset */
1821 ppc40x_chip_reset(cpu);
1822 break;
1823 case 0x3:
1824 /* System reset */
1825 ppc40x_system_reset(cpu);
1826 break;
1827 }
1828 }
1829
1830 /*****************************************************************************/
1831 /* PowerPC 405CR */
1832 enum {
1833 PPC405CR_CPC0_PLLMR = 0x0B0,
1834 PPC405CR_CPC0_CR0 = 0x0B1,
1835 PPC405CR_CPC0_CR1 = 0x0B2,
1836 PPC405CR_CPC0_PSR = 0x0B4,
1837 PPC405CR_CPC0_JTAGID = 0x0B5,
1838 PPC405CR_CPC0_ER = 0x0B9,
1839 PPC405CR_CPC0_FR = 0x0BA,
1840 PPC405CR_CPC0_SR = 0x0BB,
1841 };
1842
1843 enum {
1844 PPC405CR_CPU_CLK = 0,
1845 PPC405CR_TMR_CLK = 1,
1846 PPC405CR_PLB_CLK = 2,
1847 PPC405CR_SDRAM_CLK = 3,
1848 PPC405CR_OPB_CLK = 4,
1849 PPC405CR_EXT_CLK = 5,
1850 PPC405CR_UART_CLK = 6,
1851 PPC405CR_CLK_NB = 7,
1852 };
1853
1854 typedef struct ppc405cr_cpc_t ppc405cr_cpc_t;
1855 struct ppc405cr_cpc_t {
1856 clk_setup_t clk_setup[PPC405CR_CLK_NB];
1857 uint32_t sysclk;
1858 uint32_t psr;
1859 uint32_t cr0;
1860 uint32_t cr1;
1861 uint32_t jtagid;
1862 uint32_t pllmr;
1863 uint32_t er;
1864 uint32_t fr;
1865 };
1866
1867 static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc)
1868 {
1869 uint64_t VCO_out, PLL_out;
1870 uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk;
1871 int M, D0, D1, D2;
1872
1873 D0 = ((cpc->pllmr >> 26) & 0x3) + 1; /* CBDV */
1874 if (cpc->pllmr & 0x80000000) {
1875 D1 = (((cpc->pllmr >> 20) - 1) & 0xF) + 1; /* FBDV */
1876 D2 = 8 - ((cpc->pllmr >> 16) & 0x7); /* FWDVA */
1877 M = D0 * D1 * D2;
1878 VCO_out = cpc->sysclk * M;
1879 if (VCO_out < 400000000 || VCO_out > 800000000) {
1880 /* PLL cannot lock */
1881 cpc->pllmr &= ~0x80000000;
1882 goto bypass_pll;
1883 }
1884 PLL_out = VCO_out / D2;
1885 } else {
1886 /* Bypass PLL */
1887 bypass_pll:
1888 M = D0;
1889 PLL_out = cpc->sysclk * M;
1890 }
1891 CPU_clk = PLL_out;
1892 if (cpc->cr1 & 0x00800000)
1893 TMR_clk = cpc->sysclk; /* Should have a separate clock */
1894 else
1895 TMR_clk = CPU_clk;
1896 PLB_clk = CPU_clk / D0;
1897 SDRAM_clk = PLB_clk;
1898 D0 = ((cpc->pllmr >> 10) & 0x3) + 1;
1899 OPB_clk = PLB_clk / D0;
1900 D0 = ((cpc->pllmr >> 24) & 0x3) + 2;
1901 EXT_clk = PLB_clk / D0;
1902 D0 = ((cpc->cr0 >> 1) & 0x1F) + 1;
1903 UART_clk = CPU_clk / D0;
1904 /* Setup CPU clocks */
1905 clk_setup(&cpc->clk_setup[PPC405CR_CPU_CLK], CPU_clk);
1906 /* Setup time-base clock */
1907 clk_setup(&cpc->clk_setup[PPC405CR_TMR_CLK], TMR_clk);
1908 /* Setup PLB clock */
1909 clk_setup(&cpc->clk_setup[PPC405CR_PLB_CLK], PLB_clk);
1910 /* Setup SDRAM clock */
1911 clk_setup(&cpc->clk_setup[PPC405CR_SDRAM_CLK], SDRAM_clk);
1912 /* Setup OPB clock */
1913 clk_setup(&cpc->clk_setup[PPC405CR_OPB_CLK], OPB_clk);
1914 /* Setup external clock */
1915 clk_setup(&cpc->clk_setup[PPC405CR_EXT_CLK], EXT_clk);
1916 /* Setup UART clock */
1917 clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk);
1918 }
1919
1920 static uint32_t dcr_read_crcpc (void *opaque, int dcrn)
1921 {
1922 ppc405cr_cpc_t *cpc;
1923 uint32_t ret;
1924
1925 cpc = opaque;
1926 switch (dcrn) {
1927 case PPC405CR_CPC0_PLLMR:
1928 ret = cpc->pllmr;
1929 break;
1930 case PPC405CR_CPC0_CR0:
1931 ret = cpc->cr0;
1932 break;
1933 case PPC405CR_CPC0_CR1:
1934 ret = cpc->cr1;
1935 break;
1936 case PPC405CR_CPC0_PSR:
1937 ret = cpc->psr;
1938 break;
1939 case PPC405CR_CPC0_JTAGID:
1940 ret = cpc->jtagid;
1941 break;
1942 case PPC405CR_CPC0_ER:
1943 ret = cpc->er;
1944 break;
1945 case PPC405CR_CPC0_FR:
1946 ret = cpc->fr;
1947 break;
1948 case PPC405CR_CPC0_SR:
1949 ret = ~(cpc->er | cpc->fr) & 0xFFFF0000;
1950 break;
1951 default:
1952 /* Avoid gcc warning */
1953 ret = 0;
1954 break;
1955 }
1956
1957 return ret;
1958 }
1959
1960 static void dcr_write_crcpc (void *opaque, int dcrn, uint32_t val)
1961 {
1962 ppc405cr_cpc_t *cpc;
1963
1964 cpc = opaque;
1965 switch (dcrn) {
1966 case PPC405CR_CPC0_PLLMR:
1967 cpc->pllmr = val & 0xFFF77C3F;
1968 break;
1969 case PPC405CR_CPC0_CR0:
1970 cpc->cr0 = val & 0x0FFFFFFE;
1971 break;
1972 case PPC405CR_CPC0_CR1:
1973 cpc->cr1 = val & 0x00800000;
1974 break;
1975 case PPC405CR_CPC0_PSR:
1976 /* Read-only */
1977 break;
1978 case PPC405CR_CPC0_JTAGID:
1979 /* Read-only */
1980 break;
1981 case PPC405CR_CPC0_ER:
1982 cpc->er = val & 0xBFFC0000;
1983 break;
1984 case PPC405CR_CPC0_FR:
1985 cpc->fr = val & 0xBFFC0000;
1986 break;
1987 case PPC405CR_CPC0_SR:
1988 /* Read-only */
1989 break;
1990 }
1991 }
1992
1993 static void ppc405cr_cpc_reset (void *opaque)
1994 {
1995 ppc405cr_cpc_t *cpc;
1996 int D;
1997
1998 cpc = opaque;
1999 /* Compute PLLMR value from PSR settings */
2000 cpc->pllmr = 0x80000000;
2001 /* PFWD */
2002 switch ((cpc->psr >> 30) & 3) {
2003 case 0:
2004 /* Bypass */
2005 cpc->pllmr &= ~0x80000000;
2006 break;
2007 case 1:
2008 /* Divide by 3 */
2009 cpc->pllmr |= 5 << 16;
2010 break;
2011 case 2:
2012 /* Divide by 4 */
2013 cpc->pllmr |= 4 << 16;
2014 break;
2015 case 3:
2016 /* Divide by 6 */
2017 cpc->pllmr |= 2 << 16;
2018 break;
2019 }
2020 /* PFBD */
2021 D = (cpc->psr >> 28) & 3;
2022 cpc->pllmr |= (D + 1) << 20;
2023 /* PT */
2024 D = (cpc->psr >> 25) & 7;
2025 switch (D) {
2026 case 0x2:
2027 cpc->pllmr |= 0x13;
2028 break;
2029 case 0x4:
2030 cpc->pllmr |= 0x15;
2031 break;
2032 case 0x5:
2033 cpc->pllmr |= 0x16;
2034 break;
2035 default:
2036 break;
2037 }
2038 /* PDC */
2039 D = (cpc->psr >> 23) & 3;
2040 cpc->pllmr |= D << 26;
2041 /* ODP */
2042 D = (cpc->psr >> 21) & 3;
2043 cpc->pllmr |= D << 10;
2044 /* EBPD */
2045 D = (cpc->psr >> 17) & 3;
2046 cpc->pllmr |= D << 24;
2047 cpc->cr0 = 0x0000003C;
2048 cpc->cr1 = 0x2B0D8800;
2049 cpc->er = 0x00000000;
2050 cpc->fr = 0x00000000;
2051 ppc405cr_clk_setup(cpc);
2052 }
2053
2054 static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc)
2055 {
2056 int D;
2057
2058 /* XXX: this should be read from IO pins */
2059 cpc->psr = 0x00000000; /* 8 bits ROM */
2060 /* PFWD */
2061 D = 0x2; /* Divide by 4 */
2062 cpc->psr |= D << 30;
2063 /* PFBD */
2064 D = 0x1; /* Divide by 2 */
2065 cpc->psr |= D << 28;
2066 /* PDC */
2067 D = 0x1; /* Divide by 2 */
2068 cpc->psr |= D << 23;
2069 /* PT */
2070 D = 0x5; /* M = 16 */
2071 cpc->psr |= D << 25;
2072 /* ODP */
2073 D = 0x1; /* Divide by 2 */
2074 cpc->psr |= D << 21;
2075 /* EBDP */
2076 D = 0x2; /* Divide by 4 */
2077 cpc->psr |= D << 17;
2078 }
2079
2080 static void ppc405cr_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[7],
2081 uint32_t sysclk)
2082 {
2083 ppc405cr_cpc_t *cpc;
2084
2085 cpc = g_malloc0(sizeof(ppc405cr_cpc_t));
2086 memcpy(cpc->clk_setup, clk_setup,
2087 PPC405CR_CLK_NB * sizeof(clk_setup_t));
2088 cpc->sysclk = sysclk;
2089 cpc->jtagid = 0x42051049;
2090 ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
2091 &dcr_read_crcpc, &dcr_write_crcpc);
2092 ppc_dcr_register(env, PPC405CR_CPC0_CR0, cpc,
2093 &dcr_read_crcpc, &dcr_write_crcpc);
2094 ppc_dcr_register(env, PPC405CR_CPC0_CR1, cpc,
2095 &dcr_read_crcpc, &dcr_write_crcpc);
2096 ppc_dcr_register(env, PPC405CR_CPC0_JTAGID, cpc,
2097 &dcr_read_crcpc, &dcr_write_crcpc);
2098 ppc_dcr_register(env, PPC405CR_CPC0_PLLMR, cpc,
2099 &dcr_read_crcpc, &dcr_write_crcpc);
2100 ppc_dcr_register(env, PPC405CR_CPC0_ER, cpc,
2101 &dcr_read_crcpc, &dcr_write_crcpc);
2102 ppc_dcr_register(env, PPC405CR_CPC0_FR, cpc,
2103 &dcr_read_crcpc, &dcr_write_crcpc);
2104 ppc_dcr_register(env, PPC405CR_CPC0_SR, cpc,
2105 &dcr_read_crcpc, &dcr_write_crcpc);
2106 ppc405cr_clk_init(cpc);
2107 qemu_register_reset(ppc405cr_cpc_reset, cpc);
2108 }
2109
2110 CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,
2111 MemoryRegion ram_memories[4],
2112 hwaddr ram_bases[4],
2113 hwaddr ram_sizes[4],
2114 uint32_t sysclk, qemu_irq **picp,
2115 int do_init)
2116 {
2117 clk_setup_t clk_setup[PPC405CR_CLK_NB];
2118 qemu_irq dma_irqs[4];
2119 PowerPCCPU *cpu;
2120 CPUPPCState *env;
2121 qemu_irq *pic, *irqs;
2122
2123 memset(clk_setup, 0, sizeof(clk_setup));
2124 cpu = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
2125 &clk_setup[PPC405CR_TMR_CLK], sysclk);
2126 env = &cpu->env;
2127 /* Memory mapped devices registers */
2128 /* PLB arbitrer */
2129 ppc4xx_plb_init(env);
2130 /* PLB to OPB bridge */
2131 ppc4xx_pob_init(env);
2132 /* OBP arbitrer */
2133 ppc4xx_opba_init(0xef600600);
2134 /* Universal interrupt controller */
2135 irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2136 irqs[PPCUIC_OUTPUT_INT] =
2137 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2138 irqs[PPCUIC_OUTPUT_CINT] =
2139 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2140 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2141 *picp = pic;
2142 /* SDRAM controller */
2143 ppc4xx_sdram_init(env, pic[14], 1, ram_memories,
2144 ram_bases, ram_sizes, do_init);
2145 /* External bus controller */
2146 ppc405_ebc_init(env);
2147 /* DMA controller */
2148 dma_irqs[0] = pic[26];
2149 dma_irqs[1] = pic[25];
2150 dma_irqs[2] = pic[24];
2151 dma_irqs[3] = pic[23];
2152 ppc405_dma_init(env, dma_irqs);
2153 /* Serial ports */
2154 if (serial_hds[0] != NULL) {
2155 serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
2156 PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
2157 DEVICE_BIG_ENDIAN);
2158 }
2159 if (serial_hds[1] != NULL) {
2160 serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
2161 PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
2162 DEVICE_BIG_ENDIAN);
2163 }
2164 /* IIC controller */
2165 ppc405_i2c_init(0xef600500, pic[2]);
2166 /* GPIO */
2167 ppc405_gpio_init(0xef600700);
2168 /* CPU control */
2169 ppc405cr_cpc_init(env, clk_setup, sysclk);
2170
2171 return env;
2172 }
2173
2174 /*****************************************************************************/
2175 /* PowerPC 405EP */
2176 /* CPU control */
2177 enum {
2178 PPC405EP_CPC0_PLLMR0 = 0x0F0,
2179 PPC405EP_CPC0_BOOT = 0x0F1,
2180 PPC405EP_CPC0_EPCTL = 0x0F3,
2181 PPC405EP_CPC0_PLLMR1 = 0x0F4,
2182 PPC405EP_CPC0_UCR = 0x0F5,
2183 PPC405EP_CPC0_SRR = 0x0F6,
2184 PPC405EP_CPC0_JTAGID = 0x0F7,
2185 PPC405EP_CPC0_PCI = 0x0F9,
2186 #if 0
2187 PPC405EP_CPC0_ER = xxx,
2188 PPC405EP_CPC0_FR = xxx,
2189 PPC405EP_CPC0_SR = xxx,
2190 #endif
2191 };
2192
2193 enum {
2194 PPC405EP_CPU_CLK = 0,
2195 PPC405EP_PLB_CLK = 1,
2196 PPC405EP_OPB_CLK = 2,
2197 PPC405EP_EBC_CLK = 3,
2198 PPC405EP_MAL_CLK = 4,
2199 PPC405EP_PCI_CLK = 5,
2200 PPC405EP_UART0_CLK = 6,
2201 PPC405EP_UART1_CLK = 7,
2202 PPC405EP_CLK_NB = 8,
2203 };
2204
2205 typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
2206 struct ppc405ep_cpc_t {
2207 uint32_t sysclk;
2208 clk_setup_t clk_setup[PPC405EP_CLK_NB];
2209 uint32_t boot;
2210 uint32_t epctl;
2211 uint32_t pllmr[2];
2212 uint32_t ucr;
2213 uint32_t srr;
2214 uint32_t jtagid;
2215 uint32_t pci;
2216 /* Clock and power management */
2217 uint32_t er;
2218 uint32_t fr;
2219 uint32_t sr;
2220 };
2221
2222 static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
2223 {
2224 uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
2225 uint32_t UART0_clk, UART1_clk;
2226 uint64_t VCO_out, PLL_out;
2227 int M, D;
2228
2229 VCO_out = 0;
2230 if ((cpc->pllmr[1] & 0x80000000) && !(cpc->pllmr[1] & 0x40000000)) {
2231 M = (((cpc->pllmr[1] >> 20) - 1) & 0xF) + 1; /* FBMUL */
2232 #ifdef DEBUG_CLOCKS_LL
2233 printf("FBMUL %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 20) & 0xF, M);
2234 #endif
2235 D = 8 - ((cpc->pllmr[1] >> 16) & 0x7); /* FWDA */
2236 #ifdef DEBUG_CLOCKS_LL
2237 printf("FWDA %01" PRIx32 " %d\n", (cpc->pllmr[1] >> 16) & 0x7, D);
2238 #endif
2239 VCO_out = cpc->sysclk * M * D;
2240 if (VCO_out < 500000000UL || VCO_out > 1000000000UL) {
2241 /* Error - unlock the PLL */
2242 printf("VCO out of range %" PRIu64 "\n", VCO_out);
2243 #if 0
2244 cpc->pllmr[1] &= ~0x80000000;
2245 goto pll_bypass;
2246 #endif
2247 }
2248 PLL_out = VCO_out / D;
2249 /* Pretend the PLL is locked */
2250 cpc->boot |= 0x00000001;
2251 } else {
2252 #if 0
2253 pll_bypass:
2254 #endif
2255 PLL_out = cpc->sysclk;
2256 if (cpc->pllmr[1] & 0x40000000) {
2257 /* Pretend the PLL is not locked */
2258 cpc->boot &= ~0x00000001;
2259 }
2260 }
2261 /* Now, compute all other clocks */
2262 D = ((cpc->pllmr[0] >> 20) & 0x3) + 1; /* CCDV */
2263 #ifdef DEBUG_CLOCKS_LL
2264 printf("CCDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 20) & 0x3, D);
2265 #endif
2266 CPU_clk = PLL_out / D;
2267 D = ((cpc->pllmr[0] >> 16) & 0x3) + 1; /* CBDV */
2268 #ifdef DEBUG_CLOCKS_LL
2269 printf("CBDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 16) & 0x3, D);
2270 #endif
2271 PLB_clk = CPU_clk / D;
2272 D = ((cpc->pllmr[0] >> 12) & 0x3) + 1; /* OPDV */
2273 #ifdef DEBUG_CLOCKS_LL
2274 printf("OPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 12) & 0x3, D);
2275 #endif
2276 OPB_clk = PLB_clk / D;
2277 D = ((cpc->pllmr[0] >> 8) & 0x3) + 2; /* EPDV */
2278 #ifdef DEBUG_CLOCKS_LL
2279 printf("EPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 8) & 0x3, D);
2280 #endif
2281 EBC_clk = PLB_clk / D;
2282 D = ((cpc->pllmr[0] >> 4) & 0x3) + 1; /* MPDV */
2283 #ifdef DEBUG_CLOCKS_LL
2284 printf("MPDV %01" PRIx32 " %d\n", (cpc->pllmr[0] >> 4) & 0x3, D);
2285 #endif
2286 MAL_clk = PLB_clk / D;
2287 D = (cpc->pllmr[0] & 0x3) + 1; /* PPDV */
2288 #ifdef DEBUG_CLOCKS_LL
2289 printf("PPDV %01" PRIx32 " %d\n", cpc->pllmr[0] & 0x3, D);
2290 #endif
2291 PCI_clk = PLB_clk / D;
2292 D = ((cpc->ucr - 1) & 0x7F) + 1; /* U0DIV */
2293 #ifdef DEBUG_CLOCKS_LL
2294 printf("U0DIV %01" PRIx32 " %d\n", cpc->ucr & 0x7F, D);
2295 #endif
2296 UART0_clk = PLL_out / D;
2297 D = (((cpc->ucr >> 8) - 1) & 0x7F) + 1; /* U1DIV */
2298 #ifdef DEBUG_CLOCKS_LL
2299 printf("U1DIV %01" PRIx32 " %d\n", (cpc->ucr >> 8) & 0x7F, D);
2300 #endif
2301 UART1_clk = PLL_out / D;
2302 #ifdef DEBUG_CLOCKS
2303 printf("Setup PPC405EP clocks - sysclk %" PRIu32 " VCO %" PRIu64
2304 " PLL out %" PRIu64 " Hz\n", cpc->sysclk, VCO_out, PLL_out);
2305 printf("CPU %" PRIu32 " PLB %" PRIu32 " OPB %" PRIu32 " EBC %" PRIu32
2306 " MAL %" PRIu32 " PCI %" PRIu32 " UART0 %" PRIu32
2307 " UART1 %" PRIu32 "\n",
2308 CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk,
2309 UART0_clk, UART1_clk);
2310 #endif
2311 /* Setup CPU clocks */
2312 clk_setup(&cpc->clk_setup[PPC405EP_CPU_CLK], CPU_clk);
2313 /* Setup PLB clock */
2314 clk_setup(&cpc->clk_setup[PPC405EP_PLB_CLK], PLB_clk);
2315 /* Setup OPB clock */
2316 clk_setup(&cpc->clk_setup[PPC405EP_OPB_CLK], OPB_clk);
2317 /* Setup external clock */
2318 clk_setup(&cpc->clk_setup[PPC405EP_EBC_CLK], EBC_clk);
2319 /* Setup MAL clock */
2320 clk_setup(&cpc->clk_setup[PPC405EP_MAL_CLK], MAL_clk);
2321 /* Setup PCI clock */
2322 clk_setup(&cpc->clk_setup[PPC405EP_PCI_CLK], PCI_clk);
2323 /* Setup UART0 clock */
2324 clk_setup(&cpc->clk_setup[PPC405EP_UART0_CLK], UART0_clk);
2325 /* Setup UART1 clock */
2326 clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk);
2327 }
2328
2329 static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
2330 {
2331 ppc405ep_cpc_t *cpc;
2332 uint32_t ret;
2333
2334 cpc = opaque;
2335 switch (dcrn) {
2336 case PPC405EP_CPC0_BOOT:
2337 ret = cpc->boot;
2338 break;
2339 case PPC405EP_CPC0_EPCTL:
2340 ret = cpc->epctl;
2341 break;
2342 case PPC405EP_CPC0_PLLMR0:
2343 ret = cpc->pllmr[0];
2344 break;
2345 case PPC405EP_CPC0_PLLMR1:
2346 ret = cpc->pllmr[1];
2347 break;
2348 case PPC405EP_CPC0_UCR:
2349 ret = cpc->ucr;
2350 break;
2351 case PPC405EP_CPC0_SRR:
2352 ret = cpc->srr;
2353 break;
2354 case PPC405EP_CPC0_JTAGID:
2355 ret = cpc->jtagid;
2356 break;
2357 case PPC405EP_CPC0_PCI:
2358 ret = cpc->pci;
2359 break;
2360 default:
2361 /* Avoid gcc warning */
2362 ret = 0;
2363 break;
2364 }
2365
2366 return ret;
2367 }
2368
2369 static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
2370 {
2371 ppc405ep_cpc_t *cpc;
2372
2373 cpc = opaque;
2374 switch (dcrn) {
2375 case PPC405EP_CPC0_BOOT:
2376 /* Read-only register */
2377 break;
2378 case PPC405EP_CPC0_EPCTL:
2379 /* Don't care for now */
2380 cpc->epctl = val & 0xC00000F3;
2381 break;
2382 case PPC405EP_CPC0_PLLMR0:
2383 cpc->pllmr[0] = val & 0x00633333;
2384 ppc405ep_compute_clocks(cpc);
2385 break;
2386 case PPC405EP_CPC0_PLLMR1:
2387 cpc->pllmr[1] = val & 0xC0F73FFF;
2388 ppc405ep_compute_clocks(cpc);
2389 break;
2390 case PPC405EP_CPC0_UCR:
2391 /* UART control - don't care for now */
2392 cpc->ucr = val & 0x003F7F7F;
2393 break;
2394 case PPC405EP_CPC0_SRR:
2395 cpc->srr = val;
2396 break;
2397 case PPC405EP_CPC0_JTAGID:
2398 /* Read-only */
2399 break;
2400 case PPC405EP_CPC0_PCI:
2401 cpc->pci = val;
2402 break;
2403 }
2404 }
2405
2406 static void ppc405ep_cpc_reset (void *opaque)
2407 {
2408 ppc405ep_cpc_t *cpc = opaque;
2409
2410 cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
2411 cpc->epctl = 0x00000000;
2412 cpc->pllmr[0] = 0x00011010;
2413 cpc->pllmr[1] = 0x40000000;
2414 cpc->ucr = 0x00000000;
2415 cpc->srr = 0x00040000;
2416 cpc->pci = 0x00000000;
2417 cpc->er = 0x00000000;
2418 cpc->fr = 0x00000000;
2419 cpc->sr = 0x00000000;
2420 ppc405ep_compute_clocks(cpc);
2421 }
2422
2423 /* XXX: sysclk should be between 25 and 100 MHz */
2424 static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
2425 uint32_t sysclk)
2426 {
2427 ppc405ep_cpc_t *cpc;
2428
2429 cpc = g_malloc0(sizeof(ppc405ep_cpc_t));
2430 memcpy(cpc->clk_setup, clk_setup,
2431 PPC405EP_CLK_NB * sizeof(clk_setup_t));
2432 cpc->jtagid = 0x20267049;
2433 cpc->sysclk = sysclk;
2434 qemu_register_reset(&ppc405ep_cpc_reset, cpc);
2435 ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
2436 &dcr_read_epcpc, &dcr_write_epcpc);
2437 ppc_dcr_register(env, PPC405EP_CPC0_EPCTL, cpc,
2438 &dcr_read_epcpc, &dcr_write_epcpc);
2439 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR0, cpc,
2440 &dcr_read_epcpc, &dcr_write_epcpc);
2441 ppc_dcr_register(env, PPC405EP_CPC0_PLLMR1, cpc,
2442 &dcr_read_epcpc, &dcr_write_epcpc);
2443 ppc_dcr_register(env, PPC405EP_CPC0_UCR, cpc,
2444 &dcr_read_epcpc, &dcr_write_epcpc);
2445 ppc_dcr_register(env, PPC405EP_CPC0_SRR, cpc,
2446 &dcr_read_epcpc, &dcr_write_epcpc);
2447 ppc_dcr_register(env, PPC405EP_CPC0_JTAGID, cpc,
2448 &dcr_read_epcpc, &dcr_write_epcpc);
2449 ppc_dcr_register(env, PPC405EP_CPC0_PCI, cpc,
2450 &dcr_read_epcpc, &dcr_write_epcpc);
2451 #if 0
2452 ppc_dcr_register(env, PPC405EP_CPC0_ER, cpc,
2453 &dcr_read_epcpc, &dcr_write_epcpc);
2454 ppc_dcr_register(env, PPC405EP_CPC0_FR, cpc,
2455 &dcr_read_epcpc, &dcr_write_epcpc);
2456 ppc_dcr_register(env, PPC405EP_CPC0_SR, cpc,
2457 &dcr_read_epcpc, &dcr_write_epcpc);
2458 #endif
2459 }
2460
2461 CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
2462 MemoryRegion ram_memories[2],
2463 hwaddr ram_bases[2],
2464 hwaddr ram_sizes[2],
2465 uint32_t sysclk, qemu_irq **picp,
2466 int do_init)
2467 {
2468 clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
2469 qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
2470 PowerPCCPU *cpu;
2471 CPUPPCState *env;
2472 qemu_irq *pic, *irqs;
2473
2474 memset(clk_setup, 0, sizeof(clk_setup));
2475 /* init CPUs */
2476 cpu = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
2477 &tlb_clk_setup, sysclk);
2478 env = &cpu->env;
2479 clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
2480 clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
2481 /* Internal devices init */
2482 /* Memory mapped devices registers */
2483 /* PLB arbitrer */
2484 ppc4xx_plb_init(env);
2485 /* PLB to OPB bridge */
2486 ppc4xx_pob_init(env);
2487 /* OBP arbitrer */
2488 ppc4xx_opba_init(0xef600600);
2489 /* Initialize timers */
2490 ppc_booke_timers_init(cpu, sysclk, 0);
2491 /* Universal interrupt controller */
2492 irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
2493 irqs[PPCUIC_OUTPUT_INT] =
2494 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
2495 irqs[PPCUIC_OUTPUT_CINT] =
2496 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
2497 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
2498 *picp = pic;
2499 /* SDRAM controller */
2500 /* XXX 405EP has no ECC interrupt */
2501 ppc4xx_sdram_init(env, pic[17], 2, ram_memories,
2502 ram_bases, ram_sizes, do_init);
2503 /* External bus controller */
2504 ppc405_ebc_init(env);
2505 /* DMA controller */
2506 dma_irqs[0] = pic[5];
2507 dma_irqs[1] = pic[6];
2508 dma_irqs[2] = pic[7];
2509 dma_irqs[3] = pic[8];
2510 ppc405_dma_init(env, dma_irqs);
2511 /* IIC controller */
2512 ppc405_i2c_init(0xef600500, pic[2]);
2513 /* GPIO */
2514 ppc405_gpio_init(0xef600700);
2515 /* Serial ports */
2516 if (serial_hds[0] != NULL) {
2517 serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
2518 PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
2519 DEVICE_BIG_ENDIAN);
2520 }
2521 if (serial_hds[1] != NULL) {
2522 serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
2523 PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
2524 DEVICE_BIG_ENDIAN);
2525 }
2526 /* OCM */
2527 ppc405_ocm_init(env);
2528 /* GPT */
2529 gpt_irqs[0] = pic[19];
2530 gpt_irqs[1] = pic[20];
2531 gpt_irqs[2] = pic[21];
2532 gpt_irqs[3] = pic[22];
2533 gpt_irqs[4] = pic[23];
2534 ppc4xx_gpt_init(0xef600000, gpt_irqs);
2535 /* PCI */
2536 /* Uses pic[3], pic[16], pic[18] */
2537 /* MAL */
2538 mal_irqs[0] = pic[11];
2539 mal_irqs[1] = pic[12];
2540 mal_irqs[2] = pic[13];
2541 mal_irqs[3] = pic[14];
2542 ppc405_mal_init(env, mal_irqs);
2543 /* Ethernet */
2544 /* Uses pic[9], pic[15], pic[17] */
2545 /* CPU control */
2546 ppc405ep_cpc_init(env, clk_setup, sysclk);
2547
2548 return env;
2549 }