hw/arm/raspi: fix CPRMAN base address
[qemu.git] / hw / ppc / ppc440_bamboo.c
1 /*
2 * QEMU PowerPC 440 Bamboo board emulation
3 *
4 * Copyright 2007 IBM Corporation.
5 * Authors:
6 * Jerone Young <jyoung5@us.ibm.com>
7 * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
8 * Hollis Blanchard <hollisb@us.ibm.com>
9 *
10 * This work is licensed under the GNU GPL license version 2 or later.
11 *
12 */
13
14 #include "qemu/osdep.h"
15 #include "qemu/units.h"
16 #include "qemu/error-report.h"
17 #include "qemu-common.h"
18 #include "qemu/error-report.h"
19 #include "net/net.h"
20 #include "hw/pci/pci.h"
21 #include "hw/boards.h"
22 #include "sysemu/kvm.h"
23 #include "kvm_ppc.h"
24 #include "sysemu/device_tree.h"
25 #include "hw/loader.h"
26 #include "elf.h"
27 #include "exec/address-spaces.h"
28 #include "hw/char/serial.h"
29 #include "hw/ppc/ppc.h"
30 #include "ppc405.h"
31 #include "sysemu/sysemu.h"
32 #include "sysemu/qtest.h"
33 #include "sysemu/reset.h"
34 #include "hw/sysbus.h"
35
36 #define BINARY_DEVICE_TREE_FILE "bamboo.dtb"
37
38 /* from u-boot */
39 #define KERNEL_ADDR 0x1000000
40 #define FDT_ADDR 0x1800000
41 #define RAMDISK_ADDR 0x1900000
42
43 #define PPC440EP_PCI_CONFIG 0xeec00000
44 #define PPC440EP_PCI_INTACK 0xeed00000
45 #define PPC440EP_PCI_SPECIAL 0xeed00000
46 #define PPC440EP_PCI_REGS 0xef400000
47 #define PPC440EP_PCI_IO 0xe8000000
48 #define PPC440EP_PCI_IOLEN 0x00010000
49
50 #define PPC440EP_SDRAM_NR_BANKS 4
51
52 static const ram_addr_t ppc440ep_sdram_bank_sizes[] = {
53 256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 0
54 };
55
56 static hwaddr entry;
57
58 static int bamboo_load_device_tree(hwaddr addr,
59 uint32_t ramsize,
60 hwaddr initrd_base,
61 hwaddr initrd_size,
62 const char *kernel_cmdline)
63 {
64 int ret = -1;
65 uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(ramsize) };
66 char *filename;
67 int fdt_size;
68 void *fdt;
69 uint32_t tb_freq = 400000000;
70 uint32_t clock_freq = 400000000;
71
72 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
73 if (!filename) {
74 return -1;
75 }
76 fdt = load_device_tree(filename, &fdt_size);
77 g_free(filename);
78 if (fdt == NULL) {
79 return -1;
80 }
81
82 /* Manipulate device tree in memory. */
83
84 ret = qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property,
85 sizeof(mem_reg_property));
86 if (ret < 0)
87 fprintf(stderr, "couldn't set /memory/reg\n");
88
89 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
90 initrd_base);
91 if (ret < 0)
92 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
93
94 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
95 (initrd_base + initrd_size));
96 if (ret < 0)
97 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
98
99 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
100 kernel_cmdline);
101 if (ret < 0)
102 fprintf(stderr, "couldn't set /chosen/bootargs\n");
103
104 /* Copy data from the host device tree into the guest. Since the guest can
105 * directly access the timebase without host involvement, we must expose
106 * the correct frequencies. */
107 if (kvm_enabled()) {
108 tb_freq = kvmppc_get_tbfreq();
109 clock_freq = kvmppc_get_clockfreq();
110 }
111
112 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency",
113 clock_freq);
114 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency",
115 tb_freq);
116
117 rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
118 g_free(fdt);
119 return 0;
120 }
121
122 /* Create reset TLB entries for BookE, spanning the 32bit addr space. */
123 static void mmubooke_create_initial_mapping(CPUPPCState *env,
124 target_ulong va,
125 hwaddr pa)
126 {
127 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
128
129 tlb->attr = 0;
130 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
131 tlb->size = 1U << 31; /* up to 0x80000000 */
132 tlb->EPN = va & TARGET_PAGE_MASK;
133 tlb->RPN = pa & TARGET_PAGE_MASK;
134 tlb->PID = 0;
135
136 tlb = &env->tlb.tlbe[1];
137 tlb->attr = 0;
138 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
139 tlb->size = 1U << 31; /* up to 0xffffffff */
140 tlb->EPN = 0x80000000 & TARGET_PAGE_MASK;
141 tlb->RPN = 0x80000000 & TARGET_PAGE_MASK;
142 tlb->PID = 0;
143 }
144
145 static void main_cpu_reset(void *opaque)
146 {
147 PowerPCCPU *cpu = opaque;
148 CPUPPCState *env = &cpu->env;
149
150 cpu_reset(CPU(cpu));
151 env->gpr[1] = (16 * MiB) - 8;
152 env->gpr[3] = FDT_ADDR;
153 env->nip = entry;
154
155 /* Create a mapping for the kernel. */
156 mmubooke_create_initial_mapping(env, 0, 0);
157 }
158
159 static void bamboo_init(MachineState *machine)
160 {
161 const char *kernel_filename = machine->kernel_filename;
162 const char *kernel_cmdline = machine->kernel_cmdline;
163 const char *initrd_filename = machine->initrd_filename;
164 unsigned int pci_irq_nrs[4] = { 28, 27, 26, 25 };
165 MemoryRegion *address_space_mem = get_system_memory();
166 MemoryRegion *isa = g_new(MemoryRegion, 1);
167 MemoryRegion *ram_memories = g_new(MemoryRegion, PPC440EP_SDRAM_NR_BANKS);
168 hwaddr ram_bases[PPC440EP_SDRAM_NR_BANKS];
169 hwaddr ram_sizes[PPC440EP_SDRAM_NR_BANKS];
170 qemu_irq *pic;
171 qemu_irq *irqs;
172 PCIBus *pcibus;
173 PowerPCCPU *cpu;
174 CPUPPCState *env;
175 target_long initrd_size = 0;
176 DeviceState *dev;
177 int success;
178 int i;
179
180 cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
181 env = &cpu->env;
182
183 if (env->mmu_model != POWERPC_MMU_BOOKE) {
184 error_report("MMU model %i not supported by this machine",
185 env->mmu_model);
186 exit(1);
187 }
188
189 qemu_register_reset(main_cpu_reset, cpu);
190 ppc_booke_timers_init(cpu, 400000000, 0);
191 ppc_dcr_init(env, NULL, NULL);
192
193 /* interrupt controller */
194 irqs = g_new0(qemu_irq, PPCUIC_OUTPUT_NB);
195 irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
196 irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT];
197 pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
198
199 /* SDRAM controller */
200 memset(ram_bases, 0, sizeof(ram_bases));
201 memset(ram_sizes, 0, sizeof(ram_sizes));
202 ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_memories,
203 ram_bases, ram_sizes, ppc440ep_sdram_bank_sizes);
204 /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
205 ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_memories,
206 ram_bases, ram_sizes, 1);
207
208 /* PCI */
209 dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE,
210 PPC440EP_PCI_CONFIG,
211 pic[pci_irq_nrs[0]], pic[pci_irq_nrs[1]],
212 pic[pci_irq_nrs[2]], pic[pci_irq_nrs[3]],
213 NULL);
214 pcibus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
215 if (!pcibus) {
216 error_report("couldn't create PCI controller");
217 exit(1);
218 }
219
220 memory_region_init_alias(isa, NULL, "isa_mmio",
221 get_system_io(), 0, PPC440EP_PCI_IOLEN);
222 memory_region_add_subregion(get_system_memory(), PPC440EP_PCI_IO, isa);
223
224 if (serial_hd(0) != NULL) {
225 serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
226 PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
227 DEVICE_BIG_ENDIAN);
228 }
229 if (serial_hd(1) != NULL) {
230 serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
231 PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
232 DEVICE_BIG_ENDIAN);
233 }
234
235 if (pcibus) {
236 /* Register network interfaces. */
237 for (i = 0; i < nb_nics; i++) {
238 /* There are no PCI NICs on the Bamboo board, but there are
239 * PCI slots, so we can pick whatever default model we want. */
240 pci_nic_init_nofail(&nd_table[i], pcibus, "e1000", NULL);
241 }
242 }
243
244 /* Load kernel. */
245 if (kernel_filename) {
246 hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID;
247 success = load_uimage(kernel_filename, &entry, &loadaddr, NULL,
248 NULL, NULL);
249 if (success < 0) {
250 uint64_t elf_entry;
251 success = load_elf(kernel_filename, NULL, NULL, NULL, &elf_entry,
252 NULL, NULL, NULL, 1, PPC_ELF_MACHINE, 0, 0);
253 entry = elf_entry;
254 }
255 /* XXX try again as binary */
256 if (success < 0) {
257 error_report("could not load kernel '%s'", kernel_filename);
258 exit(1);
259 }
260 }
261
262 /* Load initrd. */
263 if (initrd_filename) {
264 initrd_size = load_image_targphys(initrd_filename, RAMDISK_ADDR,
265 machine->ram_size - RAMDISK_ADDR);
266
267 if (initrd_size < 0) {
268 error_report("could not load ram disk '%s' at %x",
269 initrd_filename, RAMDISK_ADDR);
270 exit(1);
271 }
272 }
273
274 /* If we're loading a kernel directly, we must load the device tree too. */
275 if (kernel_filename) {
276 if (bamboo_load_device_tree(FDT_ADDR, machine->ram_size, RAMDISK_ADDR,
277 initrd_size, kernel_cmdline) < 0) {
278 error_report("couldn't load device tree");
279 exit(1);
280 }
281 }
282 }
283
284 static void bamboo_machine_init(MachineClass *mc)
285 {
286 mc->desc = "bamboo";
287 mc->init = bamboo_init;
288 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("440epb");
289 mc->default_ram_id = "ppc4xx.sdram";
290 }
291
292 DEFINE_MACHINE("bamboo", bamboo_machine_init)