Merge remote-tracking branch 'remotes/philmd-gitlab/tags/renesas-20201027' into staging
[qemu.git] / hw / ppc / ppc_booke.c
1 /*
2 * QEMU PowerPC Booke hardware System Emulator
3 *
4 * Copyright (c) 2011 AdaCore
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "cpu.h"
27 #include "hw/ppc/ppc.h"
28 #include "qemu/timer.h"
29 #include "sysemu/reset.h"
30 #include "sysemu/runstate.h"
31 #include "qemu/log.h"
32 #include "hw/loader.h"
33 #include "kvm_ppc.h"
34
35
36 /* Timer Control Register */
37
38 #define TCR_WP_SHIFT 30 /* Watchdog Timer Period */
39 #define TCR_WP_MASK (0x3U << TCR_WP_SHIFT)
40 #define TCR_WRC_SHIFT 28 /* Watchdog Timer Reset Control */
41 #define TCR_WRC_MASK (0x3U << TCR_WRC_SHIFT)
42 #define TCR_WIE (1U << 27) /* Watchdog Timer Interrupt Enable */
43 #define TCR_DIE (1U << 26) /* Decrementer Interrupt Enable */
44 #define TCR_FP_SHIFT 24 /* Fixed-Interval Timer Period */
45 #define TCR_FP_MASK (0x3U << TCR_FP_SHIFT)
46 #define TCR_FIE (1U << 23) /* Fixed-Interval Timer Interrupt Enable */
47 #define TCR_ARE (1U << 22) /* Auto-Reload Enable */
48
49 /* Timer Control Register (e500 specific fields) */
50
51 #define TCR_E500_FPEXT_SHIFT 13 /* Fixed-Interval Timer Period Extension */
52 #define TCR_E500_FPEXT_MASK (0xf << TCR_E500_FPEXT_SHIFT)
53 #define TCR_E500_WPEXT_SHIFT 17 /* Watchdog Timer Period Extension */
54 #define TCR_E500_WPEXT_MASK (0xf << TCR_E500_WPEXT_SHIFT)
55
56 /* Timer Status Register */
57
58 #define TSR_FIS (1U << 26) /* Fixed-Interval Timer Interrupt Status */
59 #define TSR_DIS (1U << 27) /* Decrementer Interrupt Status */
60 #define TSR_WRS_SHIFT 28 /* Watchdog Timer Reset Status */
61 #define TSR_WRS_MASK (0x3U << TSR_WRS_SHIFT)
62 #define TSR_WIS (1U << 30) /* Watchdog Timer Interrupt Status */
63 #define TSR_ENW (1U << 31) /* Enable Next Watchdog Timer */
64
65 typedef struct booke_timer_t booke_timer_t;
66 struct booke_timer_t {
67
68 uint64_t fit_next;
69 QEMUTimer *fit_timer;
70
71 uint64_t wdt_next;
72 QEMUTimer *wdt_timer;
73
74 uint32_t flags;
75 };
76
77 static void booke_update_irq(PowerPCCPU *cpu)
78 {
79 CPUPPCState *env = &cpu->env;
80
81 ppc_set_irq(cpu, PPC_INTERRUPT_DECR,
82 (env->spr[SPR_BOOKE_TSR] & TSR_DIS
83 && env->spr[SPR_BOOKE_TCR] & TCR_DIE));
84
85 ppc_set_irq(cpu, PPC_INTERRUPT_WDT,
86 (env->spr[SPR_BOOKE_TSR] & TSR_WIS
87 && env->spr[SPR_BOOKE_TCR] & TCR_WIE));
88
89 ppc_set_irq(cpu, PPC_INTERRUPT_FIT,
90 (env->spr[SPR_BOOKE_TSR] & TSR_FIS
91 && env->spr[SPR_BOOKE_TCR] & TCR_FIE));
92 }
93
94 /* Return the location of the bit of time base at which the FIT will raise an
95 interrupt */
96 static uint8_t booke_get_fit_target(CPUPPCState *env, ppc_tb_t *tb_env)
97 {
98 uint8_t fp = (env->spr[SPR_BOOKE_TCR] & TCR_FP_MASK) >> TCR_FP_SHIFT;
99
100 if (tb_env->flags & PPC_TIMER_E500) {
101 /* e500 Fixed-interval timer period extension */
102 uint32_t fpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_FPEXT_MASK)
103 >> TCR_E500_FPEXT_SHIFT;
104 fp = 63 - (fp | fpext << 2);
105 } else {
106 fp = env->fit_period[fp];
107 }
108
109 return fp;
110 }
111
112 /* Return the location of the bit of time base at which the WDT will raise an
113 interrupt */
114 static uint8_t booke_get_wdt_target(CPUPPCState *env, ppc_tb_t *tb_env)
115 {
116 uint8_t wp = (env->spr[SPR_BOOKE_TCR] & TCR_WP_MASK) >> TCR_WP_SHIFT;
117
118 if (tb_env->flags & PPC_TIMER_E500) {
119 /* e500 Watchdog timer period extension */
120 uint32_t wpext = (env->spr[SPR_BOOKE_TCR] & TCR_E500_WPEXT_MASK)
121 >> TCR_E500_WPEXT_SHIFT;
122 wp = 63 - (wp | wpext << 2);
123 } else {
124 wp = env->wdt_period[wp];
125 }
126
127 return wp;
128 }
129
130 static void booke_update_fixed_timer(CPUPPCState *env,
131 uint8_t target_bit,
132 uint64_t *next,
133 QEMUTimer *timer,
134 int tsr_bit)
135 {
136 ppc_tb_t *tb_env = env->tb_env;
137 uint64_t delta_tick, ticks = 0;
138 uint64_t tb;
139 uint64_t period;
140 uint64_t now;
141
142 if (!(env->spr[SPR_BOOKE_TSR] & tsr_bit)) {
143 /*
144 * Don't arm the timer again when the guest has the current
145 * interrupt still pending. Wait for it to ack it.
146 */
147 return;
148 }
149
150 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
151 tb = cpu_ppc_get_tb(tb_env, now, tb_env->tb_offset);
152 period = 1ULL << target_bit;
153 delta_tick = period - (tb & (period - 1));
154
155 /* the timer triggers only when the selected bit toggles from 0 to 1 */
156 if (tb & period) {
157 ticks = period;
158 }
159
160 if (ticks + delta_tick < ticks) {
161 /* Overflow, so assume the biggest number we can express. */
162 ticks = UINT64_MAX;
163 } else {
164 ticks += delta_tick;
165 }
166
167 *next = now + muldiv64(ticks, NANOSECONDS_PER_SECOND, tb_env->tb_freq);
168 if ((*next < now) || (*next > INT64_MAX)) {
169 /* Overflow, so assume the biggest number the qemu timer supports. */
170 *next = INT64_MAX;
171 }
172
173 /* XXX: If expire time is now. We can't run the callback because we don't
174 * have access to it. So we just set the timer one nanosecond later.
175 */
176
177 if (*next == now) {
178 (*next)++;
179 } else {
180 /*
181 * There's no point to fake any granularity that's more fine grained
182 * than milliseconds. Anything beyond that just overloads the system.
183 */
184 *next = MAX(*next, now + SCALE_MS);
185 }
186
187 /* Fire the next timer */
188 timer_mod(timer, *next);
189 }
190
191 static void booke_decr_cb(void *opaque)
192 {
193 PowerPCCPU *cpu = opaque;
194 CPUPPCState *env = &cpu->env;
195
196 env->spr[SPR_BOOKE_TSR] |= TSR_DIS;
197 booke_update_irq(cpu);
198
199 if (env->spr[SPR_BOOKE_TCR] & TCR_ARE) {
200 /* Do not reload 0, it is already there. It would just trigger
201 * the timer again and lead to infinite loop */
202 if (env->spr[SPR_BOOKE_DECAR] != 0) {
203 /* Auto Reload */
204 cpu_ppc_store_decr(env, env->spr[SPR_BOOKE_DECAR]);
205 }
206 }
207 }
208
209 static void booke_fit_cb(void *opaque)
210 {
211 PowerPCCPU *cpu = opaque;
212 CPUPPCState *env = &cpu->env;
213 ppc_tb_t *tb_env;
214 booke_timer_t *booke_timer;
215
216 tb_env = env->tb_env;
217 booke_timer = tb_env->opaque;
218 env->spr[SPR_BOOKE_TSR] |= TSR_FIS;
219
220 booke_update_irq(cpu);
221
222 booke_update_fixed_timer(env,
223 booke_get_fit_target(env, tb_env),
224 &booke_timer->fit_next,
225 booke_timer->fit_timer,
226 TSR_FIS);
227 }
228
229 static void booke_wdt_cb(void *opaque)
230 {
231 PowerPCCPU *cpu = opaque;
232 CPUPPCState *env = &cpu->env;
233 ppc_tb_t *tb_env;
234 booke_timer_t *booke_timer;
235
236 tb_env = env->tb_env;
237 booke_timer = tb_env->opaque;
238
239 /* TODO: There's lots of complicated stuff to do here */
240
241 booke_update_irq(cpu);
242
243 booke_update_fixed_timer(env,
244 booke_get_wdt_target(env, tb_env),
245 &booke_timer->wdt_next,
246 booke_timer->wdt_timer,
247 TSR_WIS);
248 }
249
250 void store_booke_tsr(CPUPPCState *env, target_ulong val)
251 {
252 PowerPCCPU *cpu = env_archcpu(env);
253 ppc_tb_t *tb_env = env->tb_env;
254 booke_timer_t *booke_timer = tb_env->opaque;
255
256 env->spr[SPR_BOOKE_TSR] &= ~val;
257 kvmppc_clear_tsr_bits(cpu, val);
258
259 if (val & TSR_FIS) {
260 booke_update_fixed_timer(env,
261 booke_get_fit_target(env, tb_env),
262 &booke_timer->fit_next,
263 booke_timer->fit_timer,
264 TSR_FIS);
265 }
266
267 if (val & TSR_WIS) {
268 booke_update_fixed_timer(env,
269 booke_get_wdt_target(env, tb_env),
270 &booke_timer->wdt_next,
271 booke_timer->wdt_timer,
272 TSR_WIS);
273 }
274
275 booke_update_irq(cpu);
276 }
277
278 void store_booke_tcr(CPUPPCState *env, target_ulong val)
279 {
280 PowerPCCPU *cpu = env_archcpu(env);
281 ppc_tb_t *tb_env = env->tb_env;
282 booke_timer_t *booke_timer = tb_env->opaque;
283
284 env->spr[SPR_BOOKE_TCR] = val;
285 kvmppc_set_tcr(cpu);
286
287 booke_update_irq(cpu);
288
289 booke_update_fixed_timer(env,
290 booke_get_fit_target(env, tb_env),
291 &booke_timer->fit_next,
292 booke_timer->fit_timer,
293 TSR_FIS);
294
295 booke_update_fixed_timer(env,
296 booke_get_wdt_target(env, tb_env),
297 &booke_timer->wdt_next,
298 booke_timer->wdt_timer,
299 TSR_WIS);
300 }
301
302 static void ppc_booke_timer_reset_handle(void *opaque)
303 {
304 PowerPCCPU *cpu = opaque;
305 CPUPPCState *env = &cpu->env;
306
307 store_booke_tcr(env, 0);
308 store_booke_tsr(env, -1);
309 }
310
311 /*
312 * This function will be called whenever the CPU state changes.
313 * CPU states are defined "typedef enum RunState".
314 * Regarding timer, When CPU state changes to running after debug halt
315 * or similar cases which takes time then in between final watchdog
316 * expiry happenes. This will cause exit to QEMU and configured watchdog
317 * action will be taken. To avoid this we always clear the watchdog state when
318 * state changes to running.
319 */
320 static void cpu_state_change_handler(void *opaque, int running, RunState state)
321 {
322 PowerPCCPU *cpu = opaque;
323 CPUPPCState *env = &cpu->env;
324
325 if (!running) {
326 return;
327 }
328
329 /*
330 * Clear watchdog interrupt condition by clearing TSR.
331 */
332 store_booke_tsr(env, TSR_ENW | TSR_WIS | TSR_WRS_MASK);
333 }
334
335 void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t freq, uint32_t flags)
336 {
337 ppc_tb_t *tb_env;
338 booke_timer_t *booke_timer;
339 int ret = 0;
340
341 tb_env = g_malloc0(sizeof(ppc_tb_t));
342 booke_timer = g_malloc0(sizeof(booke_timer_t));
343
344 cpu->env.tb_env = tb_env;
345 tb_env->flags = flags | PPC_TIMER_BOOKE | PPC_DECR_ZERO_TRIGGERED;
346
347 tb_env->tb_freq = freq;
348 tb_env->decr_freq = freq;
349 tb_env->opaque = booke_timer;
350 tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_decr_cb, cpu);
351
352 booke_timer->fit_timer =
353 timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_fit_cb, cpu);
354 booke_timer->wdt_timer =
355 timer_new_ns(QEMU_CLOCK_VIRTUAL, &booke_wdt_cb, cpu);
356
357 ret = kvmppc_booke_watchdog_enable(cpu);
358
359 if (ret) {
360 /* TODO: Start the QEMU emulated watchdog if not running on KVM.
361 * Also start the QEMU emulated watchdog if KVM does not support
362 * emulated watchdog or somehow it is not enabled (supported but
363 * not enabled is though some bug and requires debugging :)).
364 */
365 }
366
367 qemu_add_vm_change_state_handler(cpu_state_change_handler, cpu);
368
369 qemu_register_reset(ppc_booke_timer_reset_handle, cpu);
370 }