raven: Implement non-contiguous I/O region
[qemu.git] / hw / ppc / prep.c
1 /*
2 * QEMU PPC PREP hardware System Emulator
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw/hw.h"
25 #include "hw/timer/m48t59.h"
26 #include "hw/i386/pc.h"
27 #include "hw/char/serial.h"
28 #include "hw/block/fdc.h"
29 #include "net/net.h"
30 #include "sysemu/sysemu.h"
31 #include "hw/isa/isa.h"
32 #include "hw/pci/pci.h"
33 #include "hw/pci/pci_host.h"
34 #include "hw/ppc/ppc.h"
35 #include "hw/boards.h"
36 #include "qemu/log.h"
37 #include "hw/ide.h"
38 #include "hw/loader.h"
39 #include "hw/timer/mc146818rtc.h"
40 #include "hw/isa/pc87312.h"
41 #include "sysemu/blockdev.h"
42 #include "sysemu/arch_init.h"
43 #include "sysemu/qtest.h"
44 #include "exec/address-spaces.h"
45 #include "elf.h"
46
47 //#define HARD_DEBUG_PPC_IO
48 //#define DEBUG_PPC_IO
49
50 /* SMP is not enabled, for now */
51 #define MAX_CPUS 1
52
53 #define MAX_IDE_BUS 2
54
55 #define BIOS_SIZE (1024 * 1024)
56 #define BIOS_FILENAME "ppc_rom.bin"
57 #define KERNEL_LOAD_ADDR 0x01000000
58 #define INITRD_LOAD_ADDR 0x01800000
59
60 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
61 #define DEBUG_PPC_IO
62 #endif
63
64 #if defined (HARD_DEBUG_PPC_IO)
65 #define PPC_IO_DPRINTF(fmt, ...) \
66 do { \
67 if (qemu_loglevel_mask(CPU_LOG_IOPORT)) { \
68 qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \
69 } else { \
70 printf("%s : " fmt, __func__ , ## __VA_ARGS__); \
71 } \
72 } while (0)
73 #elif defined (DEBUG_PPC_IO)
74 #define PPC_IO_DPRINTF(fmt, ...) \
75 qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__)
76 #else
77 #define PPC_IO_DPRINTF(fmt, ...) do { } while (0)
78 #endif
79
80 /* Constants for devices init */
81 static const int ide_iobase[2] = { 0x1f0, 0x170 };
82 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
83 static const int ide_irq[2] = { 13, 13 };
84
85 #define NE2000_NB_MAX 6
86
87 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
88 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
89
90 /* ISA IO ports bridge */
91 #define PPC_IO_BASE 0x80000000
92
93 /* PowerPC control and status registers */
94 #if 0 // Not used
95 static struct {
96 /* IDs */
97 uint32_t veni_devi;
98 uint32_t revi;
99 /* Control and status */
100 uint32_t gcsr;
101 uint32_t xcfr;
102 uint32_t ct32;
103 uint32_t mcsr;
104 /* General purpose registers */
105 uint32_t gprg[6];
106 /* Exceptions */
107 uint32_t feen;
108 uint32_t fest;
109 uint32_t fema;
110 uint32_t fecl;
111 uint32_t eeen;
112 uint32_t eest;
113 uint32_t eecl;
114 uint32_t eeint;
115 uint32_t eemck0;
116 uint32_t eemck1;
117 /* Error diagnostic */
118 } XCSR;
119
120 static void PPC_XCSR_writeb (void *opaque,
121 hwaddr addr, uint32_t value)
122 {
123 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
124 value);
125 }
126
127 static void PPC_XCSR_writew (void *opaque,
128 hwaddr addr, uint32_t value)
129 {
130 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
131 value);
132 }
133
134 static void PPC_XCSR_writel (void *opaque,
135 hwaddr addr, uint32_t value)
136 {
137 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
138 value);
139 }
140
141 static uint32_t PPC_XCSR_readb (void *opaque, hwaddr addr)
142 {
143 uint32_t retval = 0;
144
145 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
146 retval);
147
148 return retval;
149 }
150
151 static uint32_t PPC_XCSR_readw (void *opaque, hwaddr addr)
152 {
153 uint32_t retval = 0;
154
155 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
156 retval);
157
158 return retval;
159 }
160
161 static uint32_t PPC_XCSR_readl (void *opaque, hwaddr addr)
162 {
163 uint32_t retval = 0;
164
165 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
166 retval);
167
168 return retval;
169 }
170
171 static const MemoryRegionOps PPC_XCSR_ops = {
172 .old_mmio = {
173 .read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, },
174 .write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, },
175 },
176 .endianness = DEVICE_LITTLE_ENDIAN,
177 };
178
179 #endif
180
181 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
182 typedef struct sysctrl_t {
183 qemu_irq reset_irq;
184 M48t59State *nvram;
185 uint8_t state;
186 uint8_t syscontrol;
187 int contiguous_map;
188 qemu_irq contiguous_map_irq;
189 int endian;
190 } sysctrl_t;
191
192 enum {
193 STATE_HARDFILE = 0x01,
194 };
195
196 static sysctrl_t *sysctrl;
197
198 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
199 {
200 sysctrl_t *sysctrl = opaque;
201
202 PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n",
203 addr - PPC_IO_BASE, val);
204 switch (addr) {
205 case 0x0092:
206 /* Special port 92 */
207 /* Check soft reset asked */
208 if (val & 0x01) {
209 qemu_irq_raise(sysctrl->reset_irq);
210 } else {
211 qemu_irq_lower(sysctrl->reset_irq);
212 }
213 /* Check LE mode */
214 if (val & 0x02) {
215 sysctrl->endian = 1;
216 } else {
217 sysctrl->endian = 0;
218 }
219 break;
220 case 0x0800:
221 /* Motorola CPU configuration register : read-only */
222 break;
223 case 0x0802:
224 /* Motorola base module feature register : read-only */
225 break;
226 case 0x0803:
227 /* Motorola base module status register : read-only */
228 break;
229 case 0x0808:
230 /* Hardfile light register */
231 if (val & 1)
232 sysctrl->state |= STATE_HARDFILE;
233 else
234 sysctrl->state &= ~STATE_HARDFILE;
235 break;
236 case 0x0810:
237 /* Password protect 1 register */
238 if (sysctrl->nvram != NULL)
239 m48t59_toggle_lock(sysctrl->nvram, 1);
240 break;
241 case 0x0812:
242 /* Password protect 2 register */
243 if (sysctrl->nvram != NULL)
244 m48t59_toggle_lock(sysctrl->nvram, 2);
245 break;
246 case 0x0814:
247 /* L2 invalidate register */
248 // tlb_flush(first_cpu, 1);
249 break;
250 case 0x081C:
251 /* system control register */
252 sysctrl->syscontrol = val & 0x0F;
253 break;
254 case 0x0850:
255 /* I/O map type register */
256 sysctrl->contiguous_map = val & 0x01;
257 qemu_set_irq(sysctrl->contiguous_map_irq, sysctrl->contiguous_map);
258 break;
259 default:
260 printf("ERROR: unaffected IO port write: %04" PRIx32
261 " => %02" PRIx32"\n", addr, val);
262 break;
263 }
264 }
265
266 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
267 {
268 sysctrl_t *sysctrl = opaque;
269 uint32_t retval = 0xFF;
270
271 switch (addr) {
272 case 0x0092:
273 /* Special port 92 */
274 retval = sysctrl->endian << 1;
275 break;
276 case 0x0800:
277 /* Motorola CPU configuration register */
278 retval = 0xEF; /* MPC750 */
279 break;
280 case 0x0802:
281 /* Motorola Base module feature register */
282 retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
283 break;
284 case 0x0803:
285 /* Motorola base module status register */
286 retval = 0xE0; /* Standard MPC750 */
287 break;
288 case 0x080C:
289 /* Equipment present register:
290 * no L2 cache
291 * no upgrade processor
292 * no cards in PCI slots
293 * SCSI fuse is bad
294 */
295 retval = 0x3C;
296 break;
297 case 0x0810:
298 /* Motorola base module extended feature register */
299 retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
300 break;
301 case 0x0814:
302 /* L2 invalidate: don't care */
303 break;
304 case 0x0818:
305 /* Keylock */
306 retval = 0x00;
307 break;
308 case 0x081C:
309 /* system control register
310 * 7 - 6 / 1 - 0: L2 cache enable
311 */
312 retval = sysctrl->syscontrol;
313 break;
314 case 0x0823:
315 /* */
316 retval = 0x03; /* no L2 cache */
317 break;
318 case 0x0850:
319 /* I/O map type register */
320 retval = sysctrl->contiguous_map;
321 break;
322 default:
323 printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
324 break;
325 }
326 PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n",
327 addr - PPC_IO_BASE, retval);
328
329 return retval;
330 }
331
332
333 #define NVRAM_SIZE 0x2000
334
335 static void cpu_request_exit(void *opaque, int irq, int level)
336 {
337 CPUState *cpu = current_cpu;
338
339 if (cpu && level) {
340 cpu_exit(cpu);
341 }
342 }
343
344 static void ppc_prep_reset(void *opaque)
345 {
346 PowerPCCPU *cpu = opaque;
347
348 cpu_reset(CPU(cpu));
349
350 /* Reset address */
351 cpu->env.nip = 0xfffffffc;
352 }
353
354 static const MemoryRegionPortio prep_portio_list[] = {
355 /* System control ports */
356 { 0x0092, 1, 1, .read = PREP_io_800_readb, .write = PREP_io_800_writeb, },
357 { 0x0800, 0x52, 1,
358 .read = PREP_io_800_readb, .write = PREP_io_800_writeb, },
359 /* Special port to get debug messages from Open-Firmware */
360 { 0x0F00, 4, 1, .write = PPC_debug_write, },
361 PORTIO_END_OF_LIST(),
362 };
363
364 /* PowerPC PREP hardware initialisation */
365 static void ppc_prep_init(QEMUMachineInitArgs *args)
366 {
367 ram_addr_t ram_size = args->ram_size;
368 const char *cpu_model = args->cpu_model;
369 const char *kernel_filename = args->kernel_filename;
370 const char *kernel_cmdline = args->kernel_cmdline;
371 const char *initrd_filename = args->initrd_filename;
372 const char *boot_device = args->boot_order;
373 MemoryRegion *sysmem = get_system_memory();
374 PowerPCCPU *cpu = NULL;
375 CPUPPCState *env = NULL;
376 nvram_t nvram;
377 M48t59State *m48t59;
378 PortioList *port_list = g_new(PortioList, 1);
379 #if 0
380 MemoryRegion *xcsr = g_new(MemoryRegion, 1);
381 #endif
382 int linux_boot, i, nb_nics1;
383 MemoryRegion *ram = g_new(MemoryRegion, 1);
384 uint32_t kernel_base, initrd_base;
385 long kernel_size, initrd_size;
386 DeviceState *dev;
387 PCIHostState *pcihost;
388 PCIBus *pci_bus;
389 PCIDevice *pci;
390 ISABus *isa_bus;
391 ISADevice *isa;
392 qemu_irq *cpu_exit_irq;
393 int ppc_boot_device;
394 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
395
396 sysctrl = g_malloc0(sizeof(sysctrl_t));
397
398 linux_boot = (kernel_filename != NULL);
399
400 /* init CPUs */
401 if (cpu_model == NULL)
402 cpu_model = "602";
403 for (i = 0; i < smp_cpus; i++) {
404 cpu = cpu_ppc_init(cpu_model);
405 if (cpu == NULL) {
406 fprintf(stderr, "Unable to find PowerPC CPU definition\n");
407 exit(1);
408 }
409 env = &cpu->env;
410
411 if (env->flags & POWERPC_FLAG_RTC_CLK) {
412 /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
413 cpu_ppc_tb_init(env, 7812500UL);
414 } else {
415 /* Set time-base frequency to 100 Mhz */
416 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
417 }
418 qemu_register_reset(ppc_prep_reset, cpu);
419 }
420
421 /* allocate RAM */
422 memory_region_init_ram(ram, NULL, "ppc_prep.ram", ram_size);
423 vmstate_register_ram_global(ram);
424 memory_region_add_subregion(sysmem, 0, ram);
425
426 if (linux_boot) {
427 kernel_base = KERNEL_LOAD_ADDR;
428 /* now we can load the kernel */
429 kernel_size = load_image_targphys(kernel_filename, kernel_base,
430 ram_size - kernel_base);
431 if (kernel_size < 0) {
432 hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
433 exit(1);
434 }
435 /* load initrd */
436 if (initrd_filename) {
437 initrd_base = INITRD_LOAD_ADDR;
438 initrd_size = load_image_targphys(initrd_filename, initrd_base,
439 ram_size - initrd_base);
440 if (initrd_size < 0) {
441 hw_error("qemu: could not load initial ram disk '%s'\n",
442 initrd_filename);
443 }
444 } else {
445 initrd_base = 0;
446 initrd_size = 0;
447 }
448 ppc_boot_device = 'm';
449 } else {
450 kernel_base = 0;
451 kernel_size = 0;
452 initrd_base = 0;
453 initrd_size = 0;
454 ppc_boot_device = '\0';
455 /* For now, OHW cannot boot from the network. */
456 for (i = 0; boot_device[i] != '\0'; i++) {
457 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
458 ppc_boot_device = boot_device[i];
459 break;
460 }
461 }
462 if (ppc_boot_device == '\0') {
463 fprintf(stderr, "No valid boot device for Mac99 machine\n");
464 exit(1);
465 }
466 }
467
468 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
469 hw_error("Only 6xx bus is supported on PREP machine\n");
470 }
471
472 dev = qdev_create(NULL, "raven-pcihost");
473 if (bios_name == NULL) {
474 bios_name = BIOS_FILENAME;
475 }
476 qdev_prop_set_string(dev, "bios-name", bios_name);
477 qdev_prop_set_uint32(dev, "elf-machine", ELF_MACHINE);
478 pcihost = PCI_HOST_BRIDGE(dev);
479 object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
480 qdev_init_nofail(dev);
481 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
482 if (pci_bus == NULL) {
483 fprintf(stderr, "Couldn't create PCI host controller.\n");
484 exit(1);
485 }
486 sysctrl->contiguous_map_irq = qdev_get_gpio_in(dev, 0);
487
488 /* PCI -> ISA bridge */
489 pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378");
490 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
491 cpu = POWERPC_CPU(first_cpu);
492 qdev_connect_gpio_out(&pci->qdev, 0,
493 cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
494 qdev_connect_gpio_out(&pci->qdev, 1, *cpu_exit_irq);
495 sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9));
496 sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11));
497 sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9));
498 sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11));
499 isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci), "isa.0"));
500
501 /* Super I/O (parallel + serial ports) */
502 isa = isa_create(isa_bus, TYPE_PC87312);
503 dev = DEVICE(isa);
504 qdev_prop_set_uint8(dev, "config", 13); /* fdc, ser0, ser1, par0 */
505 qdev_init_nofail(dev);
506
507 /* init basic PC hardware */
508 pci_vga_init(pci_bus);
509
510 nb_nics1 = nb_nics;
511 if (nb_nics1 > NE2000_NB_MAX)
512 nb_nics1 = NE2000_NB_MAX;
513 for(i = 0; i < nb_nics1; i++) {
514 if (nd_table[i].model == NULL) {
515 nd_table[i].model = g_strdup("ne2k_isa");
516 }
517 if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
518 isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i],
519 &nd_table[i]);
520 } else {
521 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
522 }
523 }
524
525 ide_drive_get(hd, MAX_IDE_BUS);
526 for(i = 0; i < MAX_IDE_BUS; i++) {
527 isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i],
528 hd[2 * i],
529 hd[2 * i + 1]);
530 }
531 isa_create_simple(isa_bus, "i8042");
532
533 cpu = POWERPC_CPU(first_cpu);
534 sysctrl->reset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET];
535
536 portio_list_init(port_list, NULL, prep_portio_list, sysctrl, "prep");
537 portio_list_add(port_list, isa_address_space_io(isa), 0x0);
538
539 /* PowerPC control and status register group */
540 #if 0
541 memory_region_init_io(xcsr, NULL, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000);
542 memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr);
543 #endif
544
545 if (usb_enabled(false)) {
546 pci_create_simple(pci_bus, -1, "pci-ohci");
547 }
548
549 m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 59);
550 if (m48t59 == NULL)
551 return;
552 sysctrl->nvram = m48t59;
553
554 /* Initialise NVRAM */
555 nvram.opaque = m48t59;
556 nvram.read_fn = &m48t59_read;
557 nvram.write_fn = &m48t59_write;
558 PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device,
559 kernel_base, kernel_size,
560 kernel_cmdline,
561 initrd_base, initrd_size,
562 /* XXX: need an option to load a NVRAM image */
563 0,
564 graphic_width, graphic_height, graphic_depth);
565 }
566
567 static QEMUMachine prep_machine = {
568 .name = "prep",
569 .desc = "PowerPC PREP platform",
570 .init = ppc_prep_init,
571 .max_cpus = MAX_CPUS,
572 .default_boot_order = "cad",
573 };
574
575 static void prep_machine_init(void)
576 {
577 qemu_register_machine(&prep_machine);
578 }
579
580 machine_init(prep_machine_init);