meson: convert hw/vfio
[qemu.git] / hw / ppc / prep.c
1 /*
2 * QEMU PPC PREP hardware System Emulator
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (c) 2017 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 #include "qemu/osdep.h"
27 #include "cpu.h"
28 #include "hw/rtc/m48t59.h"
29 #include "hw/char/serial.h"
30 #include "hw/block/fdc.h"
31 #include "net/net.h"
32 #include "sysemu/sysemu.h"
33 #include "hw/isa/isa.h"
34 #include "hw/pci/pci.h"
35 #include "hw/pci/pci_host.h"
36 #include "hw/ppc/ppc.h"
37 #include "hw/boards.h"
38 #include "qapi/error.h"
39 #include "qemu/error-report.h"
40 #include "qemu/log.h"
41 #include "hw/irq.h"
42 #include "hw/loader.h"
43 #include "hw/rtc/mc146818rtc.h"
44 #include "hw/isa/pc87312.h"
45 #include "hw/qdev-properties.h"
46 #include "sysemu/arch_init.h"
47 #include "sysemu/kvm.h"
48 #include "sysemu/qtest.h"
49 #include "sysemu/reset.h"
50 #include "exec/address-spaces.h"
51 #include "trace.h"
52 #include "elf.h"
53 #include "qemu/units.h"
54 #include "kvm_ppc.h"
55
56 /* SMP is not enabled, for now */
57 #define MAX_CPUS 1
58
59 #define MAX_IDE_BUS 2
60
61 #define CFG_ADDR 0xf0000510
62
63 #define KERNEL_LOAD_ADDR 0x01000000
64 #define INITRD_LOAD_ADDR 0x01800000
65
66 #define NVRAM_SIZE 0x2000
67
68 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
69 Error **errp)
70 {
71 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
72 }
73
74 static void ppc_prep_reset(void *opaque)
75 {
76 PowerPCCPU *cpu = opaque;
77
78 cpu_reset(CPU(cpu));
79 }
80
81
82 /*****************************************************************************/
83 /* NVRAM helpers */
84 static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr)
85 {
86 NvramClass *k = NVRAM_GET_CLASS(nvram);
87 return (k->read)(nvram, addr);
88 }
89
90 static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val)
91 {
92 NvramClass *k = NVRAM_GET_CLASS(nvram);
93 (k->write)(nvram, addr, val);
94 }
95
96 static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value)
97 {
98 nvram_write(nvram, addr, value);
99 }
100
101 static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr)
102 {
103 return nvram_read(nvram, addr);
104 }
105
106 static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value)
107 {
108 nvram_write(nvram, addr, value >> 8);
109 nvram_write(nvram, addr + 1, value & 0xFF);
110 }
111
112 static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr)
113 {
114 uint16_t tmp;
115
116 tmp = nvram_read(nvram, addr) << 8;
117 tmp |= nvram_read(nvram, addr + 1);
118
119 return tmp;
120 }
121
122 static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value)
123 {
124 nvram_write(nvram, addr, value >> 24);
125 nvram_write(nvram, addr + 1, (value >> 16) & 0xFF);
126 nvram_write(nvram, addr + 2, (value >> 8) & 0xFF);
127 nvram_write(nvram, addr + 3, value & 0xFF);
128 }
129
130 static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str,
131 uint32_t max)
132 {
133 int i;
134
135 for (i = 0; i < max && str[i] != '\0'; i++) {
136 nvram_write(nvram, addr + i, str[i]);
137 }
138 nvram_write(nvram, addr + i, str[i]);
139 nvram_write(nvram, addr + max - 1, '\0');
140 }
141
142 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
143 {
144 uint16_t tmp;
145 uint16_t pd, pd1, pd2;
146
147 tmp = prev >> 8;
148 pd = prev ^ value;
149 pd1 = pd & 0x000F;
150 pd2 = ((pd >> 4) & 0x000F) ^ pd1;
151 tmp ^= (pd1 << 3) | (pd1 << 8);
152 tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
153
154 return tmp;
155 }
156
157 static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count)
158 {
159 uint32_t i;
160 uint16_t crc = 0xFFFF;
161 int odd;
162
163 odd = count & 1;
164 count &= ~1;
165 for (i = 0; i != count; i++) {
166 crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
167 }
168 if (odd) {
169 crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
170 }
171
172 return crc;
173 }
174
175 #define CMDLINE_ADDR 0x017ff000
176
177 static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size,
178 const char *arch,
179 uint32_t RAM_size, int boot_device,
180 uint32_t kernel_image, uint32_t kernel_size,
181 const char *cmdline,
182 uint32_t initrd_image, uint32_t initrd_size,
183 uint32_t NVRAM_image,
184 int width, int height, int depth)
185 {
186 uint16_t crc;
187
188 /* Set parameters for Open Hack'Ware BIOS */
189 NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
190 NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */
191 NVRAM_set_word(nvram, 0x14, NVRAM_size);
192 NVRAM_set_string(nvram, 0x20, arch, 16);
193 NVRAM_set_lword(nvram, 0x30, RAM_size);
194 NVRAM_set_byte(nvram, 0x34, boot_device);
195 NVRAM_set_lword(nvram, 0x38, kernel_image);
196 NVRAM_set_lword(nvram, 0x3C, kernel_size);
197 if (cmdline) {
198 /* XXX: put the cmdline in NVRAM too ? */
199 pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR,
200 cmdline);
201 NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
202 NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
203 } else {
204 NVRAM_set_lword(nvram, 0x40, 0);
205 NVRAM_set_lword(nvram, 0x44, 0);
206 }
207 NVRAM_set_lword(nvram, 0x48, initrd_image);
208 NVRAM_set_lword(nvram, 0x4C, initrd_size);
209 NVRAM_set_lword(nvram, 0x50, NVRAM_image);
210
211 NVRAM_set_word(nvram, 0x54, width);
212 NVRAM_set_word(nvram, 0x56, height);
213 NVRAM_set_word(nvram, 0x58, depth);
214 crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
215 NVRAM_set_word(nvram, 0xFC, crc);
216
217 return 0;
218 }
219
220 static int prep_set_cmos_checksum(DeviceState *dev, void *opaque)
221 {
222 uint16_t checksum = *(uint16_t *)opaque;
223 ISADevice *rtc;
224
225 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
226 rtc = ISA_DEVICE(dev);
227 rtc_set_memory(rtc, 0x2e, checksum & 0xff);
228 rtc_set_memory(rtc, 0x3e, checksum & 0xff);
229 rtc_set_memory(rtc, 0x2f, checksum >> 8);
230 rtc_set_memory(rtc, 0x3f, checksum >> 8);
231
232 object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(rtc),
233 "date");
234 }
235 return 0;
236 }
237
238 static void ibm_40p_init(MachineState *machine)
239 {
240 CPUPPCState *env = NULL;
241 uint16_t cmos_checksum;
242 PowerPCCPU *cpu;
243 DeviceState *dev, *i82378_dev;
244 SysBusDevice *pcihost, *s;
245 Nvram *m48t59 = NULL;
246 PCIBus *pci_bus;
247 ISADevice *isa_dev;
248 ISABus *isa_bus;
249 void *fw_cfg;
250 int i;
251 uint32_t kernel_base = 0, initrd_base = 0;
252 long kernel_size = 0, initrd_size = 0;
253 char boot_device;
254
255 /* init CPU */
256 cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
257 env = &cpu->env;
258 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
259 error_report("only 6xx bus is supported on this machine");
260 exit(1);
261 }
262
263 if (env->flags & POWERPC_FLAG_RTC_CLK) {
264 /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
265 cpu_ppc_tb_init(env, 7812500UL);
266 } else {
267 /* Set time-base frequency to 100 Mhz */
268 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
269 }
270 qemu_register_reset(ppc_prep_reset, cpu);
271
272 /* PCI host */
273 dev = qdev_new("raven-pcihost");
274 if (!bios_name) {
275 bios_name = "openbios-ppc";
276 }
277 qdev_prop_set_string(dev, "bios-name", bios_name);
278 qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
279 pcihost = SYS_BUS_DEVICE(dev);
280 object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev));
281 sysbus_realize_and_unref(pcihost, &error_fatal);
282 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0"));
283 if (!pci_bus) {
284 error_report("could not create PCI host controller");
285 exit(1);
286 }
287
288 /* PCI -> ISA bridge */
289 i82378_dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(11, 0), "i82378"));
290 qdev_connect_gpio_out(i82378_dev, 0,
291 cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
292 sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(i82378_dev, 15));
293 isa_bus = ISA_BUS(qdev_get_child_bus(i82378_dev, "isa.0"));
294
295 /* Memory controller */
296 isa_dev = isa_new("rs6000-mc");
297 dev = DEVICE(isa_dev);
298 qdev_prop_set_uint32(dev, "ram-size", machine->ram_size);
299 isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
300
301 /* RTC */
302 isa_dev = isa_new(TYPE_MC146818_RTC);
303 dev = DEVICE(isa_dev);
304 qdev_prop_set_int32(dev, "base_year", 1900);
305 isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
306
307 /* initialize CMOS checksums */
308 cmos_checksum = 0x6aa9;
309 qbus_walk_children(BUS(isa_bus), prep_set_cmos_checksum, NULL, NULL, NULL,
310 &cmos_checksum);
311
312 /* add some more devices */
313 if (defaults_enabled()) {
314 m48t59 = NVRAM(isa_create_simple(isa_bus, "isa-m48t59"));
315
316 isa_dev = isa_new("cs4231a");
317 dev = DEVICE(isa_dev);
318 qdev_prop_set_uint32(dev, "iobase", 0x830);
319 qdev_prop_set_uint32(dev, "irq", 10);
320 isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
321
322 isa_dev = isa_new("pc87312");
323 dev = DEVICE(isa_dev);
324 qdev_prop_set_uint32(dev, "config", 12);
325 isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
326
327 isa_dev = isa_new("prep-systemio");
328 dev = DEVICE(isa_dev);
329 qdev_prop_set_uint32(dev, "ibm-planar-id", 0xfc);
330 qdev_prop_set_uint32(dev, "equipment", 0xc0);
331 isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
332
333 dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(1, 0),
334 "lsi53c810"));
335 lsi53c8xx_handle_legacy_cmdline(dev);
336 qdev_connect_gpio_out(dev, 0, qdev_get_gpio_in(i82378_dev, 13));
337
338 /* XXX: s3-trio at PCI_DEVFN(2, 0) */
339 pci_vga_init(pci_bus);
340
341 for (i = 0; i < nb_nics; i++) {
342 pci_nic_init_nofail(&nd_table[i], pci_bus, "pcnet",
343 i == 0 ? "3" : NULL);
344 }
345 }
346
347 /* Prepare firmware configuration for OpenBIOS */
348 dev = qdev_new(TYPE_FW_CFG_MEM);
349 fw_cfg = FW_CFG(dev);
350 qdev_prop_set_uint32(dev, "data_width", 1);
351 qdev_prop_set_bit(dev, "dma_enabled", false);
352 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
353 OBJECT(fw_cfg));
354 s = SYS_BUS_DEVICE(dev);
355 sysbus_realize_and_unref(s, &error_fatal);
356 sysbus_mmio_map(s, 0, CFG_ADDR);
357 sysbus_mmio_map(s, 1, CFG_ADDR + 2);
358
359 if (machine->kernel_filename) {
360 /* load kernel */
361 kernel_base = KERNEL_LOAD_ADDR;
362 kernel_size = load_image_targphys(machine->kernel_filename,
363 kernel_base,
364 machine->ram_size - kernel_base);
365 if (kernel_size < 0) {
366 error_report("could not load kernel '%s'",
367 machine->kernel_filename);
368 exit(1);
369 }
370 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
371 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
372 /* load initrd */
373 if (machine->initrd_filename) {
374 initrd_base = INITRD_LOAD_ADDR;
375 initrd_size = load_image_targphys(machine->initrd_filename,
376 initrd_base,
377 machine->ram_size - initrd_base);
378 if (initrd_size < 0) {
379 error_report("could not load initial ram disk '%s'",
380 machine->initrd_filename);
381 exit(1);
382 }
383 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
384 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
385 }
386 if (machine->kernel_cmdline && *machine->kernel_cmdline) {
387 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
388 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
389 machine->kernel_cmdline);
390 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
391 machine->kernel_cmdline);
392 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
393 strlen(machine->kernel_cmdline) + 1);
394 }
395 boot_device = 'm';
396 } else {
397 boot_device = machine->boot_order[0];
398 }
399
400 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
401 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
402 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_PREP);
403
404 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
405 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
406 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
407
408 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
409 if (kvm_enabled()) {
410 uint8_t *hypercall;
411
412 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq());
413 hypercall = g_malloc(16);
414 kvmppc_get_hypercall(env, hypercall, 16);
415 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
416 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
417 } else {
418 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, NANOSECONDS_PER_SECOND);
419 }
420 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device);
421 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
422
423 /* Prepare firmware configuration for Open Hack'Ware */
424 if (m48t59) {
425 PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", ram_size,
426 boot_device,
427 kernel_base, kernel_size,
428 machine->kernel_cmdline,
429 initrd_base, initrd_size,
430 /* XXX: need an option to load a NVRAM image */
431 0,
432 graphic_width, graphic_height, graphic_depth);
433 }
434 }
435
436 static void ibm_40p_machine_init(MachineClass *mc)
437 {
438 mc->desc = "IBM RS/6000 7020 (40p)",
439 mc->init = ibm_40p_init;
440 mc->max_cpus = 1;
441 mc->default_ram_size = 128 * MiB;
442 mc->block_default_type = IF_SCSI;
443 mc->default_boot_order = "c";
444 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("604");
445 mc->default_display = "std";
446 }
447
448 DEFINE_MACHINE("40p", ibm_40p_machine_init)