raven: Move BIOS loading from board code to PCI host
[qemu.git] / hw / ppc / prep.c
1 /*
2 * QEMU PPC PREP hardware System Emulator
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw/hw.h"
25 #include "hw/timer/m48t59.h"
26 #include "hw/i386/pc.h"
27 #include "hw/char/serial.h"
28 #include "hw/block/fdc.h"
29 #include "net/net.h"
30 #include "sysemu/sysemu.h"
31 #include "hw/isa/isa.h"
32 #include "hw/pci/pci.h"
33 #include "hw/pci/pci_host.h"
34 #include "hw/ppc/ppc.h"
35 #include "hw/boards.h"
36 #include "qemu/log.h"
37 #include "hw/ide.h"
38 #include "hw/loader.h"
39 #include "hw/timer/mc146818rtc.h"
40 #include "hw/isa/pc87312.h"
41 #include "sysemu/blockdev.h"
42 #include "sysemu/arch_init.h"
43 #include "sysemu/qtest.h"
44 #include "exec/address-spaces.h"
45 #include "elf.h"
46
47 //#define HARD_DEBUG_PPC_IO
48 //#define DEBUG_PPC_IO
49
50 /* SMP is not enabled, for now */
51 #define MAX_CPUS 1
52
53 #define MAX_IDE_BUS 2
54
55 #define BIOS_SIZE (1024 * 1024)
56 #define BIOS_FILENAME "ppc_rom.bin"
57 #define KERNEL_LOAD_ADDR 0x01000000
58 #define INITRD_LOAD_ADDR 0x01800000
59
60 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
61 #define DEBUG_PPC_IO
62 #endif
63
64 #if defined (HARD_DEBUG_PPC_IO)
65 #define PPC_IO_DPRINTF(fmt, ...) \
66 do { \
67 if (qemu_loglevel_mask(CPU_LOG_IOPORT)) { \
68 qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \
69 } else { \
70 printf("%s : " fmt, __func__ , ## __VA_ARGS__); \
71 } \
72 } while (0)
73 #elif defined (DEBUG_PPC_IO)
74 #define PPC_IO_DPRINTF(fmt, ...) \
75 qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__)
76 #else
77 #define PPC_IO_DPRINTF(fmt, ...) do { } while (0)
78 #endif
79
80 /* Constants for devices init */
81 static const int ide_iobase[2] = { 0x1f0, 0x170 };
82 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
83 static const int ide_irq[2] = { 13, 13 };
84
85 #define NE2000_NB_MAX 6
86
87 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
88 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
89
90 /* ISA IO ports bridge */
91 #define PPC_IO_BASE 0x80000000
92
93 /* PowerPC control and status registers */
94 #if 0 // Not used
95 static struct {
96 /* IDs */
97 uint32_t veni_devi;
98 uint32_t revi;
99 /* Control and status */
100 uint32_t gcsr;
101 uint32_t xcfr;
102 uint32_t ct32;
103 uint32_t mcsr;
104 /* General purpose registers */
105 uint32_t gprg[6];
106 /* Exceptions */
107 uint32_t feen;
108 uint32_t fest;
109 uint32_t fema;
110 uint32_t fecl;
111 uint32_t eeen;
112 uint32_t eest;
113 uint32_t eecl;
114 uint32_t eeint;
115 uint32_t eemck0;
116 uint32_t eemck1;
117 /* Error diagnostic */
118 } XCSR;
119
120 static void PPC_XCSR_writeb (void *opaque,
121 hwaddr addr, uint32_t value)
122 {
123 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
124 value);
125 }
126
127 static void PPC_XCSR_writew (void *opaque,
128 hwaddr addr, uint32_t value)
129 {
130 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
131 value);
132 }
133
134 static void PPC_XCSR_writel (void *opaque,
135 hwaddr addr, uint32_t value)
136 {
137 printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
138 value);
139 }
140
141 static uint32_t PPC_XCSR_readb (void *opaque, hwaddr addr)
142 {
143 uint32_t retval = 0;
144
145 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
146 retval);
147
148 return retval;
149 }
150
151 static uint32_t PPC_XCSR_readw (void *opaque, hwaddr addr)
152 {
153 uint32_t retval = 0;
154
155 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
156 retval);
157
158 return retval;
159 }
160
161 static uint32_t PPC_XCSR_readl (void *opaque, hwaddr addr)
162 {
163 uint32_t retval = 0;
164
165 printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
166 retval);
167
168 return retval;
169 }
170
171 static const MemoryRegionOps PPC_XCSR_ops = {
172 .old_mmio = {
173 .read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, },
174 .write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, },
175 },
176 .endianness = DEVICE_LITTLE_ENDIAN,
177 };
178
179 #endif
180
181 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
182 typedef struct sysctrl_t {
183 qemu_irq reset_irq;
184 M48t59State *nvram;
185 uint8_t state;
186 uint8_t syscontrol;
187 int contiguous_map;
188 int endian;
189 } sysctrl_t;
190
191 enum {
192 STATE_HARDFILE = 0x01,
193 };
194
195 static sysctrl_t *sysctrl;
196
197 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
198 {
199 sysctrl_t *sysctrl = opaque;
200
201 PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n",
202 addr - PPC_IO_BASE, val);
203 switch (addr) {
204 case 0x0092:
205 /* Special port 92 */
206 /* Check soft reset asked */
207 if (val & 0x01) {
208 qemu_irq_raise(sysctrl->reset_irq);
209 } else {
210 qemu_irq_lower(sysctrl->reset_irq);
211 }
212 /* Check LE mode */
213 if (val & 0x02) {
214 sysctrl->endian = 1;
215 } else {
216 sysctrl->endian = 0;
217 }
218 break;
219 case 0x0800:
220 /* Motorola CPU configuration register : read-only */
221 break;
222 case 0x0802:
223 /* Motorola base module feature register : read-only */
224 break;
225 case 0x0803:
226 /* Motorola base module status register : read-only */
227 break;
228 case 0x0808:
229 /* Hardfile light register */
230 if (val & 1)
231 sysctrl->state |= STATE_HARDFILE;
232 else
233 sysctrl->state &= ~STATE_HARDFILE;
234 break;
235 case 0x0810:
236 /* Password protect 1 register */
237 if (sysctrl->nvram != NULL)
238 m48t59_toggle_lock(sysctrl->nvram, 1);
239 break;
240 case 0x0812:
241 /* Password protect 2 register */
242 if (sysctrl->nvram != NULL)
243 m48t59_toggle_lock(sysctrl->nvram, 2);
244 break;
245 case 0x0814:
246 /* L2 invalidate register */
247 // tlb_flush(first_cpu, 1);
248 break;
249 case 0x081C:
250 /* system control register */
251 sysctrl->syscontrol = val & 0x0F;
252 break;
253 case 0x0850:
254 /* I/O map type register */
255 sysctrl->contiguous_map = val & 0x01;
256 break;
257 default:
258 printf("ERROR: unaffected IO port write: %04" PRIx32
259 " => %02" PRIx32"\n", addr, val);
260 break;
261 }
262 }
263
264 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
265 {
266 sysctrl_t *sysctrl = opaque;
267 uint32_t retval = 0xFF;
268
269 switch (addr) {
270 case 0x0092:
271 /* Special port 92 */
272 retval = sysctrl->endian << 1;
273 break;
274 case 0x0800:
275 /* Motorola CPU configuration register */
276 retval = 0xEF; /* MPC750 */
277 break;
278 case 0x0802:
279 /* Motorola Base module feature register */
280 retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
281 break;
282 case 0x0803:
283 /* Motorola base module status register */
284 retval = 0xE0; /* Standard MPC750 */
285 break;
286 case 0x080C:
287 /* Equipment present register:
288 * no L2 cache
289 * no upgrade processor
290 * no cards in PCI slots
291 * SCSI fuse is bad
292 */
293 retval = 0x3C;
294 break;
295 case 0x0810:
296 /* Motorola base module extended feature register */
297 retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
298 break;
299 case 0x0814:
300 /* L2 invalidate: don't care */
301 break;
302 case 0x0818:
303 /* Keylock */
304 retval = 0x00;
305 break;
306 case 0x081C:
307 /* system control register
308 * 7 - 6 / 1 - 0: L2 cache enable
309 */
310 retval = sysctrl->syscontrol;
311 break;
312 case 0x0823:
313 /* */
314 retval = 0x03; /* no L2 cache */
315 break;
316 case 0x0850:
317 /* I/O map type register */
318 retval = sysctrl->contiguous_map;
319 break;
320 default:
321 printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
322 break;
323 }
324 PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n",
325 addr - PPC_IO_BASE, retval);
326
327 return retval;
328 }
329
330 static inline hwaddr prep_IO_address(sysctrl_t *sysctrl,
331 hwaddr addr)
332 {
333 if (sysctrl->contiguous_map == 0) {
334 /* 64 KB contiguous space for IOs */
335 addr &= 0xFFFF;
336 } else {
337 /* 8 MB non-contiguous space for IOs */
338 addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
339 }
340
341 return addr;
342 }
343
344 static void PPC_prep_io_writeb (void *opaque, hwaddr addr,
345 uint32_t value)
346 {
347 sysctrl_t *sysctrl = opaque;
348
349 addr = prep_IO_address(sysctrl, addr);
350 cpu_outb(addr, value);
351 }
352
353 static uint32_t PPC_prep_io_readb (void *opaque, hwaddr addr)
354 {
355 sysctrl_t *sysctrl = opaque;
356 uint32_t ret;
357
358 addr = prep_IO_address(sysctrl, addr);
359 ret = cpu_inb(addr);
360
361 return ret;
362 }
363
364 static void PPC_prep_io_writew (void *opaque, hwaddr addr,
365 uint32_t value)
366 {
367 sysctrl_t *sysctrl = opaque;
368
369 addr = prep_IO_address(sysctrl, addr);
370 PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
371 cpu_outw(addr, value);
372 }
373
374 static uint32_t PPC_prep_io_readw (void *opaque, hwaddr addr)
375 {
376 sysctrl_t *sysctrl = opaque;
377 uint32_t ret;
378
379 addr = prep_IO_address(sysctrl, addr);
380 ret = cpu_inw(addr);
381 PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
382
383 return ret;
384 }
385
386 static void PPC_prep_io_writel (void *opaque, hwaddr addr,
387 uint32_t value)
388 {
389 sysctrl_t *sysctrl = opaque;
390
391 addr = prep_IO_address(sysctrl, addr);
392 PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
393 cpu_outl(addr, value);
394 }
395
396 static uint32_t PPC_prep_io_readl (void *opaque, hwaddr addr)
397 {
398 sysctrl_t *sysctrl = opaque;
399 uint32_t ret;
400
401 addr = prep_IO_address(sysctrl, addr);
402 ret = cpu_inl(addr);
403 PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
404
405 return ret;
406 }
407
408 static const MemoryRegionOps PPC_prep_io_ops = {
409 .old_mmio = {
410 .read = { PPC_prep_io_readb, PPC_prep_io_readw, PPC_prep_io_readl },
411 .write = { PPC_prep_io_writeb, PPC_prep_io_writew, PPC_prep_io_writel },
412 },
413 .endianness = DEVICE_NATIVE_ENDIAN,
414 };
415
416 #define NVRAM_SIZE 0x2000
417
418 static void cpu_request_exit(void *opaque, int irq, int level)
419 {
420 CPUState *cpu = current_cpu;
421
422 if (cpu && level) {
423 cpu_exit(cpu);
424 }
425 }
426
427 static void ppc_prep_reset(void *opaque)
428 {
429 PowerPCCPU *cpu = opaque;
430
431 cpu_reset(CPU(cpu));
432
433 /* Reset address */
434 cpu->env.nip = 0xfffffffc;
435 }
436
437 static const MemoryRegionPortio prep_portio_list[] = {
438 /* System control ports */
439 { 0x0092, 1, 1, .read = PREP_io_800_readb, .write = PREP_io_800_writeb, },
440 { 0x0800, 0x52, 1,
441 .read = PREP_io_800_readb, .write = PREP_io_800_writeb, },
442 /* Special port to get debug messages from Open-Firmware */
443 { 0x0F00, 4, 1, .write = PPC_debug_write, },
444 PORTIO_END_OF_LIST(),
445 };
446
447 /* PowerPC PREP hardware initialisation */
448 static void ppc_prep_init(QEMUMachineInitArgs *args)
449 {
450 ram_addr_t ram_size = args->ram_size;
451 const char *cpu_model = args->cpu_model;
452 const char *kernel_filename = args->kernel_filename;
453 const char *kernel_cmdline = args->kernel_cmdline;
454 const char *initrd_filename = args->initrd_filename;
455 const char *boot_device = args->boot_order;
456 MemoryRegion *sysmem = get_system_memory();
457 PowerPCCPU *cpu = NULL;
458 CPUPPCState *env = NULL;
459 nvram_t nvram;
460 M48t59State *m48t59;
461 MemoryRegion *PPC_io_memory = g_new(MemoryRegion, 1);
462 PortioList *port_list = g_new(PortioList, 1);
463 #if 0
464 MemoryRegion *xcsr = g_new(MemoryRegion, 1);
465 #endif
466 int linux_boot, i, nb_nics1;
467 MemoryRegion *ram = g_new(MemoryRegion, 1);
468 uint32_t kernel_base, initrd_base;
469 long kernel_size, initrd_size;
470 DeviceState *dev;
471 PCIHostState *pcihost;
472 PCIBus *pci_bus;
473 PCIDevice *pci;
474 ISABus *isa_bus;
475 ISADevice *isa;
476 qemu_irq *cpu_exit_irq;
477 int ppc_boot_device;
478 DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
479
480 sysctrl = g_malloc0(sizeof(sysctrl_t));
481
482 linux_boot = (kernel_filename != NULL);
483
484 /* init CPUs */
485 if (cpu_model == NULL)
486 cpu_model = "602";
487 for (i = 0; i < smp_cpus; i++) {
488 cpu = cpu_ppc_init(cpu_model);
489 if (cpu == NULL) {
490 fprintf(stderr, "Unable to find PowerPC CPU definition\n");
491 exit(1);
492 }
493 env = &cpu->env;
494
495 if (env->flags & POWERPC_FLAG_RTC_CLK) {
496 /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
497 cpu_ppc_tb_init(env, 7812500UL);
498 } else {
499 /* Set time-base frequency to 100 Mhz */
500 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
501 }
502 qemu_register_reset(ppc_prep_reset, cpu);
503 }
504
505 /* allocate RAM */
506 memory_region_init_ram(ram, NULL, "ppc_prep.ram", ram_size);
507 vmstate_register_ram_global(ram);
508 memory_region_add_subregion(sysmem, 0, ram);
509
510 if (linux_boot) {
511 kernel_base = KERNEL_LOAD_ADDR;
512 /* now we can load the kernel */
513 kernel_size = load_image_targphys(kernel_filename, kernel_base,
514 ram_size - kernel_base);
515 if (kernel_size < 0) {
516 hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
517 exit(1);
518 }
519 /* load initrd */
520 if (initrd_filename) {
521 initrd_base = INITRD_LOAD_ADDR;
522 initrd_size = load_image_targphys(initrd_filename, initrd_base,
523 ram_size - initrd_base);
524 if (initrd_size < 0) {
525 hw_error("qemu: could not load initial ram disk '%s'\n",
526 initrd_filename);
527 }
528 } else {
529 initrd_base = 0;
530 initrd_size = 0;
531 }
532 ppc_boot_device = 'm';
533 } else {
534 kernel_base = 0;
535 kernel_size = 0;
536 initrd_base = 0;
537 initrd_size = 0;
538 ppc_boot_device = '\0';
539 /* For now, OHW cannot boot from the network. */
540 for (i = 0; boot_device[i] != '\0'; i++) {
541 if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
542 ppc_boot_device = boot_device[i];
543 break;
544 }
545 }
546 if (ppc_boot_device == '\0') {
547 fprintf(stderr, "No valid boot device for Mac99 machine\n");
548 exit(1);
549 }
550 }
551
552 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
553 hw_error("Only 6xx bus is supported on PREP machine\n");
554 }
555
556 dev = qdev_create(NULL, "raven-pcihost");
557 if (bios_name == NULL) {
558 bios_name = BIOS_FILENAME;
559 }
560 qdev_prop_set_string(dev, "bios-name", bios_name);
561 qdev_prop_set_uint32(dev, "elf-machine", ELF_MACHINE);
562 pcihost = PCI_HOST_BRIDGE(dev);
563 object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
564 qdev_init_nofail(dev);
565 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
566 if (pci_bus == NULL) {
567 fprintf(stderr, "Couldn't create PCI host controller.\n");
568 exit(1);
569 }
570
571 /* PCI -> ISA bridge */
572 pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378");
573 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
574 cpu = POWERPC_CPU(first_cpu);
575 qdev_connect_gpio_out(&pci->qdev, 0,
576 cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
577 qdev_connect_gpio_out(&pci->qdev, 1, *cpu_exit_irq);
578 sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9));
579 sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11));
580 sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9));
581 sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11));
582 isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(pci), "isa.0"));
583
584 /* Super I/O (parallel + serial ports) */
585 isa = isa_create(isa_bus, TYPE_PC87312);
586 dev = DEVICE(isa);
587 qdev_prop_set_uint8(dev, "config", 13); /* fdc, ser0, ser1, par0 */
588 qdev_init_nofail(dev);
589
590 /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
591 memory_region_init_io(PPC_io_memory, NULL, &PPC_prep_io_ops, sysctrl,
592 "ppc-io", 0x00800000);
593 memory_region_add_subregion(sysmem, 0x80000000, PPC_io_memory);
594
595 /* init basic PC hardware */
596 pci_vga_init(pci_bus);
597
598 nb_nics1 = nb_nics;
599 if (nb_nics1 > NE2000_NB_MAX)
600 nb_nics1 = NE2000_NB_MAX;
601 for(i = 0; i < nb_nics1; i++) {
602 if (nd_table[i].model == NULL) {
603 nd_table[i].model = g_strdup("ne2k_isa");
604 }
605 if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
606 isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i],
607 &nd_table[i]);
608 } else {
609 pci_nic_init_nofail(&nd_table[i], pci_bus, "ne2k_pci", NULL);
610 }
611 }
612
613 ide_drive_get(hd, MAX_IDE_BUS);
614 for(i = 0; i < MAX_IDE_BUS; i++) {
615 isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i],
616 hd[2 * i],
617 hd[2 * i + 1]);
618 }
619 isa_create_simple(isa_bus, "i8042");
620
621 cpu = POWERPC_CPU(first_cpu);
622 sysctrl->reset_irq = cpu->env.irq_inputs[PPC6xx_INPUT_HRESET];
623
624 portio_list_init(port_list, NULL, prep_portio_list, sysctrl, "prep");
625 portio_list_add(port_list, isa_address_space_io(isa), 0x0);
626
627 /* PowerPC control and status register group */
628 #if 0
629 memory_region_init_io(xcsr, NULL, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000);
630 memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr);
631 #endif
632
633 if (usb_enabled(false)) {
634 pci_create_simple(pci_bus, -1, "pci-ohci");
635 }
636
637 m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 59);
638 if (m48t59 == NULL)
639 return;
640 sysctrl->nvram = m48t59;
641
642 /* Initialise NVRAM */
643 nvram.opaque = m48t59;
644 nvram.read_fn = &m48t59_read;
645 nvram.write_fn = &m48t59_write;
646 PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device,
647 kernel_base, kernel_size,
648 kernel_cmdline,
649 initrd_base, initrd_size,
650 /* XXX: need an option to load a NVRAM image */
651 0,
652 graphic_width, graphic_height, graphic_depth);
653 }
654
655 static QEMUMachine prep_machine = {
656 .name = "prep",
657 .desc = "PowerPC PREP platform",
658 .init = ppc_prep_init,
659 .max_cpus = MAX_CPUS,
660 .default_boot_order = "cad",
661 };
662
663 static void prep_machine_init(void)
664 {
665 qemu_register_machine(&prep_machine);
666 }
667
668 machine_init(prep_machine_init);