Merge tag 'pull-target-arm-20220809' of https://git.linaro.org/people/pmaydell/qemu...
[qemu.git] / hw / ppc / prep.c
1 /*
2 * QEMU PPC PREP hardware System Emulator
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (c) 2017 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 #include "qemu/osdep.h"
27 #include "hw/rtc/m48t59.h"
28 #include "hw/char/serial.h"
29 #include "hw/block/fdc.h"
30 #include "net/net.h"
31 #include "hw/isa/isa.h"
32 #include "hw/pci/pci.h"
33 #include "hw/pci/pci_host.h"
34 #include "hw/ppc/ppc.h"
35 #include "hw/boards.h"
36 #include "qapi/error.h"
37 #include "qemu/error-report.h"
38 #include "qemu/log.h"
39 #include "hw/loader.h"
40 #include "hw/rtc/mc146818rtc.h"
41 #include "hw/isa/pc87312.h"
42 #include "hw/qdev-properties.h"
43 #include "sysemu/kvm.h"
44 #include "sysemu/reset.h"
45 #include "trace.h"
46 #include "elf.h"
47 #include "qemu/units.h"
48 #include "kvm_ppc.h"
49
50 /* SMP is not enabled, for now */
51 #define MAX_CPUS 1
52
53 #define MAX_IDE_BUS 2
54
55 #define CFG_ADDR 0xf0000510
56
57 #define KERNEL_LOAD_ADDR 0x01000000
58 #define INITRD_LOAD_ADDR 0x01800000
59
60 #define NVRAM_SIZE 0x2000
61
62 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
63 Error **errp)
64 {
65 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
66 }
67
68 static void ppc_prep_reset(void *opaque)
69 {
70 PowerPCCPU *cpu = opaque;
71
72 cpu_reset(CPU(cpu));
73 }
74
75
76 /*****************************************************************************/
77 /* NVRAM helpers */
78 static inline uint32_t nvram_read(Nvram *nvram, uint32_t addr)
79 {
80 NvramClass *k = NVRAM_GET_CLASS(nvram);
81 return (k->read)(nvram, addr);
82 }
83
84 static inline void nvram_write(Nvram *nvram, uint32_t addr, uint32_t val)
85 {
86 NvramClass *k = NVRAM_GET_CLASS(nvram);
87 (k->write)(nvram, addr, val);
88 }
89
90 static void NVRAM_set_byte(Nvram *nvram, uint32_t addr, uint8_t value)
91 {
92 nvram_write(nvram, addr, value);
93 }
94
95 static uint8_t NVRAM_get_byte(Nvram *nvram, uint32_t addr)
96 {
97 return nvram_read(nvram, addr);
98 }
99
100 static void NVRAM_set_word(Nvram *nvram, uint32_t addr, uint16_t value)
101 {
102 nvram_write(nvram, addr, value >> 8);
103 nvram_write(nvram, addr + 1, value & 0xFF);
104 }
105
106 static uint16_t NVRAM_get_word(Nvram *nvram, uint32_t addr)
107 {
108 uint16_t tmp;
109
110 tmp = nvram_read(nvram, addr) << 8;
111 tmp |= nvram_read(nvram, addr + 1);
112
113 return tmp;
114 }
115
116 static void NVRAM_set_lword(Nvram *nvram, uint32_t addr, uint32_t value)
117 {
118 nvram_write(nvram, addr, value >> 24);
119 nvram_write(nvram, addr + 1, (value >> 16) & 0xFF);
120 nvram_write(nvram, addr + 2, (value >> 8) & 0xFF);
121 nvram_write(nvram, addr + 3, value & 0xFF);
122 }
123
124 static void NVRAM_set_string(Nvram *nvram, uint32_t addr, const char *str,
125 uint32_t max)
126 {
127 int i;
128
129 for (i = 0; i < max && str[i] != '\0'; i++) {
130 nvram_write(nvram, addr + i, str[i]);
131 }
132 nvram_write(nvram, addr + i, str[i]);
133 nvram_write(nvram, addr + max - 1, '\0');
134 }
135
136 static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
137 {
138 uint16_t tmp;
139 uint16_t pd, pd1, pd2;
140
141 tmp = prev >> 8;
142 pd = prev ^ value;
143 pd1 = pd & 0x000F;
144 pd2 = ((pd >> 4) & 0x000F) ^ pd1;
145 tmp ^= (pd1 << 3) | (pd1 << 8);
146 tmp ^= pd2 | (pd2 << 7) | (pd2 << 12);
147
148 return tmp;
149 }
150
151 static uint16_t NVRAM_compute_crc (Nvram *nvram, uint32_t start, uint32_t count)
152 {
153 uint32_t i;
154 uint16_t crc = 0xFFFF;
155 int odd;
156
157 odd = count & 1;
158 count &= ~1;
159 for (i = 0; i != count; i++) {
160 crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i));
161 }
162 if (odd) {
163 crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
164 }
165
166 return crc;
167 }
168
169 #define CMDLINE_ADDR 0x017ff000
170
171 static int PPC_NVRAM_set_params (Nvram *nvram, uint16_t NVRAM_size,
172 const char *arch,
173 uint32_t RAM_size, int boot_device,
174 uint32_t kernel_image, uint32_t kernel_size,
175 const char *cmdline,
176 uint32_t initrd_image, uint32_t initrd_size,
177 uint32_t NVRAM_image,
178 int width, int height, int depth)
179 {
180 uint16_t crc;
181
182 /* Set parameters for Open Hack'Ware BIOS */
183 NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16);
184 NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */
185 NVRAM_set_word(nvram, 0x14, NVRAM_size);
186 NVRAM_set_string(nvram, 0x20, arch, 16);
187 NVRAM_set_lword(nvram, 0x30, RAM_size);
188 NVRAM_set_byte(nvram, 0x34, boot_device);
189 NVRAM_set_lword(nvram, 0x38, kernel_image);
190 NVRAM_set_lword(nvram, 0x3C, kernel_size);
191 if (cmdline) {
192 /* XXX: put the cmdline in NVRAM too ? */
193 pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR,
194 cmdline);
195 NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
196 NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
197 } else {
198 NVRAM_set_lword(nvram, 0x40, 0);
199 NVRAM_set_lword(nvram, 0x44, 0);
200 }
201 NVRAM_set_lword(nvram, 0x48, initrd_image);
202 NVRAM_set_lword(nvram, 0x4C, initrd_size);
203 NVRAM_set_lword(nvram, 0x50, NVRAM_image);
204
205 NVRAM_set_word(nvram, 0x54, width);
206 NVRAM_set_word(nvram, 0x56, height);
207 NVRAM_set_word(nvram, 0x58, depth);
208 crc = NVRAM_compute_crc(nvram, 0x00, 0xF8);
209 NVRAM_set_word(nvram, 0xFC, crc);
210
211 return 0;
212 }
213
214 static int prep_set_cmos_checksum(DeviceState *dev, void *opaque)
215 {
216 uint16_t checksum = *(uint16_t *)opaque;
217 ISADevice *rtc;
218
219 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
220 rtc = ISA_DEVICE(dev);
221 rtc_set_memory(rtc, 0x2e, checksum & 0xff);
222 rtc_set_memory(rtc, 0x3e, checksum & 0xff);
223 rtc_set_memory(rtc, 0x2f, checksum >> 8);
224 rtc_set_memory(rtc, 0x3f, checksum >> 8);
225
226 object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(rtc),
227 "date");
228 }
229 return 0;
230 }
231
232 static void ibm_40p_init(MachineState *machine)
233 {
234 const char *bios_name = machine->firmware ?: "openbios-ppc";
235 CPUPPCState *env = NULL;
236 uint16_t cmos_checksum;
237 PowerPCCPU *cpu;
238 DeviceState *dev, *i82378_dev;
239 SysBusDevice *pcihost, *s;
240 Nvram *m48t59 = NULL;
241 PCIBus *pci_bus;
242 ISADevice *isa_dev;
243 ISABus *isa_bus;
244 void *fw_cfg;
245 int i;
246 uint32_t kernel_base = 0, initrd_base = 0;
247 long kernel_size = 0, initrd_size = 0;
248 char boot_device;
249
250 /* init CPU */
251 cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
252 env = &cpu->env;
253 if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
254 error_report("only 6xx bus is supported on this machine");
255 exit(1);
256 }
257
258 /* Set time-base frequency to 100 Mhz */
259 cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
260 qemu_register_reset(ppc_prep_reset, cpu);
261
262 /* PCI host */
263 dev = qdev_new("raven-pcihost");
264 qdev_prop_set_string(dev, "bios-name", bios_name);
265 qdev_prop_set_uint32(dev, "elf-machine", PPC_ELF_MACHINE);
266 pcihost = SYS_BUS_DEVICE(dev);
267 object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev));
268 sysbus_realize_and_unref(pcihost, &error_fatal);
269 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0"));
270 if (!pci_bus) {
271 error_report("could not create PCI host controller");
272 exit(1);
273 }
274
275 /* PCI -> ISA bridge */
276 i82378_dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(11, 0), "i82378"));
277 qdev_connect_gpio_out(i82378_dev, 0,
278 cpu->env.irq_inputs[PPC6xx_INPUT_INT]);
279 sysbus_connect_irq(pcihost, 0, qdev_get_gpio_in(i82378_dev, 15));
280 isa_bus = ISA_BUS(qdev_get_child_bus(i82378_dev, "isa.0"));
281
282 /* Memory controller */
283 isa_dev = isa_new("rs6000-mc");
284 dev = DEVICE(isa_dev);
285 qdev_prop_set_uint32(dev, "ram-size", machine->ram_size);
286 isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
287
288 /* RTC */
289 isa_dev = isa_new(TYPE_MC146818_RTC);
290 dev = DEVICE(isa_dev);
291 qdev_prop_set_int32(dev, "base_year", 1900);
292 isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
293
294 /* initialize CMOS checksums */
295 cmos_checksum = 0x6aa9;
296 qbus_walk_children(BUS(isa_bus), prep_set_cmos_checksum, NULL, NULL, NULL,
297 &cmos_checksum);
298
299 /* add some more devices */
300 if (defaults_enabled()) {
301 m48t59 = NVRAM(isa_create_simple(isa_bus, "isa-m48t59"));
302
303 isa_dev = isa_new("cs4231a");
304 dev = DEVICE(isa_dev);
305 qdev_prop_set_uint32(dev, "iobase", 0x830);
306 qdev_prop_set_uint32(dev, "irq", 10);
307 isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
308
309 isa_dev = isa_new("pc87312");
310 dev = DEVICE(isa_dev);
311 qdev_prop_set_uint32(dev, "config", 12);
312 isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
313
314 isa_dev = isa_new("prep-systemio");
315 dev = DEVICE(isa_dev);
316 qdev_prop_set_uint32(dev, "ibm-planar-id", 0xfc);
317 qdev_prop_set_uint32(dev, "equipment", 0xc0);
318 isa_realize_and_unref(isa_dev, isa_bus, &error_fatal);
319
320 dev = DEVICE(pci_create_simple(pci_bus, PCI_DEVFN(1, 0),
321 "lsi53c810"));
322 lsi53c8xx_handle_legacy_cmdline(dev);
323 qdev_connect_gpio_out(dev, 0, qdev_get_gpio_in(i82378_dev, 13));
324
325 /* XXX: s3-trio at PCI_DEVFN(2, 0) */
326 pci_vga_init(pci_bus);
327
328 for (i = 0; i < nb_nics; i++) {
329 pci_nic_init_nofail(&nd_table[i], pci_bus, "pcnet",
330 i == 0 ? "3" : NULL);
331 }
332 }
333
334 /* Prepare firmware configuration for OpenBIOS */
335 dev = qdev_new(TYPE_FW_CFG_MEM);
336 fw_cfg = FW_CFG(dev);
337 qdev_prop_set_uint32(dev, "data_width", 1);
338 qdev_prop_set_bit(dev, "dma_enabled", false);
339 object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG,
340 OBJECT(fw_cfg));
341 s = SYS_BUS_DEVICE(dev);
342 sysbus_realize_and_unref(s, &error_fatal);
343 sysbus_mmio_map(s, 0, CFG_ADDR);
344 sysbus_mmio_map(s, 1, CFG_ADDR + 2);
345
346 if (machine->kernel_filename) {
347 /* load kernel */
348 kernel_base = KERNEL_LOAD_ADDR;
349 kernel_size = load_image_targphys(machine->kernel_filename,
350 kernel_base,
351 machine->ram_size - kernel_base);
352 if (kernel_size < 0) {
353 error_report("could not load kernel '%s'",
354 machine->kernel_filename);
355 exit(1);
356 }
357 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base);
358 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
359 /* load initrd */
360 if (machine->initrd_filename) {
361 initrd_base = INITRD_LOAD_ADDR;
362 initrd_size = load_image_targphys(machine->initrd_filename,
363 initrd_base,
364 machine->ram_size - initrd_base);
365 if (initrd_size < 0) {
366 error_report("could not load initial ram disk '%s'",
367 machine->initrd_filename);
368 exit(1);
369 }
370 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_base);
371 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
372 }
373 if (machine->kernel_cmdline && *machine->kernel_cmdline) {
374 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
375 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE,
376 machine->kernel_cmdline);
377 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA,
378 machine->kernel_cmdline);
379 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
380 strlen(machine->kernel_cmdline) + 1);
381 }
382 boot_device = 'm';
383 } else {
384 boot_device = machine->boot_config.order[0];
385 }
386
387 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
388 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
389 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_PREP);
390
391 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_WIDTH, graphic_width);
392 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_HEIGHT, graphic_height);
393 fw_cfg_add_i16(fw_cfg, FW_CFG_PPC_DEPTH, graphic_depth);
394
395 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_IS_KVM, kvm_enabled());
396 if (kvm_enabled()) {
397 uint8_t *hypercall;
398
399 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, kvmppc_get_tbfreq());
400 hypercall = g_malloc(16);
401 kvmppc_get_hypercall(env, hypercall, 16);
402 fw_cfg_add_bytes(fw_cfg, FW_CFG_PPC_KVM_HC, hypercall, 16);
403 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_KVM_PID, getpid());
404 } else {
405 fw_cfg_add_i32(fw_cfg, FW_CFG_PPC_TBFREQ, NANOSECONDS_PER_SECOND);
406 }
407 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device);
408 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
409
410 /* Prepare firmware configuration for Open Hack'Ware */
411 if (m48t59) {
412 PPC_NVRAM_set_params(m48t59, NVRAM_SIZE, "PREP", machine->ram_size,
413 boot_device,
414 kernel_base, kernel_size,
415 machine->kernel_cmdline,
416 initrd_base, initrd_size,
417 /* XXX: need an option to load a NVRAM image */
418 0,
419 graphic_width, graphic_height, graphic_depth);
420 }
421 }
422
423 static void ibm_40p_machine_init(MachineClass *mc)
424 {
425 mc->desc = "IBM RS/6000 7020 (40p)",
426 mc->init = ibm_40p_init;
427 mc->max_cpus = 1;
428 mc->default_ram_size = 128 * MiB;
429 mc->block_default_type = IF_SCSI;
430 mc->default_boot_order = "c";
431 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("604");
432 mc->default_display = "std";
433 }
434
435 DEFINE_MACHINE("40p", ibm_40p_machine_init)