Merge tag 'pull-la-20220805' of https://gitlab.com/rth7680/qemu into staging
[qemu.git] / hw / ppc / sam460ex.c
1 /*
2 * QEMU aCube Sam460ex board emulation
3 *
4 * Copyright (c) 2012 Fran├žois Revol
5 * Copyright (c) 2016-2019 BALATON Zoltan
6 *
7 * This file is derived from hw/ppc440_bamboo.c,
8 * the copyright for that material belongs to the original owners.
9 *
10 * This work is licensed under the GNU GPL license version 2 or later.
11 *
12 */
13
14 #include "qemu/osdep.h"
15 #include "qemu/units.h"
16 #include "qemu/datadir.h"
17 #include "qemu/error-report.h"
18 #include "qapi/error.h"
19 #include "hw/boards.h"
20 #include "sysemu/kvm.h"
21 #include "kvm_ppc.h"
22 #include "sysemu/device_tree.h"
23 #include "sysemu/block-backend.h"
24 #include "hw/loader.h"
25 #include "elf.h"
26 #include "exec/memory.h"
27 #include "ppc440.h"
28 #include "ppc405.h"
29 #include "hw/block/flash.h"
30 #include "sysemu/sysemu.h"
31 #include "sysemu/reset.h"
32 #include "hw/sysbus.h"
33 #include "hw/char/serial.h"
34 #include "hw/i2c/ppc4xx_i2c.h"
35 #include "hw/i2c/smbus_eeprom.h"
36 #include "hw/usb/hcd-ehci.h"
37 #include "hw/ppc/fdt.h"
38 #include "hw/qdev-properties.h"
39 #include "hw/intc/ppc-uic.h"
40
41 #include <libfdt.h>
42
43 #define BINARY_DEVICE_TREE_FILE "canyonlands.dtb"
44 #define UBOOT_FILENAME "u-boot-sam460-20100605.bin"
45 /* to extract the official U-Boot bin from the updater: */
46 /* dd bs=1 skip=$(($(stat -c '%s' updater/updater-460) - 0x80000)) \
47 if=updater/updater-460 of=u-boot-sam460-20100605.bin */
48
49 /* from Sam460 U-Boot include/configs/Sam460ex.h */
50 #define FLASH_BASE 0xfff00000
51 #define FLASH_BASE_H 0x4
52 #define FLASH_SIZE (1 * MiB)
53 #define UBOOT_LOAD_BASE 0xfff80000
54 #define UBOOT_SIZE 0x00080000
55 #define UBOOT_ENTRY 0xfffffffc
56
57 /* from U-Boot */
58 #define EPAPR_MAGIC (0x45504150)
59 #define KERNEL_ADDR 0x1000000
60 #define FDT_ADDR 0x1800000
61 #define RAMDISK_ADDR 0x1900000
62
63 /* Sam460ex IRQ MAP:
64 IRQ0 = ETH_INT
65 IRQ1 = FPGA_INT
66 IRQ2 = PCI_INT (PCIA, PCIB, PCIC, PCIB)
67 IRQ3 = FPGA_INT2
68 IRQ11 = RTC_INT
69 IRQ12 = SM502_INT
70 */
71
72 #define CPU_FREQ 1150000000
73 #define PLB_FREQ 230000000
74 #define OPB_FREQ 115000000
75 #define EBC_FREQ 115000000
76 #define UART_FREQ 11059200
77 #define SDRAM_NR_BANKS 4
78
79 /* The SoC could also handle 4 GiB but firmware does not work with that. */
80 /* Maybe it overflows a signed 32 bit number somewhere? */
81 static const ram_addr_t ppc460ex_sdram_bank_sizes[] = {
82 2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB, 64 * MiB,
83 32 * MiB, 0
84 };
85
86 struct boot_info {
87 uint32_t dt_base;
88 uint32_t dt_size;
89 uint32_t entry;
90 };
91
92 static int sam460ex_load_uboot(void)
93 {
94 /*
95 * This first creates 1MiB of flash memory mapped at the end of
96 * the 32-bit address space (0xFFF00000..0xFFFFFFFF).
97 *
98 * If_PFLASH unit 0 is defined, the flash memory is initialized
99 * from that block backend.
100 *
101 * Else, it's initialized to zero. And then 512KiB of ROM get
102 * mapped on top of its second half (0xFFF80000..0xFFFFFFFF),
103 * initialized from u-boot-sam460-20100605.bin.
104 *
105 * This doesn't smell right.
106 *
107 * The physical hardware appears to have 512KiB flash memory.
108 *
109 * TODO Figure out what we really need here, and clean this up.
110 */
111
112 DriveInfo *dinfo;
113
114 dinfo = drive_get(IF_PFLASH, 0, 0);
115 if (!pflash_cfi01_register(FLASH_BASE | ((hwaddr)FLASH_BASE_H << 32),
116 "sam460ex.flash", FLASH_SIZE,
117 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
118 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1)) {
119 error_report("Error registering flash memory");
120 /* XXX: return an error instead? */
121 exit(1);
122 }
123
124 if (!dinfo) {
125 /*error_report("No flash image given with the 'pflash' parameter,"
126 " using default u-boot image");*/
127 rom_add_file_fixed(UBOOT_FILENAME,
128 UBOOT_LOAD_BASE | ((hwaddr)FLASH_BASE_H << 32),
129 -1);
130 }
131
132 return 0;
133 }
134
135 static int sam460ex_load_device_tree(hwaddr addr,
136 uint32_t ramsize,
137 hwaddr initrd_base,
138 hwaddr initrd_size,
139 const char *kernel_cmdline)
140 {
141 uint32_t mem_reg_property[] = { 0, 0, cpu_to_be32(ramsize) };
142 char *filename;
143 int fdt_size;
144 void *fdt;
145 uint32_t tb_freq = CPU_FREQ;
146 uint32_t clock_freq = CPU_FREQ;
147 int offset;
148
149 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
150 if (!filename) {
151 error_report("Couldn't find dtb file `%s'", BINARY_DEVICE_TREE_FILE);
152 exit(1);
153 }
154 fdt = load_device_tree(filename, &fdt_size);
155 if (!fdt) {
156 error_report("Couldn't load dtb file `%s'", filename);
157 g_free(filename);
158 exit(1);
159 }
160 g_free(filename);
161
162 /* Manipulate device tree in memory. */
163
164 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property,
165 sizeof(mem_reg_property));
166
167 /* default FDT doesn't have a /chosen node... */
168 qemu_fdt_add_subnode(fdt, "/chosen");
169
170 qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", initrd_base);
171
172 qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
173 (initrd_base + initrd_size));
174
175 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", kernel_cmdline);
176
177 /* Copy data from the host device tree into the guest. Since the guest can
178 * directly access the timebase without host involvement, we must expose
179 * the correct frequencies. */
180 if (kvm_enabled()) {
181 tb_freq = kvmppc_get_tbfreq();
182 clock_freq = kvmppc_get_clockfreq();
183 }
184
185 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "clock-frequency",
186 clock_freq);
187 qemu_fdt_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency",
188 tb_freq);
189
190 /* Remove cpm node if it exists (it is not emulated) */
191 offset = fdt_path_offset(fdt, "/cpm");
192 if (offset >= 0) {
193 _FDT(fdt_nop_node(fdt, offset));
194 }
195
196 /* set serial port clocks */
197 offset = fdt_node_offset_by_compatible(fdt, -1, "ns16550");
198 while (offset >= 0) {
199 _FDT(fdt_setprop_cell(fdt, offset, "clock-frequency", UART_FREQ));
200 offset = fdt_node_offset_by_compatible(fdt, offset, "ns16550");
201 }
202
203 /* some more clocks */
204 qemu_fdt_setprop_cell(fdt, "/plb", "clock-frequency",
205 PLB_FREQ);
206 qemu_fdt_setprop_cell(fdt, "/plb/opb", "clock-frequency",
207 OPB_FREQ);
208 qemu_fdt_setprop_cell(fdt, "/plb/opb/ebc", "clock-frequency",
209 EBC_FREQ);
210
211 rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
212 g_free(fdt);
213
214 return fdt_size;
215 }
216
217 /* Create reset TLB entries for BookE, mapping only the flash memory. */
218 static void mmubooke_create_initial_mapping_uboot(CPUPPCState *env)
219 {
220 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
221
222 /* on reset the flash is mapped by a shadow TLB,
223 * but since we don't implement them we need to use
224 * the same values U-Boot will use to avoid a fault.
225 */
226 tlb->attr = 0;
227 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
228 tlb->size = 0x10000000; /* up to 0xffffffff */
229 tlb->EPN = 0xf0000000 & TARGET_PAGE_MASK;
230 tlb->RPN = (0xf0000000 & TARGET_PAGE_MASK) | 0x4;
231 tlb->PID = 0;
232 }
233
234 /* Create reset TLB entries for BookE, spanning the 32bit addr space. */
235 static void mmubooke_create_initial_mapping(CPUPPCState *env,
236 target_ulong va,
237 hwaddr pa)
238 {
239 ppcemb_tlb_t *tlb = &env->tlb.tlbe[0];
240
241 tlb->attr = 0;
242 tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4);
243 tlb->size = 1 << 31; /* up to 0x80000000 */
244 tlb->EPN = va & TARGET_PAGE_MASK;
245 tlb->RPN = pa & TARGET_PAGE_MASK;
246 tlb->PID = 0;
247 }
248
249 static void main_cpu_reset(void *opaque)
250 {
251 PowerPCCPU *cpu = opaque;
252 CPUPPCState *env = &cpu->env;
253 struct boot_info *bi = env->load_info;
254
255 cpu_reset(CPU(cpu));
256
257 /* either we have a kernel to boot or we jump to U-Boot */
258 if (bi->entry != UBOOT_ENTRY) {
259 env->gpr[1] = (16 * MiB) - 8;
260 env->gpr[3] = FDT_ADDR;
261 env->nip = bi->entry;
262
263 /* Create a mapping for the kernel. */
264 mmubooke_create_initial_mapping(env, 0, 0);
265 env->gpr[6] = tswap32(EPAPR_MAGIC);
266 env->gpr[7] = (16 * MiB) - 8; /* bi->ima_size; */
267
268 } else {
269 env->nip = UBOOT_ENTRY;
270 mmubooke_create_initial_mapping_uboot(env);
271 }
272 }
273
274 static void sam460ex_init(MachineState *machine)
275 {
276 MemoryRegion *address_space_mem = get_system_memory();
277 MemoryRegion *isa = g_new(MemoryRegion, 1);
278 MemoryRegion *ram_memories = g_new(MemoryRegion, SDRAM_NR_BANKS);
279 hwaddr ram_bases[SDRAM_NR_BANKS] = {0};
280 hwaddr ram_sizes[SDRAM_NR_BANKS] = {0};
281 MemoryRegion *l2cache_ram = g_new(MemoryRegion, 1);
282 DeviceState *uic[4];
283 qemu_irq mal_irqs[4];
284 int i;
285 PCIBus *pci_bus;
286 PowerPCCPU *cpu;
287 CPUPPCState *env;
288 I2CBus *i2c;
289 hwaddr entry = UBOOT_ENTRY;
290 target_long initrd_size = 0;
291 DeviceState *dev;
292 SysBusDevice *sbdev;
293 struct boot_info *boot_info;
294 uint8_t *spd_data;
295 int success;
296
297 cpu = POWERPC_CPU(cpu_create(machine->cpu_type));
298 env = &cpu->env;
299 if (env->mmu_model != POWERPC_MMU_BOOKE) {
300 error_report("Only MMU model BookE is supported by this machine.");
301 exit(1);
302 }
303
304 qemu_register_reset(main_cpu_reset, cpu);
305 boot_info = g_malloc0(sizeof(*boot_info));
306 env->load_info = boot_info;
307
308 ppc_booke_timers_init(cpu, CPU_FREQ, 0);
309 ppc_dcr_init(env, NULL, NULL);
310
311 /* PLB arbitrer */
312 ppc4xx_plb_init(env);
313
314 /* interrupt controllers */
315 for (i = 0; i < ARRAY_SIZE(uic); i++) {
316 SysBusDevice *sbd;
317 /*
318 * UICs 1, 2 and 3 are cascaded through UIC 0.
319 * input_ints[n] is the interrupt number on UIC 0 which
320 * the INT output of UIC n is connected to. The CINT output
321 * of UIC n connects to input_ints[n] + 1.
322 * The entry in input_ints[] for UIC 0 is ignored, because UIC 0's
323 * INT and CINT outputs are connected to the CPU.
324 */
325 const int input_ints[] = { -1, 30, 10, 16 };
326
327 uic[i] = qdev_new(TYPE_PPC_UIC);
328 sbd = SYS_BUS_DEVICE(uic[i]);
329
330 qdev_prop_set_uint32(uic[i], "dcr-base", 0xc0 + i * 0x10);
331 object_property_set_link(OBJECT(uic[i]), "cpu", OBJECT(cpu),
332 &error_fatal);
333 sysbus_realize_and_unref(sbd, &error_fatal);
334
335 if (i == 0) {
336 sysbus_connect_irq(sbd, PPCUIC_OUTPUT_INT,
337 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]);
338 sysbus_connect_irq(sbd, PPCUIC_OUTPUT_CINT,
339 ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]);
340 } else {
341 sysbus_connect_irq(sbd, PPCUIC_OUTPUT_INT,
342 qdev_get_gpio_in(uic[0], input_ints[i]));
343 sysbus_connect_irq(sbd, PPCUIC_OUTPUT_CINT,
344 qdev_get_gpio_in(uic[0], input_ints[i] + 1));
345 }
346 }
347
348 /* SDRAM controller */
349 /* put all RAM on first bank because board has one slot
350 * and firmware only checks that */
351 ppc4xx_sdram_banks(machine->ram, 1, ram_memories, ram_bases, ram_sizes,
352 ppc460ex_sdram_bank_sizes);
353
354 /* FIXME: does 460EX have ECC interrupts? */
355 ppc440_sdram_init(env, SDRAM_NR_BANKS, ram_memories,
356 ram_bases, ram_sizes, 1);
357
358 /* IIC controllers and devices */
359 dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600700,
360 qdev_get_gpio_in(uic[0], 2));
361 i2c = PPC4xx_I2C(dev)->bus;
362 /* SPD EEPROM on RAM module */
363 spd_data = spd_data_generate(ram_sizes[0] < 128 * MiB ? DDR : DDR2,
364 ram_sizes[0]);
365 spd_data[20] = 4; /* SO-DIMM module */
366 smbus_eeprom_init_one(i2c, 0x50, spd_data);
367 /* RTC */
368 i2c_slave_create_simple(i2c, "m41t80", 0x68);
369
370 dev = sysbus_create_simple(TYPE_PPC4xx_I2C, 0x4ef600800,
371 qdev_get_gpio_in(uic[0], 3));
372
373 /* External bus controller */
374 ppc405_ebc_init(env);
375
376 /* CPR */
377 ppc4xx_cpr_init(env);
378
379 /* PLB to AHB bridge */
380 ppc4xx_ahb_init(env);
381
382 /* System DCRs */
383 ppc4xx_sdr_init(env);
384
385 /* MAL */
386 for (i = 0; i < ARRAY_SIZE(mal_irqs); i++) {
387 mal_irqs[0] = qdev_get_gpio_in(uic[2], 3 + i);
388 }
389 ppc4xx_mal_init(env, 4, 16, mal_irqs);
390
391 /* DMA */
392 ppc4xx_dma_init(env, 0x200);
393
394 /* 256K of L2 cache as memory */
395 ppc4xx_l2sram_init(env);
396 /* FIXME: remove this after fixing l2sram mapping in ppc440_uc.c? */
397 memory_region_init_ram(l2cache_ram, NULL, "ppc440.l2cache_ram", 256 * KiB,
398 &error_abort);
399 memory_region_add_subregion(address_space_mem, 0x400000000LL, l2cache_ram);
400
401 /* USB */
402 sysbus_create_simple(TYPE_PPC4xx_EHCI, 0x4bffd0400,
403 qdev_get_gpio_in(uic[2], 29));
404 dev = qdev_new("sysbus-ohci");
405 qdev_prop_set_string(dev, "masterbus", "usb-bus.0");
406 qdev_prop_set_uint32(dev, "num-ports", 6);
407 sbdev = SYS_BUS_DEVICE(dev);
408 sysbus_realize_and_unref(sbdev, &error_fatal);
409 sysbus_mmio_map(sbdev, 0, 0x4bffd0000);
410 sysbus_connect_irq(sbdev, 0, qdev_get_gpio_in(uic[2], 30));
411 usb_create_simple(usb_bus_find(-1), "usb-kbd");
412 usb_create_simple(usb_bus_find(-1), "usb-mouse");
413
414 /* PCI bus */
415 ppc460ex_pcie_init(env);
416 /* All PCI irqs are connected to the same UIC pin (cf. UBoot source) */
417 dev = sysbus_create_simple("ppc440-pcix-host", 0xc0ec00000,
418 qdev_get_gpio_in(uic[1], 0));
419 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci.0"));
420
421 memory_region_init_alias(isa, NULL, "isa_mmio", get_system_io(),
422 0, 0x10000);
423 memory_region_add_subregion(get_system_memory(), 0xc08000000, isa);
424
425 /* PCI devices */
426 pci_create_simple(pci_bus, PCI_DEVFN(6, 0), "sm501");
427 /* SoC has a single SATA port but we don't emulate that yet
428 * However, firmware and usual clients have driver for SiI311x
429 * so add one for convenience by default */
430 if (defaults_enabled()) {
431 pci_create_simple(pci_bus, -1, "sii3112");
432 }
433
434 /* SoC has 4 UARTs
435 * but board has only one wired and two are present in fdt */
436 if (serial_hd(0) != NULL) {
437 serial_mm_init(address_space_mem, 0x4ef600300, 0,
438 qdev_get_gpio_in(uic[1], 1),
439 PPC_SERIAL_MM_BAUDBASE, serial_hd(0),
440 DEVICE_BIG_ENDIAN);
441 }
442 if (serial_hd(1) != NULL) {
443 serial_mm_init(address_space_mem, 0x4ef600400, 0,
444 qdev_get_gpio_in(uic[0], 1),
445 PPC_SERIAL_MM_BAUDBASE, serial_hd(1),
446 DEVICE_BIG_ENDIAN);
447 }
448
449 /* Load U-Boot image. */
450 if (!machine->kernel_filename) {
451 success = sam460ex_load_uboot();
452 if (success < 0) {
453 error_report("could not load firmware");
454 exit(1);
455 }
456 }
457
458 /* Load kernel. */
459 if (machine->kernel_filename) {
460 hwaddr loadaddr = LOAD_UIMAGE_LOADADDR_INVALID;
461 success = load_uimage(machine->kernel_filename, &entry, &loadaddr,
462 NULL, NULL, NULL);
463 if (success < 0) {
464 uint64_t elf_entry;
465
466 success = load_elf(machine->kernel_filename, NULL, NULL, NULL,
467 &elf_entry, NULL, NULL, NULL,
468 1, PPC_ELF_MACHINE, 0, 0);
469 entry = elf_entry;
470 }
471 /* XXX try again as binary */
472 if (success < 0) {
473 error_report("could not load kernel '%s'",
474 machine->kernel_filename);
475 exit(1);
476 }
477 }
478
479 /* Load initrd. */
480 if (machine->initrd_filename) {
481 initrd_size = load_image_targphys(machine->initrd_filename,
482 RAMDISK_ADDR,
483 machine->ram_size - RAMDISK_ADDR);
484 if (initrd_size < 0) {
485 error_report("could not load ram disk '%s' at %x",
486 machine->initrd_filename, RAMDISK_ADDR);
487 exit(1);
488 }
489 }
490
491 /* If we're loading a kernel directly, we must load the device tree too. */
492 if (machine->kernel_filename) {
493 int dt_size;
494
495 dt_size = sam460ex_load_device_tree(FDT_ADDR, machine->ram_size,
496 RAMDISK_ADDR, initrd_size,
497 machine->kernel_cmdline);
498
499 boot_info->dt_base = FDT_ADDR;
500 boot_info->dt_size = dt_size;
501 }
502
503 boot_info->entry = entry;
504 }
505
506 static void sam460ex_machine_init(MachineClass *mc)
507 {
508 mc->desc = "aCube Sam460ex";
509 mc->init = sam460ex_init;
510 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("460exb");
511 mc->default_ram_size = 512 * MiB;
512 mc->default_ram_id = "ppc4xx.sdram";
513 }
514
515 DEFINE_MACHINE("sam460ex", sam460ex_machine_init)